1 /* Wrapper for DMA channel allocator that starts clocks etc */
3 #include <linux/kernel.h>
4 #include <linux/spinlock.h>
6 #include <hwregs/reg_map.h>
7 #include <hwregs/reg_rdwr.h>
8 #include <hwregs/marb_defs.h>
9 #include <hwregs/config_defs.h>
10 #include <hwregs/strmux_defs.h>
11 #include <linux/errno.h>
12 #include <mach/arbiter.h>
14 static char used_dma_channels[MAX_DMA_CHANNELS];
15 static const char *used_dma_channels_users[MAX_DMA_CHANNELS];
17 static DEFINE_SPINLOCK(dma_lock);
19 int crisv32_request_dma(unsigned int dmanr, const char *device_id,
20 unsigned options, unsigned int bandwidth,
24 reg_config_rw_clk_ctrl clk_ctrl;
25 reg_strmux_rw_cfg strmux_cfg;
27 if (crisv32_arbiter_allocate_bandwidth(dmanr,
28 options & DMA_INT_MEM ?
29 INT_REGION : EXT_REGION,
33 spin_lock_irqsave(&dma_lock, flags);
35 if (used_dma_channels[dmanr]) {
36 spin_unlock_irqrestore(&dma_lock, flags);
37 if (options & DMA_VERBOSE_ON_ERROR) {
38 printk(KERN_ERR "Failed to request DMA %i for %s, "
39 "already allocated by %s\n",
42 used_dma_channels_users[dmanr]);
44 if (options & DMA_PANIC_ON_ERROR)
45 panic("request_dma error!");
46 spin_unlock_irqrestore(&dma_lock, flags);
49 clk_ctrl = REG_RD(config, regi_config, rw_clk_ctrl);
50 strmux_cfg = REG_RD(strmux, regi_strmux, rw_cfg);
55 clk_ctrl.dma01_eth0 = 1;
71 clk_ctrl.dma89_strcop = 1;
73 #if MAX_DMA_CHANNELS-1 != 9
77 spin_unlock_irqrestore(&dma_lock, flags);
78 if (options & DMA_VERBOSE_ON_ERROR) {
79 printk(KERN_ERR "Failed to request DMA %i for %s, "
81 dmanr, device_id, MAX_DMA_CHANNELS - 1);
84 if (options & DMA_PANIC_ON_ERROR)
85 panic("request_dma error!");
92 strmux_cfg.dma0 = regk_strmux_eth0;
94 strmux_cfg.dma1 = regk_strmux_eth0;
96 panic("Invalid DMA channel for eth0\n");
100 strmux_cfg.dma6 = regk_strmux_eth1;
102 strmux_cfg.dma7 = regk_strmux_eth1;
104 panic("Invalid DMA channel for eth1\n");
108 strmux_cfg.dma2 = regk_strmux_iop0;
110 strmux_cfg.dma3 = regk_strmux_iop0;
112 panic("Invalid DMA channel for iop0\n");
116 strmux_cfg.dma4 = regk_strmux_iop1;
118 strmux_cfg.dma5 = regk_strmux_iop1;
120 panic("Invalid DMA channel for iop1\n");
124 strmux_cfg.dma6 = regk_strmux_ser0;
126 strmux_cfg.dma7 = regk_strmux_ser0;
128 panic("Invalid DMA channel for ser0\n");
132 strmux_cfg.dma4 = regk_strmux_ser1;
134 strmux_cfg.dma5 = regk_strmux_ser1;
136 panic("Invalid DMA channel for ser1\n");
140 strmux_cfg.dma2 = regk_strmux_ser2;
142 strmux_cfg.dma3 = regk_strmux_ser2;
144 panic("Invalid DMA channel for ser2\n");
148 strmux_cfg.dma8 = regk_strmux_ser3;
150 strmux_cfg.dma9 = regk_strmux_ser3;
152 panic("Invalid DMA channel for ser3\n");
156 strmux_cfg.dma4 = regk_strmux_sser0;
158 strmux_cfg.dma5 = regk_strmux_sser0;
160 panic("Invalid DMA channel for sser0\n");
164 strmux_cfg.dma6 = regk_strmux_sser1;
166 strmux_cfg.dma7 = regk_strmux_sser1;
168 panic("Invalid DMA channel for sser1\n");
172 strmux_cfg.dma2 = regk_strmux_ata;
174 strmux_cfg.dma3 = regk_strmux_ata;
176 panic("Invalid DMA channel for ata\n");
180 strmux_cfg.dma8 = regk_strmux_strcop;
182 strmux_cfg.dma9 = regk_strmux_strcop;
184 panic("Invalid DMA channel for strp\n");
188 strmux_cfg.dma6 = regk_strmux_ext0;
190 panic("Invalid DMA channel for ext0\n");
194 strmux_cfg.dma7 = regk_strmux_ext1;
196 panic("Invalid DMA channel for ext1\n");
200 strmux_cfg.dma2 = regk_strmux_ext2;
202 strmux_cfg.dma8 = regk_strmux_ext2;
204 panic("Invalid DMA channel for ext2\n");
208 strmux_cfg.dma3 = regk_strmux_ext3;
210 strmux_cfg.dma9 = regk_strmux_ext2;
212 panic("Invalid DMA channel for ext2\n");
216 used_dma_channels[dmanr] = 1;
217 used_dma_channels_users[dmanr] = device_id;
218 REG_WR(config, regi_config, rw_clk_ctrl, clk_ctrl);
219 REG_WR(strmux, regi_strmux, rw_cfg, strmux_cfg);
220 spin_unlock_irqrestore(&dma_lock, flags);
224 void crisv32_free_dma(unsigned int dmanr)
226 spin_lock(&dma_lock);
227 used_dma_channels[dmanr] = 0;
228 spin_unlock(&dma_lock);