2 * Allocator for I/O pins. All pins are allocated to GPIO at bootup.
3 * Unassigned pins and GPIO pins can be allocated to a fixed interface
4 * or the I/O processor instead.
6 * Copyright (c) 2005-2007 Axis Communications AB.
9 #include <linux/init.h>
10 #include <linux/errno.h>
11 #include <linux/kernel.h>
12 #include <linux/string.h>
13 #include <linux/spinlock.h>
14 #include <hwregs/reg_map.h>
15 #include <hwregs/reg_rdwr.h>
17 #include <hwregs/pinmux_defs.h>
18 #include <hwregs/clkgen_defs.h>
26 static char pins[PINS];
27 static DEFINE_SPINLOCK(pinmux_lock);
29 static void crisv32_pinmux_set(int port);
32 crisv32_pinmux_init(void)
34 static int initialized;
38 REG_WR_INT(pinmux, regi_pinmux, rw_hwprot, 0);
39 crisv32_pinmux_alloc(PORT_A, 0, 31, pinmux_gpio);
40 crisv32_pinmux_alloc(PORT_B, 0, 31, pinmux_gpio);
41 crisv32_pinmux_alloc(PORT_C, 0, 15, pinmux_gpio);
48 crisv32_pinmux_alloc(int port, int first_pin, int last_pin, enum pin_mode mode)
53 crisv32_pinmux_init();
58 spin_lock_irqsave(&pinmux_lock, flags);
60 for (i = first_pin; i <= last_pin; i++) {
61 if ((pins[port * PORT_PINS + i] != pinmux_none) &&
62 (pins[port * PORT_PINS + i] != pinmux_gpio) &&
63 (pins[port * PORT_PINS + i] != mode)) {
64 spin_unlock_irqrestore(&pinmux_lock, flags);
66 panic("Pinmux alloc failed!\n");
72 for (i = first_pin; i <= last_pin; i++)
73 pins[port * PORT_PINS + i] = mode;
75 crisv32_pinmux_set(port);
77 spin_unlock_irqrestore(&pinmux_lock, flags);
83 crisv32_pinmux_alloc_fixed(enum fixed_function function)
86 char saved[sizeof pins];
88 reg_pinmux_rw_hwprot hwprot;
89 reg_clkgen_rw_clk_ctrl clk_ctrl;
91 spin_lock_irqsave(&pinmux_lock, flags);
93 /* Save internal data for recovery */
94 memcpy(saved, pins, sizeof pins);
96 crisv32_pinmux_init(); /* must be done before we read rw_hwprot */
98 hwprot = REG_RD(pinmux, regi_pinmux, rw_hwprot);
99 clk_ctrl = REG_RD(clkgen, regi_clkgen, rw_clk_ctrl);
103 clk_ctrl.eth = regk_clkgen_yes;
104 clk_ctrl.dma0_1_eth = regk_clkgen_yes;
105 ret = crisv32_pinmux_alloc(PORT_B, 8, 23, pinmux_fixed);
106 ret |= crisv32_pinmux_alloc(PORT_B, 24, 25, pinmux_fixed);
107 hwprot.eth = hwprot.eth_mdio = regk_pinmux_yes;
110 ret = crisv32_pinmux_alloc(PORT_B, 0, 7, pinmux_fixed);
111 hwprot.geth = regk_pinmux_yes;
114 clk_ctrl.ccd_tg_100 = clk_ctrl.ccd_tg_200 = regk_clkgen_yes;
115 ret = crisv32_pinmux_alloc(PORT_B, 27, 29, pinmux_fixed);
116 hwprot.tg_clk = regk_pinmux_yes;
119 clk_ctrl.ccd_tg_100 = clk_ctrl.ccd_tg_200 = regk_clkgen_yes;
120 ret = crisv32_pinmux_alloc(PORT_B, 27, 31, pinmux_fixed);
121 ret |= crisv32_pinmux_alloc(PORT_C, 0, 15, pinmux_fixed);
122 hwprot.tg = hwprot.tg_clk = regk_pinmux_yes;
125 clk_ctrl.strdma0_2_video = regk_clkgen_yes;
126 ret = crisv32_pinmux_alloc(PORT_A, 8, 18, pinmux_fixed);
127 hwprot.vout = hwprot.vout_sync = regk_pinmux_yes;
130 clk_ctrl.sser_ser_dma6_7 = regk_clkgen_yes;
131 ret = crisv32_pinmux_alloc(PORT_A, 24, 25, pinmux_fixed);
132 hwprot.ser1 = regk_pinmux_yes;
135 clk_ctrl.sser_ser_dma6_7 = regk_clkgen_yes;
136 ret = crisv32_pinmux_alloc(PORT_A, 26, 27, pinmux_fixed);
137 hwprot.ser2 = regk_pinmux_yes;
140 clk_ctrl.sser_ser_dma6_7 = regk_clkgen_yes;
141 ret = crisv32_pinmux_alloc(PORT_A, 28, 29, pinmux_fixed);
142 hwprot.ser3 = regk_pinmux_yes;
145 clk_ctrl.sser_ser_dma6_7 = regk_clkgen_yes;
146 ret = crisv32_pinmux_alloc(PORT_A, 30, 31, pinmux_fixed);
147 hwprot.ser4 = regk_pinmux_yes;
150 clk_ctrl.sser_ser_dma6_7 = regk_clkgen_yes;
151 ret = crisv32_pinmux_alloc(PORT_A, 19, 23, pinmux_fixed);
152 hwprot.sser = regk_pinmux_yes;
155 hwprot.pio = regk_pinmux_yes;
159 ret = crisv32_pinmux_alloc(PORT_A, 30, 30, pinmux_fixed);
160 hwprot.pwm0 = regk_pinmux_yes;
163 ret = crisv32_pinmux_alloc(PORT_A, 31, 31, pinmux_fixed);
164 hwprot.pwm1 = regk_pinmux_yes;
167 ret = crisv32_pinmux_alloc(PORT_B, 26, 26, pinmux_fixed);
168 hwprot.pwm2 = regk_pinmux_yes;
171 ret = crisv32_pinmux_alloc(PORT_A, 0, 1, pinmux_fixed);
172 hwprot.i2c0 = regk_pinmux_yes;
175 ret = crisv32_pinmux_alloc(PORT_A, 2, 3, pinmux_fixed);
176 hwprot.i2c1 = regk_pinmux_yes;
178 case pinmux_i2c1_3wire:
179 ret = crisv32_pinmux_alloc(PORT_A, 2, 3, pinmux_fixed);
180 ret |= crisv32_pinmux_alloc(PORT_A, 7, 7, pinmux_fixed);
181 hwprot.i2c1 = hwprot.i2c1_sen = regk_pinmux_yes;
183 case pinmux_i2c1_sda1:
184 ret = crisv32_pinmux_alloc(PORT_A, 2, 4, pinmux_fixed);
185 hwprot.i2c1 = hwprot.i2c1_sda1 = regk_pinmux_yes;
187 case pinmux_i2c1_sda2:
188 ret = crisv32_pinmux_alloc(PORT_A, 2, 3, pinmux_fixed);
189 ret |= crisv32_pinmux_alloc(PORT_A, 5, 5, pinmux_fixed);
190 hwprot.i2c1 = hwprot.i2c1_sda2 = regk_pinmux_yes;
192 case pinmux_i2c1_sda3:
193 ret = crisv32_pinmux_alloc(PORT_A, 2, 3, pinmux_fixed);
194 ret |= crisv32_pinmux_alloc(PORT_A, 6, 6, pinmux_fixed);
195 hwprot.i2c1 = hwprot.i2c1_sda3 = regk_pinmux_yes;
203 REG_WR(pinmux, regi_pinmux, rw_hwprot, hwprot);
204 REG_WR(clkgen, regi_clkgen, rw_clk_ctrl, clk_ctrl);
206 memcpy(pins, saved, sizeof pins);
208 spin_unlock_irqrestore(&pinmux_lock, flags);
214 crisv32_pinmux_set(int port)
219 int pin = port * PORT_PINS;
221 for (i = 0; (i < PORT_PINS) && (pin < PINS); i++, pin++) {
222 if (pins[pin] == pinmux_gpio)
223 gpio_val |= (1 << i);
224 else if (pins[pin] == pinmux_iop)
228 REG_WRITE(int, regi_pinmux + REG_RD_ADDR_pinmux_rw_gio_pa + 4 * port,
230 REG_WRITE(int, regi_pinmux + REG_RD_ADDR_pinmux_rw_iop_pa + 4 * port,
234 crisv32_pinmux_dump();
239 crisv32_pinmux_dealloc(int port, int first_pin, int last_pin)
244 crisv32_pinmux_init();
246 if (port > PORTS || port < 0)
249 spin_lock_irqsave(&pinmux_lock, flags);
251 for (i = first_pin; i <= last_pin; i++)
252 pins[port * PORT_PINS + i] = pinmux_none;
254 crisv32_pinmux_set(port);
255 spin_unlock_irqrestore(&pinmux_lock, flags);
261 crisv32_pinmux_dealloc_fixed(enum fixed_function function)
264 char saved[sizeof pins];
266 reg_pinmux_rw_hwprot hwprot;
268 spin_lock_irqsave(&pinmux_lock, flags);
270 /* Save internal data for recovery */
271 memcpy(saved, pins, sizeof pins);
273 crisv32_pinmux_init(); /* must be done before we read rw_hwprot */
275 hwprot = REG_RD(pinmux, regi_pinmux, rw_hwprot);
279 ret = crisv32_pinmux_dealloc(PORT_B, 8, 23);
280 ret |= crisv32_pinmux_dealloc(PORT_B, 24, 25);
281 ret |= crisv32_pinmux_dealloc(PORT_B, 0, 7);
282 hwprot.eth = hwprot.eth_mdio = hwprot.geth = regk_pinmux_no;
285 ret = crisv32_pinmux_dealloc(PORT_B, 27, 29);
286 hwprot.tg_clk = regk_pinmux_no;
289 ret = crisv32_pinmux_dealloc(PORT_B, 27, 31);
290 ret |= crisv32_pinmux_dealloc(PORT_C, 0, 15);
291 hwprot.tg = hwprot.tg_clk = regk_pinmux_no;
294 ret = crisv32_pinmux_dealloc(PORT_A, 8, 18);
295 hwprot.vout = hwprot.vout_sync = regk_pinmux_no;
298 ret = crisv32_pinmux_dealloc(PORT_A, 24, 25);
299 hwprot.ser1 = regk_pinmux_no;
302 ret = crisv32_pinmux_dealloc(PORT_A, 26, 27);
303 hwprot.ser2 = regk_pinmux_no;
306 ret = crisv32_pinmux_dealloc(PORT_A, 28, 29);
307 hwprot.ser3 = regk_pinmux_no;
310 ret = crisv32_pinmux_dealloc(PORT_A, 30, 31);
311 hwprot.ser4 = regk_pinmux_no;
314 ret = crisv32_pinmux_dealloc(PORT_A, 19, 23);
315 hwprot.sser = regk_pinmux_no;
318 ret = crisv32_pinmux_dealloc(PORT_A, 30, 30);
319 hwprot.pwm0 = regk_pinmux_no;
322 ret = crisv32_pinmux_dealloc(PORT_A, 31, 31);
323 hwprot.pwm1 = regk_pinmux_no;
326 ret = crisv32_pinmux_dealloc(PORT_B, 26, 26);
327 hwprot.pwm2 = regk_pinmux_no;
330 ret = crisv32_pinmux_dealloc(PORT_A, 0, 1);
331 hwprot.i2c0 = regk_pinmux_no;
334 ret = crisv32_pinmux_dealloc(PORT_A, 2, 3);
335 hwprot.i2c1 = regk_pinmux_no;
337 case pinmux_i2c1_3wire:
338 ret = crisv32_pinmux_dealloc(PORT_A, 2, 3);
339 ret |= crisv32_pinmux_dealloc(PORT_A, 7, 7);
340 hwprot.i2c1 = hwprot.i2c1_sen = regk_pinmux_no;
342 case pinmux_i2c1_sda1:
343 ret = crisv32_pinmux_dealloc(PORT_A, 2, 4);
344 hwprot.i2c1_sda1 = regk_pinmux_no;
346 case pinmux_i2c1_sda2:
347 ret = crisv32_pinmux_dealloc(PORT_A, 2, 3);
348 ret |= crisv32_pinmux_dealloc(PORT_A, 5, 5);
349 hwprot.i2c1_sda2 = regk_pinmux_no;
351 case pinmux_i2c1_sda3:
352 ret = crisv32_pinmux_dealloc(PORT_A, 2, 3);
353 ret |= crisv32_pinmux_dealloc(PORT_A, 6, 6);
354 hwprot.i2c1_sda3 = regk_pinmux_no;
362 REG_WR(pinmux, regi_pinmux, rw_hwprot, hwprot);
364 memcpy(pins, saved, sizeof pins);
366 spin_unlock_irqrestore(&pinmux_lock, flags);
372 crisv32_pinmux_dump(void)
377 crisv32_pinmux_init();
379 for (i = 0; i < PORTS; i++) {
381 printk(KERN_DEBUG "Port %c\n", 'A'+i);
382 for (j = 0; (j < PORT_PINS) && (pin < PINS); j++, pin++)
384 " Pin %d = %d\n", j, pins[i * PORT_PINS + j]);
388 __initcall(crisv32_pinmux_init);