2 * debugfs interface to core/system MMRs
4 * Copyright 2007-2011 Analog Devices Inc.
6 * Licensed under the GPL-2 or later
9 #include <linux/debugfs.h>
11 #include <linux/kernel.h>
12 #include <linux/module.h>
14 #include <asm/blackfin.h>
16 #include <asm/gptimers.h>
17 #include <asm/bfin_can.h>
18 #include <asm/bfin_dma.h>
19 #include <asm/bfin_ppi.h>
20 #include <asm/bfin_serial.h>
21 #include <asm/bfin5xx_spi.h>
22 #include <asm/bfin_twi.h>
24 /* Common code defines PORT_MUX on us, so redirect the MMR back locally */
27 #define PORT_MUX BFIN_PORT_MUX
30 #define _d(name, bits, addr, perms) debugfs_create_x##bits(name, perms, parent, (u##bits *)(addr))
31 #define d(name, bits, addr) _d(name, bits, addr, S_IRUSR|S_IWUSR)
32 #define d_RO(name, bits, addr) _d(name, bits, addr, S_IRUSR)
33 #define d_WO(name, bits, addr) _d(name, bits, addr, S_IWUSR)
35 #define D_RO(name, bits) d_RO(#name, bits, name)
36 #define D_WO(name, bits) d_WO(#name, bits, name)
37 #define D32(name) d(#name, 32, name)
38 #define D16(name) d(#name, 16, name)
40 #define REGS_OFF(peri, mmr) offsetof(struct bfin_##peri##_regs, mmr)
41 #define __REGS(peri, sname, rname) \
43 struct bfin_##peri##_regs r; \
44 void *addr = (void *)(base + REGS_OFF(peri, rname)); \
45 strcpy(_buf, sname); \
46 if (sizeof(r.rname) == 2) \
47 debugfs_create_x16(buf, S_IRUSR|S_IWUSR, parent, addr); \
49 debugfs_create_x32(buf, S_IRUSR|S_IWUSR, parent, addr); \
51 #define REGS_STR_PFX(buf, pfx, num) \
54 sprintf(buf, #pfx "%i_", num) : \
55 sprintf(buf, #pfx "_")); \
57 #define REGS_STR_PFX_C(buf, pfx, num) \
60 sprintf(buf, #pfx "%c_", 'A' + num) : \
61 sprintf(buf, #pfx "_")); \
65 * Core registers (not memory mapped)
67 extern u32 last_seqstat;
69 static int debug_cclk_get(void *data, u64 *val)
74 DEFINE_SIMPLE_ATTRIBUTE(fops_debug_cclk, debug_cclk_get, NULL, "0x%08llx\n");
76 static int debug_sclk_get(void *data, u64 *val)
81 DEFINE_SIMPLE_ATTRIBUTE(fops_debug_sclk, debug_sclk_get, NULL, "0x%08llx\n");
83 #define DEFINE_SYSREG(sr, pre, post) \
84 static int sysreg_##sr##_get(void *data, u64 *val) \
88 __asm__ __volatile__("%0 = " #sr ";" : "=d"(tmp)); \
92 static int sysreg_##sr##_set(void *data, u64 val) \
94 unsigned long tmp = val; \
95 __asm__ __volatile__(#sr " = %0;" : : "d"(tmp)); \
99 DEFINE_SIMPLE_ATTRIBUTE(fops_sysreg_##sr, sysreg_##sr##_get, sysreg_##sr##_set, "0x%08llx\n")
101 DEFINE_SYSREG(cycles, , );
102 DEFINE_SYSREG(cycles2, __asm__ __volatile__("%0 = cycles;" : "=d"(tmp)), );
103 DEFINE_SYSREG(emudat, , );
104 DEFINE_SYSREG(seqstat, , );
105 DEFINE_SYSREG(syscfg, , CSYNC());
106 #define D_SYSREG(sr) debugfs_create_file(#sr, S_IRUSR|S_IWUSR, parent, NULL, &fops_sysreg_##sr)
111 #define CAN_OFF(mmr) REGS_OFF(can, mmr)
112 #define __CAN(uname, lname) __REGS(can, #uname, lname)
113 static void __init __maybe_unused
114 bfin_debug_mmrs_can(struct dentry *parent, unsigned long base, int num)
116 static struct dentry *am, *mb;
118 char buf[32], *_buf = REGS_STR_PFX(buf, CAN, num);
121 am = debugfs_create_dir("am", parent);
122 mb = debugfs_create_dir("mb", parent);
133 __CAN(MBTIF1, mbtif1);
134 __CAN(MBRIF1, mbrif1);
147 __CAN(MBTIF2, mbtif2);
148 __CAN(MBRIF2, mbrif2);
154 __CAN(TIMING, timing);
156 __CAN(STATUS, status);
161 __CAN(CONTROL, control);
163 __CAN(VERSION, version);
167 /*__CAN(UCREG, ucreg); no longer exists */
171 __CAN(VERSION2, version2);
173 for (i = 0; i < 32; ++i) {
174 sprintf(_buf, "AM%02iL", i);
175 debugfs_create_x16(buf, S_IRUSR|S_IWUSR, am,
176 (u16 *)(base + CAN_OFF(msk[i].aml)));
177 sprintf(_buf, "AM%02iH", i);
178 debugfs_create_x16(buf, S_IRUSR|S_IWUSR, am,
179 (u16 *)(base + CAN_OFF(msk[i].amh)));
181 for (j = 0; j < 3; ++j) {
182 sprintf(_buf, "MB%02i_DATA%i", i, j);
183 debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb,
184 (u16 *)(base + CAN_OFF(chl[i].data[j*2])));
186 sprintf(_buf, "MB%02i_LENGTH", i);
187 debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb,
188 (u16 *)(base + CAN_OFF(chl[i].dlc)));
189 sprintf(_buf, "MB%02i_TIMESTAMP", i);
190 debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb,
191 (u16 *)(base + CAN_OFF(chl[i].tsv)));
192 sprintf(_buf, "MB%02i_ID0", i);
193 debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb,
194 (u16 *)(base + CAN_OFF(chl[i].id0)));
195 sprintf(_buf, "MB%02i_ID1", i);
196 debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb,
197 (u16 *)(base + CAN_OFF(chl[i].id1)));
200 #define CAN(num) bfin_debug_mmrs_can(parent, CAN##num##_MC1, num)
205 #define __DMA(uname, lname) __REGS(dma, #uname, lname)
206 static void __init __maybe_unused
207 bfin_debug_mmrs_dma(struct dentry *parent, unsigned long base, int num, char mdma, const char *pfx)
212 _buf = buf + sprintf(buf, "%s_%c%i_", pfx, mdma, num);
214 _buf = buf + sprintf(buf, "%s%i_", pfx, num);
216 __DMA(NEXT_DESC_PTR, next_desc_ptr);
217 __DMA(START_ADDR, start_addr);
218 __DMA(CONFIG, config);
219 __DMA(X_COUNT, x_count);
220 __DMA(X_MODIFY, x_modify);
221 __DMA(Y_COUNT, y_count);
222 __DMA(Y_MODIFY, y_modify);
223 __DMA(CURR_DESC_PTR, curr_desc_ptr);
224 __DMA(CURR_ADDR, curr_addr);
225 __DMA(IRQ_STATUS, irq_status);
226 if (strcmp(pfx, "IMDMA") != 0)
227 __DMA(PERIPHERAL_MAP, peripheral_map);
228 __DMA(CURR_X_COUNT, curr_x_count);
229 __DMA(CURR_Y_COUNT, curr_y_count);
231 #define _DMA(num, base, mdma, pfx) bfin_debug_mmrs_dma(parent, base, num, mdma, pfx "DMA")
232 #define DMA(num) _DMA(num, DMA##num##_NEXT_DESC_PTR, 0, "")
233 #define _MDMA(num, x) \
235 _DMA(num, x##DMA_D##num##_NEXT_DESC_PTR, 'D', #x); \
236 _DMA(num, x##DMA_S##num##_NEXT_DESC_PTR, 'S', #x); \
238 #define MDMA(num) _MDMA(num, M)
239 #define IMDMA(num) _MDMA(num, IM)
244 #define __EPPI(uname, lname) __REGS(eppi, #uname, lname)
245 static void __init __maybe_unused
246 bfin_debug_mmrs_eppi(struct dentry *parent, unsigned long base, int num)
248 char buf[32], *_buf = REGS_STR_PFX(buf, EPPI, num);
249 __EPPI(STATUS, status);
250 __EPPI(HCOUNT, hcount);
251 __EPPI(HDELAY, hdelay);
252 __EPPI(VCOUNT, vcount);
253 __EPPI(VDELAY, vdelay);
254 __EPPI(FRAME, frame);
256 __EPPI(CLKDIV, clkdiv);
257 __EPPI(CONTROL, control);
258 __EPPI(FS1W_HBL, fs1w_hbl);
259 __EPPI(FS1P_AVPL, fs1p_avpl);
260 __EPPI(FS2W_LVB, fs2w_lvb);
261 __EPPI(FS2P_LAVF, fs2p_lavf);
264 #define EPPI(num) bfin_debug_mmrs_eppi(parent, EPPI##num##_STATUS, num)
267 * General Purpose Timers
269 #define __GPTIMER(uname, lname) __REGS(gptimer, #uname, lname)
270 static void __init __maybe_unused
271 bfin_debug_mmrs_gptimer(struct dentry *parent, unsigned long base, int num)
273 char buf[32], *_buf = REGS_STR_PFX(buf, TIMER, num);
274 __GPTIMER(CONFIG, config);
275 __GPTIMER(COUNTER, counter);
276 __GPTIMER(PERIOD, period);
277 __GPTIMER(WIDTH, width);
279 #define GPTIMER(num) bfin_debug_mmrs_gptimer(parent, TIMER##num##_CONFIG, num)
281 #define GPTIMER_GROUP_OFF(mmr) REGS_OFF(gptimer_group, mmr)
282 #define __GPTIMER_GROUP(uname, lname) __REGS(gptimer_group, #uname, lname)
283 static void __init __maybe_unused
284 bfin_debug_mmrs_gptimer_group(struct dentry *parent, unsigned long base, int num)
289 _buf = buf + sprintf(buf, "TIMER_");
290 __GPTIMER_GROUP(ENABLE, enable);
291 __GPTIMER_GROUP(DISABLE, disable);
292 __GPTIMER_GROUP(STATUS, status);
294 /* These MMRs are a bit odd as the group # is a suffix */
295 _buf = buf + sprintf(buf, "TIMER_ENABLE%i", num);
296 d(buf, 16, base + GPTIMER_GROUP_OFF(enable));
298 _buf = buf + sprintf(buf, "TIMER_DISABLE%i", num);
299 d(buf, 16, base + GPTIMER_GROUP_OFF(disable));
301 _buf = buf + sprintf(buf, "TIMER_STATUS%i", num);
302 d(buf, 32, base + GPTIMER_GROUP_OFF(status));
305 #define GPTIMER_GROUP(mmr, num) bfin_debug_mmrs_gptimer_group(parent, mmr, num)
310 #define __HMDMA(uname, lname) __REGS(hmdma, #uname, lname)
311 static void __init __maybe_unused
312 bfin_debug_mmrs_hmdma(struct dentry *parent, unsigned long base, int num)
314 char buf[32], *_buf = REGS_STR_PFX(buf, HMDMA, num);
315 __HMDMA(CONTROL, control);
316 __HMDMA(ECINIT, ecinit);
317 __HMDMA(BCINIT, bcinit);
318 __HMDMA(ECURGENT, ecurgent);
319 __HMDMA(ECOVERFLOW, ecoverflow);
320 __HMDMA(ECOUNT, ecount);
321 __HMDMA(BCOUNT, bcount);
323 #define HMDMA(num) bfin_debug_mmrs_hmdma(parent, HMDMA##num##_CONTROL, num)
326 * Peripheral Interrupts (PINT/GPIO)
328 #ifdef PINT0_MASK_SET
329 #define __PINT(uname, lname) __REGS(pint, #uname, lname)
330 static void __init __maybe_unused
331 bfin_debug_mmrs_pint(struct dentry *parent, unsigned long base, int num)
333 char buf[32], *_buf = REGS_STR_PFX(buf, PINT, num);
334 __PINT(MASK_SET, mask_set);
335 __PINT(MASK_CLEAR, mask_clear);
336 __PINT(REQUEST, request);
337 __PINT(ASSIGN, assign);
338 __PINT(EDGE_SET, edge_set);
339 __PINT(EDGE_CLEAR, edge_clear);
340 __PINT(INVERT_SET, invert_set);
341 __PINT(INVERT_CLEAR, invert_clear);
342 __PINT(PINSTATE, pinstate);
343 __PINT(LATCH, latch);
345 #define PINT(num) bfin_debug_mmrs_pint(parent, PINT##num##_MASK_SET, num)
351 #define bfin_gpio_regs gpio_port_t
352 #define __PORT(uname, lname) __REGS(gpio, #uname, lname)
353 static void __init __maybe_unused
354 bfin_debug_mmrs_port(struct dentry *parent, unsigned long base, int num)
358 _buf = REGS_STR_PFX_C(buf, PORT, num);
359 __PORT(FER, port_fer);
360 __PORT(SET, data_set);
361 __PORT(CLEAR, data_clear);
362 __PORT(DIR_SET, dir_set);
363 __PORT(DIR_CLEAR, dir_clear);
365 __PORT(MUX, port_mux);
367 _buf = buf + sprintf(buf, "PORT%cIO_", num);
368 __PORT(CLEAR, data_clear);
369 __PORT(SET, data_set);
370 __PORT(TOGGLE, toggle);
371 __PORT(MASKA, maska);
372 __PORT(MASKA_CLEAR, maska_clear);
373 __PORT(MASKA_SET, maska_set);
374 __PORT(MASKA_TOGGLE, maska_toggle);
375 __PORT(MASKB, maskb);
376 __PORT(MASKB_CLEAR, maskb_clear);
377 __PORT(MASKB_SET, maskb_set);
378 __PORT(MASKB_TOGGLE, maskb_toggle);
380 __PORT(POLAR, polar);
386 d(buf, 16, base + REGS_OFF(gpio, data));
388 #define PORT(base, num) bfin_debug_mmrs_port(parent, base, num)
393 #define __PPI(uname, lname) __REGS(ppi, #uname, lname)
394 static void __init __maybe_unused
395 bfin_debug_mmrs_ppi(struct dentry *parent, unsigned long base, int num)
397 char buf[32], *_buf = REGS_STR_PFX(buf, PPI, num);
398 __PPI(CONTROL, control);
399 __PPI(STATUS, status);
404 #define PPI(num) bfin_debug_mmrs_ppi(parent, PPI##num##_CONTROL, num)
409 #define __SPI(uname, lname) __REGS(spi, #uname, lname)
410 static void __init __maybe_unused
411 bfin_debug_mmrs_spi(struct dentry *parent, unsigned long base, int num)
413 char buf[32], *_buf = REGS_STR_PFX(buf, SPI, num);
420 __SPI(SHADOW, shadow);
422 #define SPI(num) bfin_debug_mmrs_spi(parent, SPI##num##_REGBASE, num)
427 static inline int sport_width(void *mmr)
429 unsigned long lmmr = (unsigned long)mmr;
430 if ((lmmr & 0xff) == 0x10)
431 /* SPORT#_TX has 0x10 offset -> SPORT#_TCR2 has 0x04 offset */
434 /* SPORT#_RX has 0x18 offset -> SPORT#_RCR2 has 0x24 offset */
436 /* extract SLEN field from control register 2 and add 1 */
437 return (bfin_read16(lmmr) & 0x1f) + 1;
439 static int sport_set(void *mmr, u64 val)
442 local_irq_save(flags);
443 if (sport_width(mmr) <= 16)
444 bfin_write16(mmr, val);
446 bfin_write32(mmr, val);
447 local_irq_restore(flags);
450 static int sport_get(void *mmr, u64 *val)
453 local_irq_save(flags);
454 if (sport_width(mmr) <= 16)
455 *val = bfin_read16(mmr);
457 *val = bfin_read32(mmr);
458 local_irq_restore(flags);
461 DEFINE_SIMPLE_ATTRIBUTE(fops_sport, sport_get, sport_set, "0x%08llx\n");
462 /*DEFINE_SIMPLE_ATTRIBUTE(fops_sport_ro, sport_get, NULL, "0x%08llx\n");*/
463 DEFINE_SIMPLE_ATTRIBUTE(fops_sport_wo, NULL, sport_set, "0x%08llx\n");
464 #define SPORT_OFF(mmr) (SPORT0_##mmr - SPORT0_TCR1)
465 #define _D_SPORT(name, perms, fops) \
467 strcpy(_buf, #name); \
468 debugfs_create_file(buf, perms, parent, (void *)(base + SPORT_OFF(name)), fops); \
470 #define __SPORT_RW(name) _D_SPORT(name, S_IRUSR|S_IWUSR, &fops_sport)
471 #define __SPORT_RO(name) _D_SPORT(name, S_IRUSR, &fops_sport_ro)
472 #define __SPORT_WO(name) _D_SPORT(name, S_IWUSR, &fops_sport_wo)
473 #define __SPORT(name, bits) \
475 strcpy(_buf, #name); \
476 debugfs_create_x##bits(buf, S_IRUSR|S_IWUSR, parent, (u##bits *)(base + SPORT_OFF(name))); \
478 static void __init __maybe_unused
479 bfin_debug_mmrs_sport(struct dentry *parent, unsigned long base, int num)
481 char buf[32], *_buf = REGS_STR_PFX(buf, SPORT, num);
493 __SPORT(RCLKDIV, 16);
499 __SPORT(TCLKDIV, 16);
505 #define SPORT(num) bfin_debug_mmrs_sport(parent, SPORT##num##_TCR1, num)
510 #define __TWI(uname, lname) __REGS(twi, #uname, lname)
511 static void __init __maybe_unused
512 bfin_debug_mmrs_twi(struct dentry *parent, unsigned long base, int num)
514 char buf[32], *_buf = REGS_STR_PFX(buf, TWI, num);
515 __TWI(CLKDIV, clkdiv);
516 __TWI(CONTROL, control);
517 __TWI(SLAVE_CTL, slave_ctl);
518 __TWI(SLAVE_STAT, slave_stat);
519 __TWI(SLAVE_ADDR, slave_addr);
520 __TWI(MASTER_CTL, master_ctl);
521 __TWI(MASTER_STAT, master_stat);
522 __TWI(MASTER_ADDR, master_addr);
523 __TWI(INT_STAT, int_stat);
524 __TWI(INT_MASK, int_mask);
525 __TWI(FIFO_CTL, fifo_ctl);
526 __TWI(FIFO_STAT, fifo_stat);
527 __TWI(XMT_DATA8, xmt_data8);
528 __TWI(XMT_DATA16, xmt_data16);
529 __TWI(RCV_DATA8, rcv_data8);
530 __TWI(RCV_DATA16, rcv_data16);
532 #define TWI(num) bfin_debug_mmrs_twi(parent, TWI##num##_CLKDIV, num)
537 #define __UART(uname, lname) __REGS(uart, #uname, lname)
538 static void __init __maybe_unused
539 bfin_debug_mmrs_uart(struct dentry *parent, unsigned long base, int num)
541 char buf[32], *_buf = REGS_STR_PFX(buf, UART, num);
542 #ifdef BFIN_UART_BF54X_STYLE
551 __UART(IER_SET, ier_set);
552 __UART(IER_CLEAR, ier_clear);
570 #define UART(num) bfin_debug_mmrs_uart(parent, UART##num##_DLL, num)
573 * The actual debugfs generation
575 static struct dentry *debug_mmrs_dentry;
577 static int __init bfin_debug_mmrs_init(void)
579 struct dentry *top, *parent;
581 pr_info("debug-mmrs: setting up Blackfin MMR debugfs\n");
583 top = debugfs_create_dir("blackfin", NULL);
587 parent = debugfs_create_dir("core_regs", top);
588 debugfs_create_file("cclk", S_IRUSR, parent, NULL, &fops_debug_cclk);
589 debugfs_create_file("sclk", S_IRUSR, parent, NULL, &fops_debug_sclk);
590 debugfs_create_x32("last_seqstat", S_IRUSR, parent, &last_seqstat);
598 parent = debugfs_create_dir("ctimer", top);
604 parent = debugfs_create_dir("cec", top);
627 parent = debugfs_create_dir("debug", top);
631 parent = debugfs_create_dir("mmu", top);
632 D32(SRAM_BASE_ADDRESS);
665 D32(DCPLB_FAULT_ADDR);
704 D32(ICPLB_FAULT_ADDR);
707 if (!ANOMALY_05000481) {
713 parent = debugfs_create_dir("perf", top);
718 parent = debugfs_create_dir("trace", top);
723 parent = debugfs_create_dir("watchpoint", top);
746 parent = debugfs_create_dir("atapi", top);
749 D16(ATAPI_DEV_RXBUF);
750 D16(ATAPI_DEV_TXBUF);
751 D16(ATAPI_DMA_TFRCNT);
753 D16(ATAPI_INT_STATUS);
754 D16(ATAPI_LINE_STATUS);
755 D16(ATAPI_MULTI_TIM_0);
756 D16(ATAPI_MULTI_TIM_1);
757 D16(ATAPI_MULTI_TIM_2);
758 D16(ATAPI_PIO_TFRCNT);
759 D16(ATAPI_PIO_TIM_0);
760 D16(ATAPI_PIO_TIM_1);
761 D16(ATAPI_REG_TIM_0);
764 D16(ATAPI_TERMINATE);
765 D16(ATAPI_UDMAOUT_TFRCNT);
766 D16(ATAPI_ULTRA_TIM_0);
767 D16(ATAPI_ULTRA_TIM_1);
768 D16(ATAPI_ULTRA_TIM_2);
769 D16(ATAPI_ULTRA_TIM_3);
770 D16(ATAPI_UMAIN_TFRCNT);
774 #if defined(CAN_MC1) || defined(CAN0_MC1) || defined(CAN1_MC1)
775 parent = debugfs_create_dir("can", top);
777 bfin_debug_mmrs_can(parent, CAN_MC1, -1);
788 parent = debugfs_create_dir("counter", top);
799 parent = debugfs_create_dir("dmac", top);
817 /* XXX: should rewrite the MMR map */
818 # define DMA0_NEXT_DESC_PTR DMA2_0_NEXT_DESC_PTR
819 # define DMA1_NEXT_DESC_PTR DMA2_1_NEXT_DESC_PTR
820 # define DMA2_NEXT_DESC_PTR DMA2_2_NEXT_DESC_PTR
821 # define DMA3_NEXT_DESC_PTR DMA2_3_NEXT_DESC_PTR
822 # define DMA4_NEXT_DESC_PTR DMA2_4_NEXT_DESC_PTR
823 # define DMA5_NEXT_DESC_PTR DMA2_5_NEXT_DESC_PTR
824 # define DMA6_NEXT_DESC_PTR DMA2_6_NEXT_DESC_PTR
825 # define DMA7_NEXT_DESC_PTR DMA2_7_NEXT_DESC_PTR
826 # define DMA8_NEXT_DESC_PTR DMA2_8_NEXT_DESC_PTR
827 # define DMA9_NEXT_DESC_PTR DMA2_9_NEXT_DESC_PTR
828 # define DMA10_NEXT_DESC_PTR DMA2_10_NEXT_DESC_PTR
829 # define DMA11_NEXT_DESC_PTR DMA2_11_NEXT_DESC_PTR
830 # define DMA12_NEXT_DESC_PTR DMA1_0_NEXT_DESC_PTR
831 # define DMA13_NEXT_DESC_PTR DMA1_1_NEXT_DESC_PTR
832 # define DMA14_NEXT_DESC_PTR DMA1_2_NEXT_DESC_PTR
833 # define DMA15_NEXT_DESC_PTR DMA1_3_NEXT_DESC_PTR
834 # define DMA16_NEXT_DESC_PTR DMA1_4_NEXT_DESC_PTR
835 # define DMA17_NEXT_DESC_PTR DMA1_5_NEXT_DESC_PTR
836 # define DMA18_NEXT_DESC_PTR DMA1_6_NEXT_DESC_PTR
837 # define DMA19_NEXT_DESC_PTR DMA1_7_NEXT_DESC_PTR
838 # define DMA20_NEXT_DESC_PTR DMA1_8_NEXT_DESC_PTR
839 # define DMA21_NEXT_DESC_PTR DMA1_9_NEXT_DESC_PTR
840 # define DMA22_NEXT_DESC_PTR DMA1_10_NEXT_DESC_PTR
841 # define DMA23_NEXT_DESC_PTR DMA1_11_NEXT_DESC_PTR
843 parent = debugfs_create_dir("dma", top);
853 #ifdef DMA8_NEXT_DESC_PTR
859 #ifdef DMA12_NEXT_DESC_PTR
869 #ifdef DMA20_NEXT_DESC_PTR
876 parent = debugfs_create_dir("ebiu_amc", top);
888 parent = debugfs_create_dir("ebiu_sdram", top);
889 # ifdef __ADSPBF561__
900 parent = debugfs_create_dir("ebiu_ddr", top);
937 parent = debugfs_create_dir("emac", top);
950 D32(EMAC_RXC_ALLFRM);
951 D32(EMAC_RXC_ALLOCT);
953 D32(EMAC_RXC_DMAOVF);
956 D32(EMAC_RXC_GE1024);
957 D32(EMAC_RXC_LNERRI);
958 D32(EMAC_RXC_LNERRO);
960 D32(EMAC_RXC_LT1024);
964 D32(EMAC_RXC_MACCTL);
968 D32(EMAC_RXC_OPCODE);
972 D32(EMAC_RXC_UNICST);
982 D32(EMAC_TXC_ALLFRM);
983 D32(EMAC_TXC_ALLOCT);
985 D32(EMAC_TXC_CRSERR);
987 D32(EMAC_TXC_DMAUND);
989 D32(EMAC_TXC_GE1024);
990 D32(EMAC_TXC_GT1COL);
991 D32(EMAC_TXC_LATECL);
992 D32(EMAC_TXC_LT1024);
996 D32(EMAC_TXC_MACCTL);
1000 D32(EMAC_TXC_UNICST);
1001 D32(EMAC_TXC_XS_COL);
1002 D32(EMAC_TXC_XS_DFR);
1009 D32(EMAC_WKUP_FFCMD);
1010 D32(EMAC_WKUP_FFCRC0);
1011 D32(EMAC_WKUP_FFCRC1);
1012 D32(EMAC_WKUP_FFMSK0);
1013 D32(EMAC_WKUP_FFMSK1);
1014 D32(EMAC_WKUP_FFMSK2);
1015 D32(EMAC_WKUP_FFMSK3);
1016 D32(EMAC_WKUP_FFOFF);
1017 # ifdef EMAC_PTP_ACCR
1019 D32(EMAC_PTP_ADDEND);
1020 D32(EMAC_PTP_ALARMHI);
1021 D32(EMAC_PTP_ALARMLO);
1027 D16(EMAC_PTP_ID_OFF);
1028 D32(EMAC_PTP_ID_SNAP);
1030 D16(EMAC_PTP_ISTAT);
1031 D32(EMAC_PTP_OFFSET);
1032 D32(EMAC_PTP_PPS_PERIOD);
1033 D32(EMAC_PTP_PPS_STARTHI);
1034 D32(EMAC_PTP_PPS_STARTLO);
1035 D32(EMAC_PTP_RXSNAPHI);
1036 D32(EMAC_PTP_RXSNAPLO);
1037 D32(EMAC_PTP_TIMEHI);
1038 D32(EMAC_PTP_TIMELO);
1039 D32(EMAC_PTP_TXSNAPHI);
1040 D32(EMAC_PTP_TXSNAPLO);
1044 #if defined(EPPI0_STATUS) || defined(EPPI1_STATUS) || defined(EPPI2_STATUS)
1045 parent = debugfs_create_dir("eppi", top);
1046 # ifdef EPPI0_STATUS
1049 # ifdef EPPI1_STATUS
1052 # ifdef EPPI2_STATUS
1057 parent = debugfs_create_dir("gptimer", top);
1059 GPTIMER_GROUP(TIMER_ENABLE, -1);
1061 #ifdef TIMER_ENABLE0
1062 GPTIMER_GROUP(TIMER_ENABLE0, 0);
1064 #ifdef TIMER_ENABLE1
1065 GPTIMER_GROUP(TIMER_ENABLE1, 1);
1067 /* XXX: Should convert BF561 MMR names */
1068 #ifdef TMRS4_DISABLE
1069 GPTIMER_GROUP(TMRS4_ENABLE, 0);
1070 GPTIMER_GROUP(TMRS8_ENABLE, 1);
1075 #ifdef TIMER3_CONFIG
1082 #ifdef TIMER8_CONFIG
1087 #ifdef TIMER11_CONFIG
1091 #ifdef HMDMA0_CONTROL
1092 parent = debugfs_create_dir("hmdma", top);
1098 parent = debugfs_create_dir("hostdp", top);
1104 #ifdef IMDMA_S0_CONFIG
1105 parent = debugfs_create_dir("imdma", top);
1111 parent = debugfs_create_dir("keypad", top);
1120 parent = debugfs_create_dir("mdma", top);
1123 #ifdef MDMA_D2_CONFIG
1129 parent = debugfs_create_dir("mxvr", top);
1131 # ifdef MXVR_PLL_CTL_0
1132 D32(MXVR_PLL_CTL_0);
1136 D32(MXVR_INT_STAT_0);
1137 D32(MXVR_INT_STAT_1);
1141 D16(MXVR_MAX_POSITION);
1143 D16(MXVR_MAX_DELAY);
1162 D32(MXVR_SYNC_LCHAN_0);
1163 D32(MXVR_SYNC_LCHAN_1);
1164 D32(MXVR_SYNC_LCHAN_2);
1165 D32(MXVR_SYNC_LCHAN_3);
1166 D32(MXVR_SYNC_LCHAN_4);
1167 D32(MXVR_SYNC_LCHAN_5);
1168 D32(MXVR_SYNC_LCHAN_6);
1169 D32(MXVR_SYNC_LCHAN_7);
1170 D32(MXVR_DMA0_CONFIG);
1171 D32(MXVR_DMA0_START_ADDR);
1172 D16(MXVR_DMA0_COUNT);
1173 D32(MXVR_DMA0_CURR_ADDR);
1174 D16(MXVR_DMA0_CURR_COUNT);
1175 D32(MXVR_DMA1_CONFIG);
1176 D32(MXVR_DMA1_START_ADDR);
1177 D16(MXVR_DMA1_COUNT);
1178 D32(MXVR_DMA1_CURR_ADDR);
1179 D16(MXVR_DMA1_CURR_COUNT);
1180 D32(MXVR_DMA2_CONFIG);
1181 D32(MXVR_DMA2_START_ADDR);
1182 D16(MXVR_DMA2_COUNT);
1183 D32(MXVR_DMA2_CURR_ADDR);
1184 D16(MXVR_DMA2_CURR_COUNT);
1185 D32(MXVR_DMA3_CONFIG);
1186 D32(MXVR_DMA3_START_ADDR);
1187 D16(MXVR_DMA3_COUNT);
1188 D32(MXVR_DMA3_CURR_ADDR);
1189 D16(MXVR_DMA3_CURR_COUNT);
1190 D32(MXVR_DMA4_CONFIG);
1191 D32(MXVR_DMA4_START_ADDR);
1192 D16(MXVR_DMA4_COUNT);
1193 D32(MXVR_DMA4_CURR_ADDR);
1194 D16(MXVR_DMA4_CURR_COUNT);
1195 D32(MXVR_DMA5_CONFIG);
1196 D32(MXVR_DMA5_START_ADDR);
1197 D16(MXVR_DMA5_COUNT);
1198 D32(MXVR_DMA5_CURR_ADDR);
1199 D16(MXVR_DMA5_CURR_COUNT);
1200 D32(MXVR_DMA6_CONFIG);
1201 D32(MXVR_DMA6_START_ADDR);
1202 D16(MXVR_DMA6_COUNT);
1203 D32(MXVR_DMA6_CURR_ADDR);
1204 D16(MXVR_DMA6_CURR_COUNT);
1205 D32(MXVR_DMA7_CONFIG);
1206 D32(MXVR_DMA7_START_ADDR);
1207 D16(MXVR_DMA7_COUNT);
1208 D32(MXVR_DMA7_CURR_ADDR);
1209 D16(MXVR_DMA7_CURR_COUNT);
1211 D32(MXVR_APRB_START_ADDR);
1212 D32(MXVR_APRB_CURR_ADDR);
1213 D32(MXVR_APTB_START_ADDR);
1214 D32(MXVR_APTB_CURR_ADDR);
1216 D32(MXVR_CMRB_START_ADDR);
1217 D32(MXVR_CMRB_CURR_ADDR);
1218 D32(MXVR_CMTB_START_ADDR);
1219 D32(MXVR_CMTB_CURR_ADDR);
1220 D32(MXVR_RRDB_START_ADDR);
1221 D32(MXVR_RRDB_CURR_ADDR);
1222 D32(MXVR_PAT_DATA_0);
1224 D32(MXVR_PAT_DATA_1);
1226 D16(MXVR_FRAME_CNT_0);
1227 D16(MXVR_FRAME_CNT_1);
1228 D32(MXVR_ROUTING_0);
1229 D32(MXVR_ROUTING_1);
1230 D32(MXVR_ROUTING_2);
1231 D32(MXVR_ROUTING_3);
1232 D32(MXVR_ROUTING_4);
1233 D32(MXVR_ROUTING_5);
1234 D32(MXVR_ROUTING_6);
1235 D32(MXVR_ROUTING_7);
1236 D32(MXVR_ROUTING_8);
1237 D32(MXVR_ROUTING_9);
1238 D32(MXVR_ROUTING_10);
1239 D32(MXVR_ROUTING_11);
1240 D32(MXVR_ROUTING_12);
1241 D32(MXVR_ROUTING_13);
1242 D32(MXVR_ROUTING_14);
1243 # ifdef MXVR_PLL_CTL_1
1244 D32(MXVR_PLL_CTL_1);
1246 D16(MXVR_BLOCK_CNT);
1247 # ifdef MXVR_CLK_CTL
1250 # ifdef MXVR_CDRPLL_CTL
1251 D32(MXVR_CDRPLL_CTL);
1253 # ifdef MXVR_FMPLL_CTL
1254 D32(MXVR_FMPLL_CTL);
1256 # ifdef MXVR_PIN_CTL
1259 # ifdef MXVR_SCLK_CNT
1265 parent = debugfs_create_dir("nfc", top);
1268 D_RO(NFC_COUNT, 16);
1270 D_WO(NFC_DATA_RD, 16);
1271 D_WO(NFC_DATA_WR, 16);
1278 D_WO(NFC_PGCTL, 16);
1285 parent = debugfs_create_dir("otp", top);
1296 #ifdef PINT0_MASK_SET
1297 parent = debugfs_create_dir("pint", top);
1305 parent = debugfs_create_dir("pixc", top);
1327 parent = debugfs_create_dir("pll", top);
1333 D32(CHIPID); /* it's part of this hardware block */
1335 #if defined(PPI_CONTROL) || defined(PPI0_CONTROL) || defined(PPI1_CONTROL)
1336 parent = debugfs_create_dir("ppi", top);
1338 bfin_debug_mmrs_ppi(parent, PPI_CONTROL, -1);
1340 # ifdef PPI0_CONTROL
1343 # ifdef PPI1_CONTROL
1349 parent = debugfs_create_dir("pwm", top);
1368 parent = debugfs_create_dir("rsi", top);
1370 D16(RSI_CEATA_CONTROL);
1371 D16(RSI_CLK_CONTROL);
1375 D16(RSI_DATA_CONTROL);
1377 D32(RSI_DATA_TIMER);
1392 D16(RSI_PWR_CONTROL);
1393 D16(RSI_RD_WAIT_EN);
1400 D_WO(RSI_STATUSCL, 16);
1404 parent = debugfs_create_dir("rtc", top);
1414 parent = debugfs_create_dir("sdh", top);
1419 D_RO(SDH_DATA_CNT, 16);
1422 D32(SDH_DATA_TIMER);
1426 D_RO(SDH_FIFO_CNT, 16);
1438 D16(SDH_RD_WAIT_EN);
1439 D_RO(SDH_RESPONSE0, 32);
1440 D_RO(SDH_RESPONSE1, 32);
1441 D_RO(SDH_RESPONSE2, 32);
1442 D_RO(SDH_RESPONSE3, 32);
1443 D_RO(SDH_RESP_CMD, 16);
1444 D_RO(SDH_STATUS, 32);
1445 D_WO(SDH_STATUS_CLR, 16);
1448 #ifdef SECURE_CONTROL
1449 parent = debugfs_create_dir("security", top);
1450 D16(SECURE_CONTROL);
1455 parent = debugfs_create_dir("sic", top);
1517 parent = debugfs_create_dir("spi", top);
1528 parent = debugfs_create_dir("sport", top);
1542 #if defined(TWI_CLKDIV) || defined(TWI0_CLKDIV) || defined(TWI1_CLKDIV)
1543 parent = debugfs_create_dir("twi", top);
1545 bfin_debug_mmrs_twi(parent, TWI_CLKDIV, -1);
1555 parent = debugfs_create_dir("uart", top);
1556 #ifdef BFIN_UART_DLL
1557 bfin_debug_mmrs_uart(parent, BFIN_UART_DLL, -1);
1573 parent = debugfs_create_dir("usb", top);
1586 D16(USB_GLOBAL_CTL);
1587 D16(USB_TX_MAX_PACKET);
1590 D16(USB_RX_MAX_PACKET);
1596 D16(USB_TXINTERVAL);
1598 D16(USB_RXINTERVAL);
1608 D16(USB_OTG_DEV_CTL);
1609 D16(USB_OTG_VBUS_IRQ);
1610 D16(USB_OTG_VBUS_MASK);
1616 D16(USB_APHY_CNTRL);
1617 D16(USB_APHY_CALIB);
1618 D16(USB_APHY_CNTRL2);
1620 D16(USB_PLLOSC_CTRL);
1621 D16(USB_SRP_CLKDIV);
1622 D16(USB_EP_NI0_TXMAXP);
1623 D16(USB_EP_NI0_TXCSR);
1624 D16(USB_EP_NI0_RXMAXP);
1625 D16(USB_EP_NI0_RXCSR);
1626 D16(USB_EP_NI0_RXCOUNT);
1627 D16(USB_EP_NI0_TXTYPE);
1628 D16(USB_EP_NI0_TXINTERVAL);
1629 D16(USB_EP_NI0_RXTYPE);
1630 D16(USB_EP_NI0_RXINTERVAL);
1631 D16(USB_EP_NI0_TXCOUNT);
1632 D16(USB_EP_NI1_TXMAXP);
1633 D16(USB_EP_NI1_TXCSR);
1634 D16(USB_EP_NI1_RXMAXP);
1635 D16(USB_EP_NI1_RXCSR);
1636 D16(USB_EP_NI1_RXCOUNT);
1637 D16(USB_EP_NI1_TXTYPE);
1638 D16(USB_EP_NI1_TXINTERVAL);
1639 D16(USB_EP_NI1_RXTYPE);
1640 D16(USB_EP_NI1_RXINTERVAL);
1641 D16(USB_EP_NI1_TXCOUNT);
1642 D16(USB_EP_NI2_TXMAXP);
1643 D16(USB_EP_NI2_TXCSR);
1644 D16(USB_EP_NI2_RXMAXP);
1645 D16(USB_EP_NI2_RXCSR);
1646 D16(USB_EP_NI2_RXCOUNT);
1647 D16(USB_EP_NI2_TXTYPE);
1648 D16(USB_EP_NI2_TXINTERVAL);
1649 D16(USB_EP_NI2_RXTYPE);
1650 D16(USB_EP_NI2_RXINTERVAL);
1651 D16(USB_EP_NI2_TXCOUNT);
1652 D16(USB_EP_NI3_TXMAXP);
1653 D16(USB_EP_NI3_TXCSR);
1654 D16(USB_EP_NI3_RXMAXP);
1655 D16(USB_EP_NI3_RXCSR);
1656 D16(USB_EP_NI3_RXCOUNT);
1657 D16(USB_EP_NI3_TXTYPE);
1658 D16(USB_EP_NI3_TXINTERVAL);
1659 D16(USB_EP_NI3_RXTYPE);
1660 D16(USB_EP_NI3_RXINTERVAL);
1661 D16(USB_EP_NI3_TXCOUNT);
1662 D16(USB_EP_NI4_TXMAXP);
1663 D16(USB_EP_NI4_TXCSR);
1664 D16(USB_EP_NI4_RXMAXP);
1665 D16(USB_EP_NI4_RXCSR);
1666 D16(USB_EP_NI4_RXCOUNT);
1667 D16(USB_EP_NI4_TXTYPE);
1668 D16(USB_EP_NI4_TXINTERVAL);
1669 D16(USB_EP_NI4_RXTYPE);
1670 D16(USB_EP_NI4_RXINTERVAL);
1671 D16(USB_EP_NI4_TXCOUNT);
1672 D16(USB_EP_NI5_TXMAXP);
1673 D16(USB_EP_NI5_TXCSR);
1674 D16(USB_EP_NI5_RXMAXP);
1675 D16(USB_EP_NI5_RXCSR);
1676 D16(USB_EP_NI5_RXCOUNT);
1677 D16(USB_EP_NI5_TXTYPE);
1678 D16(USB_EP_NI5_TXINTERVAL);
1679 D16(USB_EP_NI5_RXTYPE);
1680 D16(USB_EP_NI5_RXINTERVAL);
1681 D16(USB_EP_NI5_TXCOUNT);
1682 D16(USB_EP_NI6_TXMAXP);
1683 D16(USB_EP_NI6_TXCSR);
1684 D16(USB_EP_NI6_RXMAXP);
1685 D16(USB_EP_NI6_RXCSR);
1686 D16(USB_EP_NI6_RXCOUNT);
1687 D16(USB_EP_NI6_TXTYPE);
1688 D16(USB_EP_NI6_TXINTERVAL);
1689 D16(USB_EP_NI6_RXTYPE);
1690 D16(USB_EP_NI6_RXINTERVAL);
1691 D16(USB_EP_NI6_TXCOUNT);
1692 D16(USB_EP_NI7_TXMAXP);
1693 D16(USB_EP_NI7_TXCSR);
1694 D16(USB_EP_NI7_RXMAXP);
1695 D16(USB_EP_NI7_RXCSR);
1696 D16(USB_EP_NI7_RXCOUNT);
1697 D16(USB_EP_NI7_TXTYPE);
1698 D16(USB_EP_NI7_TXINTERVAL);
1699 D16(USB_EP_NI7_RXTYPE);
1700 D16(USB_EP_NI7_RXINTERVAL);
1701 D16(USB_EP_NI7_TXCOUNT);
1702 D16(USB_DMA_INTERRUPT);
1703 D16(USB_DMA0CONTROL);
1704 D16(USB_DMA0ADDRLOW);
1705 D16(USB_DMA0ADDRHIGH);
1706 D16(USB_DMA0COUNTLOW);
1707 D16(USB_DMA0COUNTHIGH);
1708 D16(USB_DMA1CONTROL);
1709 D16(USB_DMA1ADDRLOW);
1710 D16(USB_DMA1ADDRHIGH);
1711 D16(USB_DMA1COUNTLOW);
1712 D16(USB_DMA1COUNTHIGH);
1713 D16(USB_DMA2CONTROL);
1714 D16(USB_DMA2ADDRLOW);
1715 D16(USB_DMA2ADDRHIGH);
1716 D16(USB_DMA2COUNTLOW);
1717 D16(USB_DMA2COUNTHIGH);
1718 D16(USB_DMA3CONTROL);
1719 D16(USB_DMA3ADDRLOW);
1720 D16(USB_DMA3ADDRHIGH);
1721 D16(USB_DMA3COUNTLOW);
1722 D16(USB_DMA3COUNTHIGH);
1723 D16(USB_DMA4CONTROL);
1724 D16(USB_DMA4ADDRLOW);
1725 D16(USB_DMA4ADDRHIGH);
1726 D16(USB_DMA4COUNTLOW);
1727 D16(USB_DMA4COUNTHIGH);
1728 D16(USB_DMA5CONTROL);
1729 D16(USB_DMA5ADDRLOW);
1730 D16(USB_DMA5ADDRHIGH);
1731 D16(USB_DMA5COUNTLOW);
1732 D16(USB_DMA5COUNTHIGH);
1733 D16(USB_DMA6CONTROL);
1734 D16(USB_DMA6ADDRLOW);
1735 D16(USB_DMA6ADDRHIGH);
1736 D16(USB_DMA6COUNTLOW);
1737 D16(USB_DMA6COUNTHIGH);
1738 D16(USB_DMA7CONTROL);
1739 D16(USB_DMA7ADDRLOW);
1740 D16(USB_DMA7ADDRHIGH);
1741 D16(USB_DMA7COUNTLOW);
1742 D16(USB_DMA7COUNTHIGH);
1746 parent = debugfs_create_dir("watchdog", top);
1752 parent = debugfs_create_dir("watchdog", top);
1763 #define PORTFIO FIO_FLAG_D
1767 #define PORTFIO FIO0_FLAG_D
1770 #define PORTGIO FIO1_FLAG_D
1773 #define PORTHIO FIO2_FLAG_D
1775 parent = debugfs_create_dir("port", top);
1786 #ifdef __ADSPBF51x__
1789 D16(PORTF_HYSTERESIS);
1794 D16(PORTG_HYSTERESIS);
1799 D16(PORTH_HYSTERESIS);
1802 D16(MISCPORT_DRIVE);
1803 D16(MISCPORT_HYSTERESIS);
1806 #ifdef __ADSPBF52x__
1809 D16(PORTF_HYSTERESIS);
1815 D16(PORTG_HYSTERESIS);
1821 D16(PORTH_HYSTERESIS);
1825 D16(MISCPORT_DRIVE);
1826 D16(MISCPORT_HYSTERESIS);
1835 #endif /* BF534 BF536 BF537 */
1842 D16(PORTCIO_TOGGLE);
1852 D16(PORTDIO_TOGGLE);
1860 D16(PORTEIO_TOGGLE);
1861 #endif /* BF538 BF539 */
1863 #ifdef __ADSPBF54x__
1869 for (num = 0; num < 10; ++num) {
1871 base += sizeof(struct bfin_gpio_regs);
1877 debug_mmrs_dentry = top;
1881 module_init(bfin_debug_mmrs_init);
1883 static void __exit bfin_debug_mmrs_exit(void)
1885 debugfs_remove_recursive(debug_mmrs_dentry);
1887 module_exit(bfin_debug_mmrs_exit);
1889 MODULE_LICENSE("GPL");