2 * SMP initialisation and IPI support
3 * Based on arch/arm/kernel/smp.c
5 * Copyright (C) 2012 ARM Ltd.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 #include <linux/delay.h>
21 #include <linux/init.h>
22 #include <linux/spinlock.h>
23 #include <linux/sched.h>
24 #include <linux/interrupt.h>
25 #include <linux/cache.h>
26 #include <linux/profile.h>
27 #include <linux/errno.h>
29 #include <linux/err.h>
30 #include <linux/cpu.h>
31 #include <linux/smp.h>
32 #include <linux/seq_file.h>
33 #include <linux/irq.h>
34 #include <linux/percpu.h>
35 #include <linux/clockchips.h>
36 #include <linux/completion.h>
39 #include <asm/atomic.h>
40 #include <asm/cacheflush.h>
41 #include <asm/cputype.h>
42 #include <asm/mmu_context.h>
43 #include <asm/pgtable.h>
44 #include <asm/pgalloc.h>
45 #include <asm/processor.h>
46 #include <asm/smp_plat.h>
47 #include <asm/sections.h>
48 #include <asm/tlbflush.h>
49 #include <asm/ptrace.h>
52 * as from 2.5, kernels no longer have an init_tasks structure
53 * so we need some other way of telling a new secondary core
54 * where to place its SVC stack
56 struct secondary_data secondary_data;
57 volatile unsigned long secondary_holding_pen_release = INVALID_HWID;
66 static DEFINE_RAW_SPINLOCK(boot_lock);
69 * Write secondary_holding_pen_release in a way that is guaranteed to be
70 * visible to all observers, irrespective of whether they're taking part
71 * in coherency or not. This is necessary for the hotplug code to work
74 static void __cpuinit write_pen_release(u64 val)
76 void *start = (void *)&secondary_holding_pen_release;
77 unsigned long size = sizeof(secondary_holding_pen_release);
79 secondary_holding_pen_release = val;
80 __flush_dcache_area(start, size);
84 * Boot a secondary CPU, and assign it the specified idle task.
85 * This also gives us the initial stack to use for this CPU.
87 static int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
89 unsigned long timeout;
92 * Set synchronisation state between this boot processor
93 * and the secondary one
95 raw_spin_lock(&boot_lock);
98 * Update the pen release flag.
100 write_pen_release(cpu_logical_map(cpu));
103 * Send an event, causing the secondaries to read pen_release.
107 timeout = jiffies + (1 * HZ);
108 while (time_before(jiffies, timeout)) {
109 if (secondary_holding_pen_release == INVALID_HWID)
115 * Now the secondary core is starting up let it run its
116 * calibrations, then wait for it to finish
118 raw_spin_unlock(&boot_lock);
120 return secondary_holding_pen_release != INVALID_HWID ? -ENOSYS : 0;
123 static DECLARE_COMPLETION(cpu_running);
125 int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *idle)
130 * We need to tell the secondary core where to find its stack and the
133 secondary_data.stack = task_stack_page(idle) + THREAD_START_SP;
134 __flush_dcache_area(&secondary_data, sizeof(secondary_data));
137 * Now bring the CPU into our world.
139 ret = boot_secondary(cpu, idle);
142 * CPU was successfully started, wait for it to come online or
145 wait_for_completion_timeout(&cpu_running,
146 msecs_to_jiffies(1000));
148 if (!cpu_online(cpu)) {
149 pr_crit("CPU%u: failed to come online\n", cpu);
153 pr_err("CPU%u: failed to boot: %d\n", cpu, ret);
156 secondary_data.stack = NULL;
161 static void __cpuinit smp_store_cpu_info(unsigned int cpuid)
163 store_cpu_topology(cpuid);
167 * This is the secondary CPU boot entry. We're using this CPUs
168 * idle thread stack, but a set of temporary page tables.
170 asmlinkage void __cpuinit secondary_start_kernel(void)
172 struct mm_struct *mm = &init_mm;
173 unsigned int cpu = smp_processor_id();
175 printk("CPU%u: Booted secondary processor\n", cpu);
178 * All kernel threads share the same mm context; grab a
179 * reference and switch to it.
181 atomic_inc(&mm->mm_count);
182 current->active_mm = mm;
183 cpumask_set_cpu(cpu, mm_cpumask(mm));
186 * TTBR0 is only used for the identity mapping at this stage. Make it
187 * point to zero page to avoid speculatively fetching new entries.
189 cpu_set_reserved_ttbr0();
193 trace_hardirqs_off();
196 * Let the primary processor know we're out of the
197 * pen, then head off into the C entry point
199 write_pen_release(INVALID_HWID);
202 * Synchronise with the boot thread.
204 raw_spin_lock(&boot_lock);
205 raw_spin_unlock(&boot_lock);
208 * Enable local interrupts.
210 notify_cpu_starting(cpu);
214 smp_store_cpu_info(cpu);
217 * OK, now it's safe to let the boot CPU continue. Wait for
218 * the CPU migration code to notice that the CPU is online
219 * before we continue.
221 set_cpu_online(cpu, true);
222 complete(&cpu_running);
225 * OK, it's off to the idle thread for us
227 cpu_startup_entry(CPUHP_ONLINE);
230 void __init smp_cpus_done(unsigned int max_cpus)
232 unsigned long bogosum = loops_per_jiffy * num_online_cpus();
234 pr_info("SMP: Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
235 num_online_cpus(), bogosum / (500000/HZ),
236 (bogosum / (5000/HZ)) % 100);
239 void __init smp_prepare_boot_cpu(void)
243 static void (*smp_cross_call)(const struct cpumask *, unsigned int);
245 static const struct smp_enable_ops *enable_ops[] __initconst = {
251 static const struct smp_enable_ops *smp_enable_ops[NR_CPUS];
253 static const struct smp_enable_ops * __init smp_get_enable_ops(const char *name)
255 const struct smp_enable_ops **ops = enable_ops;
258 if (!strcmp(name, (*ops)->name))
268 * Enumerate the possible CPU set from the device tree and build the
269 * cpu logical map array containing MPIDR values related to logical
270 * cpus. Assumes that cpu_logical_map(0) has already been initialized.
272 void __init smp_init_cpus(void)
274 const char *enable_method;
275 struct device_node *dn = NULL;
277 bool bootcpu_valid = false;
279 while ((dn = of_find_node_by_type(dn, "cpu"))) {
284 * A cpu node with missing "reg" property is
285 * considered invalid to build a cpu_logical_map
288 cell = of_get_property(dn, "reg", NULL);
290 pr_err("%s: missing reg property\n", dn->full_name);
293 hwid = of_read_number(cell, of_n_addr_cells(dn));
296 * Non affinity bits must be set to 0 in the DT
298 if (hwid & ~MPIDR_HWID_BITMASK) {
299 pr_err("%s: invalid reg property\n", dn->full_name);
304 * Duplicate MPIDRs are a recipe for disaster. Scan
305 * all initialized entries and check for
306 * duplicates. If any is found just ignore the cpu.
307 * cpu_logical_map was initialized to INVALID_HWID to
308 * avoid matching valid MPIDR values.
310 for (i = 1; (i < cpu) && (i < NR_CPUS); i++) {
311 if (cpu_logical_map(i) == hwid) {
312 pr_err("%s: duplicate cpu reg properties in the DT\n",
319 * The numbering scheme requires that the boot CPU
320 * must be assigned logical id 0. Record it so that
321 * the logical map built from DT is validated and can
324 if (hwid == cpu_logical_map(0)) {
326 pr_err("%s: duplicate boot cpu reg property in DT\n",
331 bootcpu_valid = true;
334 * cpu_logical_map has already been
335 * initialized and the boot cpu doesn't need
336 * the enable-method so continue without
346 * We currently support only the "spin-table" enable-method.
348 enable_method = of_get_property(dn, "enable-method", NULL);
349 if (!enable_method) {
350 pr_err("%s: missing enable-method property\n",
355 smp_enable_ops[cpu] = smp_get_enable_ops(enable_method);
357 if (!smp_enable_ops[cpu]) {
358 pr_err("%s: invalid enable-method property: %s\n",
359 dn->full_name, enable_method);
363 if (smp_enable_ops[cpu]->init_cpu(dn, cpu))
366 pr_debug("cpu logical map 0x%llx\n", hwid);
367 cpu_logical_map(cpu) = hwid;
374 pr_warning("no. of cores (%d) greater than configured maximum of %d - clipping\n",
377 if (!bootcpu_valid) {
378 pr_err("DT missing boot CPU MPIDR, not enabling secondaries\n");
383 * All the cpus that made it to the cpu_logical_map have been
384 * validated so set them as possible cpus.
386 for (i = 0; i < NR_CPUS; i++)
387 if (cpu_logical_map(i) != INVALID_HWID)
388 set_cpu_possible(i, true);
391 void __init smp_prepare_cpus(unsigned int max_cpus)
394 unsigned int ncores = num_possible_cpus();
398 smp_store_cpu_info(smp_processor_id());
401 * are we trying to boot more cores than exist?
403 if (max_cpus > ncores)
406 /* Don't bother if we're effectively UP */
411 * Initialise the present map (which describes the set of CPUs
412 * actually populated at the present time) and release the
413 * secondaries from the bootloader.
415 * Make sure we online at most (max_cpus - 1) additional CPUs.
418 for_each_possible_cpu(cpu) {
422 if (cpu == smp_processor_id())
425 if (!smp_enable_ops[cpu])
428 err = smp_enable_ops[cpu]->prepare_cpu(cpu);
432 set_cpu_present(cpu, true);
438 void __init set_smp_cross_call(void (*fn)(const struct cpumask *, unsigned int))
443 void arch_send_call_function_ipi_mask(const struct cpumask *mask)
445 smp_cross_call(mask, IPI_CALL_FUNC);
448 void arch_send_call_function_single_ipi(int cpu)
450 smp_cross_call(cpumask_of(cpu), IPI_CALL_FUNC_SINGLE);
453 static const char *ipi_types[NR_IPI] = {
454 #define S(x,s) [x - IPI_RESCHEDULE] = s
455 S(IPI_RESCHEDULE, "Rescheduling interrupts"),
456 S(IPI_CALL_FUNC, "Function call interrupts"),
457 S(IPI_CALL_FUNC_SINGLE, "Single function call interrupts"),
458 S(IPI_CPU_STOP, "CPU stop interrupts"),
461 void show_ipi_list(struct seq_file *p, int prec)
465 for (i = 0; i < NR_IPI; i++) {
466 seq_printf(p, "%*s%u:%s", prec - 1, "IPI", i + IPI_RESCHEDULE,
467 prec >= 4 ? " " : "");
468 for_each_present_cpu(cpu)
469 seq_printf(p, "%10u ",
470 __get_irq_stat(cpu, ipi_irqs[i]));
471 seq_printf(p, " %s\n", ipi_types[i]);
475 u64 smp_irq_stat_cpu(unsigned int cpu)
480 for (i = 0; i < NR_IPI; i++)
481 sum += __get_irq_stat(cpu, ipi_irqs[i]);
486 static DEFINE_RAW_SPINLOCK(stop_lock);
489 * ipi_cpu_stop - handle IPI from smp_send_stop()
491 static void ipi_cpu_stop(unsigned int cpu)
493 if (system_state == SYSTEM_BOOTING ||
494 system_state == SYSTEM_RUNNING) {
495 raw_spin_lock(&stop_lock);
496 pr_crit("CPU%u: stopping\n", cpu);
498 raw_spin_unlock(&stop_lock);
501 set_cpu_online(cpu, false);
511 * Main handler for inter-processor interrupts
513 void handle_IPI(int ipinr, struct pt_regs *regs)
515 unsigned int cpu = smp_processor_id();
516 struct pt_regs *old_regs = set_irq_regs(regs);
518 if (ipinr >= IPI_RESCHEDULE && ipinr < IPI_RESCHEDULE + NR_IPI)
519 __inc_irq_stat(cpu, ipi_irqs[ipinr - IPI_RESCHEDULE]);
528 generic_smp_call_function_interrupt();
532 case IPI_CALL_FUNC_SINGLE:
534 generic_smp_call_function_single_interrupt();
545 pr_crit("CPU%u: Unknown IPI message 0x%x\n", cpu, ipinr);
548 set_irq_regs(old_regs);
551 void smp_send_reschedule(int cpu)
553 smp_cross_call(cpumask_of(cpu), IPI_RESCHEDULE);
556 void smp_send_stop(void)
558 unsigned long timeout;
560 if (num_online_cpus() > 1) {
563 cpumask_copy(&mask, cpu_online_mask);
564 cpu_clear(smp_processor_id(), mask);
566 smp_cross_call(&mask, IPI_CPU_STOP);
569 /* Wait up to one second for other CPUs to stop */
570 timeout = USEC_PER_SEC;
571 while (num_online_cpus() > 1 && timeout--)
574 if (num_online_cpus() > 1)
575 pr_warning("SMP: failed to stop secondary CPUs\n");
581 int setup_profiling_timer(unsigned int multiplier)