2 * Based on arch/arm/kernel/setup.c
4 * Copyright (C) 1995-2001 Russell King
5 * Copyright (C) 2012 ARM Ltd.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 #include <linux/export.h>
21 #include <linux/kernel.h>
22 #include <linux/stddef.h>
23 #include <linux/ioport.h>
24 #include <linux/delay.h>
25 #include <linux/utsname.h>
26 #include <linux/initrd.h>
27 #include <linux/console.h>
28 #include <linux/bootmem.h>
29 #include <linux/seq_file.h>
30 #include <linux/screen_info.h>
31 #include <linux/init.h>
32 #include <linux/kexec.h>
33 #include <linux/crash_dump.h>
34 #include <linux/root_dev.h>
35 #include <linux/clk-provider.h>
36 #include <linux/cpu.h>
37 #include <linux/interrupt.h>
38 #include <linux/smp.h>
40 #include <linux/proc_fs.h>
41 #include <linux/memblock.h>
42 #include <linux/of_fdt.h>
43 #include <linux/of_platform.h>
45 #include <asm/fixmap.h>
46 #include <asm/cputype.h>
48 #include <asm/cputable.h>
49 #include <asm/cpu_ops.h>
50 #include <asm/sections.h>
51 #include <asm/setup.h>
52 #include <asm/smp_plat.h>
53 #include <asm/cacheflush.h>
54 #include <asm/tlbflush.h>
55 #include <asm/traps.h>
56 #include <asm/memblock.h>
59 unsigned int processor_id;
60 EXPORT_SYMBOL(processor_id);
62 unsigned long elf_hwcap __read_mostly;
63 EXPORT_SYMBOL_GPL(elf_hwcap);
66 #define COMPAT_ELF_HWCAP_DEFAULT \
67 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
68 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
69 COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\
70 COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\
71 COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV)
72 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
73 unsigned int compat_elf_hwcap2 __read_mostly;
76 static const char *cpu_name;
77 static const char *machine_name;
78 phys_addr_t __fdt_pointer __initdata;
81 * Standard memory resources
83 static struct resource mem_res[] = {
85 .name = "Kernel code",
88 .flags = IORESOURCE_MEM
91 .name = "Kernel data",
94 .flags = IORESOURCE_MEM
98 #define kernel_code mem_res[0]
99 #define kernel_data mem_res[1]
101 void __init early_print(const char *str, ...)
107 vsnprintf(buf, sizeof(buf), str, ap);
113 void __init smp_setup_processor_id(void)
116 * clear __my_cpu_offset on boot CPU to avoid hang caused by
117 * using percpu variable early, for example, lockdep will
118 * access percpu variable inside lock_release
120 set_my_cpu_offset(0);
123 bool arch_match_cpu_phys_id(int cpu, u64 phys_id)
125 return phys_id == cpu_logical_map(cpu);
128 struct mpidr_hash mpidr_hash;
131 * smp_build_mpidr_hash - Pre-compute shifts required at each affinity
132 * level in order to build a linear index from an
133 * MPIDR value. Resulting algorithm is a collision
134 * free hash carried out through shifting and ORing
136 static void __init smp_build_mpidr_hash(void)
138 u32 i, affinity, fs[4], bits[4], ls;
141 * Pre-scan the list of MPIDRS and filter out bits that do
142 * not contribute to affinity levels, ie they never toggle.
144 for_each_possible_cpu(i)
145 mask |= (cpu_logical_map(i) ^ cpu_logical_map(0));
146 pr_debug("mask of set bits %#llx\n", mask);
148 * Find and stash the last and first bit set at all affinity levels to
149 * check how many bits are required to represent them.
151 for (i = 0; i < 4; i++) {
152 affinity = MPIDR_AFFINITY_LEVEL(mask, i);
154 * Find the MSB bit and LSB bits position
155 * to determine how many bits are required
156 * to express the affinity level.
159 fs[i] = affinity ? ffs(affinity) - 1 : 0;
160 bits[i] = ls - fs[i];
163 * An index can be created from the MPIDR_EL1 by isolating the
164 * significant bits at each affinity level and by shifting
165 * them in order to compress the 32 bits values space to a
166 * compressed set of values. This is equivalent to hashing
167 * the MPIDR_EL1 through shifting and ORing. It is a collision free
168 * hash though not minimal since some levels might contain a number
169 * of CPUs that is not an exact power of 2 and their bit
170 * representation might contain holes, eg MPIDR_EL1[7:0] = {0x2, 0x80}.
172 mpidr_hash.shift_aff[0] = MPIDR_LEVEL_SHIFT(0) + fs[0];
173 mpidr_hash.shift_aff[1] = MPIDR_LEVEL_SHIFT(1) + fs[1] - bits[0];
174 mpidr_hash.shift_aff[2] = MPIDR_LEVEL_SHIFT(2) + fs[2] -
176 mpidr_hash.shift_aff[3] = MPIDR_LEVEL_SHIFT(3) +
177 fs[3] - (bits[2] + bits[1] + bits[0]);
178 mpidr_hash.mask = mask;
179 mpidr_hash.bits = bits[3] + bits[2] + bits[1] + bits[0];
180 pr_debug("MPIDR hash: aff0[%u] aff1[%u] aff2[%u] aff3[%u] mask[%#llx] bits[%u]\n",
181 mpidr_hash.shift_aff[0],
182 mpidr_hash.shift_aff[1],
183 mpidr_hash.shift_aff[2],
184 mpidr_hash.shift_aff[3],
188 * 4x is an arbitrary value used to warn on a hash table much bigger
189 * than expected on most systems.
191 if (mpidr_hash_size() > 4 * num_possible_cpus())
192 pr_warn("Large number of MPIDR hash buckets detected\n");
193 __flush_dcache_area(&mpidr_hash, sizeof(struct mpidr_hash));
197 static void __init setup_processor(void)
199 struct cpu_info *cpu_info;
202 cpu_info = lookup_processor_type(read_cpuid_id());
204 printk("CPU configuration botched (ID %08x), unable to continue.\n",
209 cpu_name = cpu_info->cpu_name;
211 printk("CPU: %s [%08x] revision %d\n",
212 cpu_name, read_cpuid_id(), read_cpuid_id() & 15);
214 sprintf(init_utsname()->machine, ELF_PLATFORM);
218 * ID_AA64ISAR0_EL1 contains 4-bit wide signed feature blocks.
219 * The blocks we test below represent incremental functionality
220 * for non-negative values. Negative values are reserved.
222 features = read_cpuid(ID_AA64ISAR0_EL1);
223 block = (features >> 4) & 0xf;
224 if (!(block & 0x8)) {
228 elf_hwcap |= HWCAP_PMULL;
230 elf_hwcap |= HWCAP_AES;
236 block = (features >> 8) & 0xf;
237 if (block && !(block & 0x8))
238 elf_hwcap |= HWCAP_SHA1;
240 block = (features >> 12) & 0xf;
241 if (block && !(block & 0x8))
242 elf_hwcap |= HWCAP_SHA2;
244 block = (features >> 16) & 0xf;
245 if (block && !(block & 0x8))
246 elf_hwcap |= HWCAP_CRC32;
250 * ID_ISAR5_EL1 carries similar information as above, but pertaining to
251 * the Aarch32 32-bit execution state.
253 features = read_cpuid(ID_ISAR5_EL1);
254 block = (features >> 4) & 0xf;
255 if (!(block & 0x8)) {
259 compat_elf_hwcap2 |= COMPAT_HWCAP2_PMULL;
261 compat_elf_hwcap2 |= COMPAT_HWCAP2_AES;
267 block = (features >> 8) & 0xf;
268 if (block && !(block & 0x8))
269 compat_elf_hwcap2 |= COMPAT_HWCAP2_SHA1;
271 block = (features >> 12) & 0xf;
272 if (block && !(block & 0x8))
273 compat_elf_hwcap2 |= COMPAT_HWCAP2_SHA2;
275 block = (features >> 16) & 0xf;
276 if (block && !(block & 0x8))
277 compat_elf_hwcap2 |= COMPAT_HWCAP2_CRC32;
281 static void __init setup_machine_fdt(phys_addr_t dt_phys)
283 if (!dt_phys || !early_init_dt_scan(phys_to_virt(dt_phys))) {
285 "Error: invalid device tree blob at physical address 0x%p (virtual address 0x%p)\n"
286 "The dtb must be 8-byte aligned and passed in the first 512MB of memory\n"
287 "\nPlease check your bootloader.\n",
288 dt_phys, phys_to_virt(dt_phys));
294 machine_name = of_flat_dt_get_machine_name();
298 * Limit the memory size that was specified via FDT.
300 static int __init early_mem(char *p)
307 limit = memparse(p, &p) & PAGE_MASK;
308 pr_notice("Memory limited to %lldMB\n", limit >> 20);
310 memblock_enforce_memory_limit(limit);
314 early_param("mem", early_mem);
316 static void __init request_standard_resources(void)
318 struct memblock_region *region;
319 struct resource *res;
321 kernel_code.start = virt_to_phys(_text);
322 kernel_code.end = virt_to_phys(_etext - 1);
323 kernel_data.start = virt_to_phys(_sdata);
324 kernel_data.end = virt_to_phys(_end - 1);
326 for_each_memblock(memory, region) {
327 res = alloc_bootmem_low(sizeof(*res));
328 res->name = "System RAM";
329 res->start = __pfn_to_phys(memblock_region_memory_base_pfn(region));
330 res->end = __pfn_to_phys(memblock_region_memory_end_pfn(region)) - 1;
331 res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
333 request_resource(&iomem_resource, res);
335 if (kernel_code.start >= res->start &&
336 kernel_code.end <= res->end)
337 request_resource(res, &kernel_code);
338 if (kernel_data.start >= res->start &&
339 kernel_data.end <= res->end)
340 request_resource(res, &kernel_data);
344 u64 __cpu_logical_map[NR_CPUS] = { [0 ... NR_CPUS-1] = INVALID_HWID };
346 void __init setup_arch(char **cmdline_p)
349 * Unmask asynchronous aborts early to catch possible system errors.
351 local_async_enable();
355 setup_machine_fdt(__fdt_pointer);
357 init_mm.start_code = (unsigned long) _text;
358 init_mm.end_code = (unsigned long) _etext;
359 init_mm.end_data = (unsigned long) _edata;
360 init_mm.brk = (unsigned long) _end;
362 *cmdline_p = boot_command_line;
365 early_ioremap_init();
369 arm64_memblock_init();
372 request_standard_resources();
374 unflatten_device_tree();
378 cpu_logical_map(0) = read_cpuid_mpidr() & MPIDR_HWID_BITMASK;
379 cpu_read_bootcpu_ops();
382 smp_build_mpidr_hash();
386 #if defined(CONFIG_VGA_CONSOLE)
387 conswitchp = &vga_con;
388 #elif defined(CONFIG_DUMMY_CONSOLE)
389 conswitchp = &dummy_con;
394 static int __init arm64_device_init(void)
396 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
399 arch_initcall(arm64_device_init);
401 static DEFINE_PER_CPU(struct cpu, cpu_data);
403 static int __init topology_init(void)
407 for_each_possible_cpu(i) {
408 struct cpu *cpu = &per_cpu(cpu_data, i);
409 cpu->hotpluggable = 1;
410 register_cpu(cpu, i);
415 subsys_initcall(topology_init);
417 static const char *hwcap_str[] = {
429 static int c_show(struct seq_file *m, void *v)
433 seq_printf(m, "Processor\t: %s rev %d (%s)\n",
434 cpu_name, read_cpuid_id() & 15, ELF_PLATFORM);
436 for_each_online_cpu(i) {
438 * glibc reads /proc/cpuinfo to determine the number of
439 * online processors, looking for lines beginning with
440 * "processor". Give glibc what it expects.
443 seq_printf(m, "processor\t: %d\n", i);
447 /* dump out the processor features */
448 seq_puts(m, "Features\t: ");
450 for (i = 0; hwcap_str[i]; i++)
451 if (elf_hwcap & (1 << i))
452 seq_printf(m, "%s ", hwcap_str[i]);
454 seq_printf(m, "\nCPU implementer\t: 0x%02x\n", read_cpuid_id() >> 24);
455 seq_printf(m, "CPU architecture: AArch64\n");
456 seq_printf(m, "CPU variant\t: 0x%x\n", (read_cpuid_id() >> 20) & 15);
457 seq_printf(m, "CPU part\t: 0x%03x\n", (read_cpuid_id() >> 4) & 0xfff);
458 seq_printf(m, "CPU revision\t: %d\n", read_cpuid_id() & 15);
462 seq_printf(m, "Hardware\t: %s\n", machine_name);
467 static void *c_start(struct seq_file *m, loff_t *pos)
469 return *pos < 1 ? (void *)1 : NULL;
472 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
478 static void c_stop(struct seq_file *m, void *v)
482 const struct seq_operations cpuinfo_op = {