2 * Based on arch/arm/kernel/setup.c
4 * Copyright (C) 1995-2001 Russell King
5 * Copyright (C) 2012 ARM Ltd.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 #include <linux/export.h>
21 #include <linux/kernel.h>
22 #include <linux/stddef.h>
23 #include <linux/ioport.h>
24 #include <linux/delay.h>
25 #include <linux/utsname.h>
26 #include <linux/initrd.h>
27 #include <linux/console.h>
28 #include <linux/bootmem.h>
29 #include <linux/seq_file.h>
30 #include <linux/screen_info.h>
31 #include <linux/init.h>
32 #include <linux/kexec.h>
33 #include <linux/crash_dump.h>
34 #include <linux/root_dev.h>
35 #include <linux/clk-provider.h>
36 #include <linux/cpu.h>
37 #include <linux/interrupt.h>
38 #include <linux/smp.h>
40 #include <linux/proc_fs.h>
41 #include <linux/memblock.h>
42 #include <linux/of_fdt.h>
43 #include <linux/of_platform.h>
45 #include <asm/cputype.h>
47 #include <asm/cputable.h>
48 #include <asm/sections.h>
49 #include <asm/setup.h>
50 #include <asm/smp_plat.h>
51 #include <asm/cacheflush.h>
52 #include <asm/tlbflush.h>
53 #include <asm/traps.h>
54 #include <asm/memblock.h>
57 unsigned int processor_id;
58 EXPORT_SYMBOL(processor_id);
60 unsigned long elf_hwcap __read_mostly;
61 EXPORT_SYMBOL_GPL(elf_hwcap);
64 #define COMPAT_ELF_HWCAP_DEFAULT \
65 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
66 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
67 COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\
68 COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\
69 COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV)
70 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
71 unsigned int compat_elf_hwcap2 __read_mostly;
74 static const char *cpu_name;
75 static const char *machine_name;
76 phys_addr_t __fdt_pointer __initdata;
79 * Standard memory resources
81 static struct resource mem_res[] = {
83 .name = "Kernel code",
86 .flags = IORESOURCE_MEM
89 .name = "Kernel data",
92 .flags = IORESOURCE_MEM
96 #define kernel_code mem_res[0]
97 #define kernel_data mem_res[1]
99 void __init early_print(const char *str, ...)
105 vsnprintf(buf, sizeof(buf), str, ap);
111 static void __init setup_processor(void)
113 struct cpu_info *cpu_info;
117 * locate processor in the list of supported processor
118 * types. The linker builds this table for us from the
119 * entries in arch/arm/mm/proc.S
121 cpu_info = lookup_processor_type(read_cpuid_id());
123 printk("CPU configuration botched (ID %08x), unable to continue.\n",
128 cpu_name = cpu_info->cpu_name;
130 printk("CPU: %s [%08x] revision %d\n",
131 cpu_name, read_cpuid_id(), read_cpuid_id() & 15);
133 sprintf(init_utsname()->machine, "aarch64");
137 * ID_AA64ISAR0_EL1 contains 4-bit wide signed feature blocks.
138 * The blocks we test below represent incremental functionality
139 * for non-negative values. Negative values are reserved.
141 features = read_cpuid(ID_AA64ISAR0_EL1);
142 block = (features >> 4) & 0xf;
143 if (!(block & 0x8)) {
147 elf_hwcap |= HWCAP_PMULL;
149 elf_hwcap |= HWCAP_AES;
155 block = (features >> 8) & 0xf;
156 if (block && !(block & 0x8))
157 elf_hwcap |= HWCAP_SHA1;
159 block = (features >> 12) & 0xf;
160 if (block && !(block & 0x8))
161 elf_hwcap |= HWCAP_SHA2;
163 block = (features >> 16) & 0xf;
164 if (block && !(block & 0x8))
165 elf_hwcap |= HWCAP_CRC32;
169 * ID_ISAR5_EL1 carries similar information as above, but pertaining to
170 * the Aarch32 32-bit execution state.
172 features = read_cpuid(ID_ISAR5_EL1);
173 block = (features >> 4) & 0xf;
174 if (!(block & 0x8)) {
178 compat_elf_hwcap2 |= COMPAT_HWCAP2_PMULL;
180 compat_elf_hwcap2 |= COMPAT_HWCAP2_AES;
186 block = (features >> 8) & 0xf;
187 if (block && !(block & 0x8))
188 compat_elf_hwcap2 |= COMPAT_HWCAP2_SHA1;
190 block = (features >> 12) & 0xf;
191 if (block && !(block & 0x8))
192 compat_elf_hwcap2 |= COMPAT_HWCAP2_SHA2;
194 block = (features >> 16) & 0xf;
195 if (block && !(block & 0x8))
196 compat_elf_hwcap2 |= COMPAT_HWCAP2_CRC32;
200 static void __init setup_machine_fdt(phys_addr_t dt_phys)
202 struct boot_param_header *devtree;
203 unsigned long dt_root;
205 /* Check we have a non-NULL DT pointer */
208 "Error: NULL or invalid device tree blob\n"
209 "The dtb must be 8-byte aligned and passed in the first 512MB of memory\n"
210 "\nPlease check your bootloader.\n");
217 devtree = phys_to_virt(dt_phys);
219 /* Check device tree validity */
220 if (be32_to_cpu(devtree->magic) != OF_DT_HEADER) {
222 "Error: invalid device tree blob at physical address 0x%p (virtual address 0x%p)\n"
223 "Expected 0x%x, found 0x%x\n"
224 "\nPlease check your bootloader.\n",
225 dt_phys, devtree, OF_DT_HEADER,
226 be32_to_cpu(devtree->magic));
232 initial_boot_params = devtree;
233 dt_root = of_get_flat_dt_root();
235 machine_name = of_get_flat_dt_prop(dt_root, "model", NULL);
237 machine_name = of_get_flat_dt_prop(dt_root, "compatible", NULL);
239 machine_name = "<unknown>";
240 pr_info("Machine: %s\n", machine_name);
242 /* Retrieve various information from the /chosen node */
243 of_scan_flat_dt(early_init_dt_scan_chosen, boot_command_line);
244 /* Initialize {size,address}-cells info */
245 of_scan_flat_dt(early_init_dt_scan_root, NULL);
246 /* Setup memory, calling early_init_dt_add_memory_arch */
247 of_scan_flat_dt(early_init_dt_scan_memory, NULL);
250 void __init early_init_dt_add_memory_arch(u64 base, u64 size)
254 if (base + size < PHYS_OFFSET) {
255 pr_warning("Ignoring memory block 0x%llx - 0x%llx\n",
259 if (base < PHYS_OFFSET) {
260 pr_warning("Ignoring memory range 0x%llx - 0x%llx\n",
262 size -= PHYS_OFFSET - base;
265 memblock_add(base, size);
268 void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align)
270 return __va(memblock_alloc(size, align));
274 * Limit the memory size that was specified via FDT.
276 static int __init early_mem(char *p)
283 limit = memparse(p, &p) & PAGE_MASK;
284 pr_notice("Memory limited to %lldMB\n", limit >> 20);
286 memblock_enforce_memory_limit(limit);
290 early_param("mem", early_mem);
292 static void __init request_standard_resources(void)
294 struct memblock_region *region;
295 struct resource *res;
297 kernel_code.start = virt_to_phys(_text);
298 kernel_code.end = virt_to_phys(_etext - 1);
299 kernel_data.start = virt_to_phys(_sdata);
300 kernel_data.end = virt_to_phys(_end - 1);
302 for_each_memblock(memory, region) {
303 res = alloc_bootmem_low(sizeof(*res));
304 res->name = "System RAM";
305 res->start = __pfn_to_phys(memblock_region_memory_base_pfn(region));
306 res->end = __pfn_to_phys(memblock_region_memory_end_pfn(region)) - 1;
307 res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
309 request_resource(&iomem_resource, res);
311 if (kernel_code.start >= res->start &&
312 kernel_code.end <= res->end)
313 request_resource(res, &kernel_code);
314 if (kernel_data.start >= res->start &&
315 kernel_data.end <= res->end)
316 request_resource(res, &kernel_data);
320 u64 __cpu_logical_map[NR_CPUS] = { [0 ... NR_CPUS-1] = INVALID_HWID };
322 void __init setup_arch(char **cmdline_p)
326 setup_machine_fdt(__fdt_pointer);
328 init_mm.start_code = (unsigned long) _text;
329 init_mm.end_code = (unsigned long) _etext;
330 init_mm.end_data = (unsigned long) _edata;
331 init_mm.brk = (unsigned long) _end;
333 *cmdline_p = boot_command_line;
337 arm64_memblock_init();
340 request_standard_resources();
342 unflatten_device_tree();
346 cpu_logical_map(0) = read_cpuid_mpidr() & MPIDR_HWID_BITMASK;
352 #if defined(CONFIG_VGA_CONSOLE)
353 conswitchp = &vga_con;
354 #elif defined(CONFIG_DUMMY_CONSOLE)
355 conswitchp = &dummy_con;
360 static int __init arm64_device_init(void)
363 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
366 arch_initcall(arm64_device_init);
368 static DEFINE_PER_CPU(struct cpu, cpu_data);
370 static int __init topology_init(void)
374 for_each_possible_cpu(i) {
375 struct cpu *cpu = &per_cpu(cpu_data, i);
376 cpu->hotpluggable = 1;
377 register_cpu(cpu, i);
382 subsys_initcall(topology_init);
384 static const char *hwcap_str[] = {
396 static int c_show(struct seq_file *m, void *v)
400 seq_printf(m, "Processor\t: %s rev %d (%s)\n",
401 cpu_name, read_cpuid_id() & 15, ELF_PLATFORM);
403 for_each_online_cpu(i) {
405 * glibc reads /proc/cpuinfo to determine the number of
406 * online processors, looking for lines beginning with
407 * "processor". Give glibc what it expects.
410 seq_printf(m, "processor\t: %d\n", i);
412 seq_printf(m, "BogoMIPS\t: %lu.%02lu\n\n",
413 loops_per_jiffy / (500000UL/HZ),
414 loops_per_jiffy / (5000UL/HZ) % 100);
417 /* dump out the processor features */
418 seq_puts(m, "Features\t: ");
420 for (i = 0; hwcap_str[i]; i++)
421 if (elf_hwcap & (1 << i))
422 seq_printf(m, "%s ", hwcap_str[i]);
423 #ifdef CONFIG_ARMV7_COMPAT_CPUINFO
424 /* Print out the non-optional ARMv8 HW capabilities */
425 seq_printf(m, "wp half thumb fastmult vfp edsp neon vfpv3d16 tlsi ");
426 seq_printf(m, "vfpv4 idiva idivt ");
429 seq_printf(m, "\nCPU implementer\t: 0x%02x\n", read_cpuid_id() >> 24);
430 seq_printf(m, "CPU architecture: 8\n");
431 seq_printf(m, "CPU variant\t: 0x%x\n", (read_cpuid_id() >> 20) & 15);
432 seq_printf(m, "CPU part\t: 0x%03x\n", (read_cpuid_id() >> 4) & 0xfff);
433 seq_printf(m, "CPU revision\t: %d\n", read_cpuid_id() & 15);
437 seq_printf(m, "Hardware\t: %s\n", machine_name);
442 static void *c_start(struct seq_file *m, loff_t *pos)
444 return *pos < 1 ? (void *)1 : NULL;
447 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
453 static void c_stop(struct seq_file *m, void *v)
457 const struct seq_operations cpuinfo_op = {