4 * Copyright (C) 2012 ARM Limited
5 * Author: Will Deacon <will.deacon@arm.com>
7 * This code is based heavily on the ARMv7 perf event code.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 #define pr_fmt(fmt) "hw perfevents: " fmt
23 #include <linux/bitmap.h>
24 #include <linux/interrupt.h>
25 #include <linux/irq.h>
26 #include <linux/kernel.h>
27 #include <linux/export.h>
28 #include <linux/perf_event.h>
29 #include <linux/platform_device.h>
30 #include <linux/spinlock.h>
31 #include <linux/uaccess.h>
33 #include <asm/cputype.h>
35 #include <asm/irq_regs.h>
37 #include <asm/stacktrace.h>
40 * ARMv8 supports a maximum of 32 events.
41 * The cycle counter is included in this total.
43 #define ARMPMU_MAX_HWEVENTS 32
45 static DEFINE_PER_CPU(struct perf_event * [ARMPMU_MAX_HWEVENTS], hw_events);
46 static DEFINE_PER_CPU(unsigned long [BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)], used_mask);
47 static DEFINE_PER_CPU(struct pmu_hw_events, cpu_hw_events);
49 #define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu))
51 /* Set at runtime when we know what CPU type we are. */
52 static struct arm_pmu *cpu_pmu;
55 armpmu_get_max_events(void)
60 max_events = cpu_pmu->num_events;
64 EXPORT_SYMBOL_GPL(armpmu_get_max_events);
66 int perf_num_counters(void)
68 return armpmu_get_max_events();
70 EXPORT_SYMBOL_GPL(perf_num_counters);
72 #define HW_OP_UNSUPPORTED 0xFFFF
75 PERF_COUNT_HW_CACHE_##_x
77 #define CACHE_OP_UNSUPPORTED 0xFFFF
80 armpmu_map_cache_event(const unsigned (*cache_map)
81 [PERF_COUNT_HW_CACHE_MAX]
82 [PERF_COUNT_HW_CACHE_OP_MAX]
83 [PERF_COUNT_HW_CACHE_RESULT_MAX],
86 unsigned int cache_type, cache_op, cache_result, ret;
88 cache_type = (config >> 0) & 0xff;
89 if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
92 cache_op = (config >> 8) & 0xff;
93 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
96 cache_result = (config >> 16) & 0xff;
97 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
100 ret = (int)(*cache_map)[cache_type][cache_op][cache_result];
102 if (ret == CACHE_OP_UNSUPPORTED)
109 armpmu_map_event(const unsigned (*event_map)[PERF_COUNT_HW_MAX], u64 config)
113 if (config >= PERF_COUNT_HW_MAX)
116 mapping = (*event_map)[config];
117 return mapping == HW_OP_UNSUPPORTED ? -ENOENT : mapping;
121 armpmu_map_raw_event(u32 raw_event_mask, u64 config)
123 return (int)(config & raw_event_mask);
126 static int map_cpu_event(struct perf_event *event,
127 const unsigned (*event_map)[PERF_COUNT_HW_MAX],
128 const unsigned (*cache_map)
129 [PERF_COUNT_HW_CACHE_MAX]
130 [PERF_COUNT_HW_CACHE_OP_MAX]
131 [PERF_COUNT_HW_CACHE_RESULT_MAX],
134 u64 config = event->attr.config;
136 switch (event->attr.type) {
137 case PERF_TYPE_HARDWARE:
138 return armpmu_map_event(event_map, config);
139 case PERF_TYPE_HW_CACHE:
140 return armpmu_map_cache_event(cache_map, config);
142 return armpmu_map_raw_event(raw_event_mask, config);
149 armpmu_event_set_period(struct perf_event *event,
150 struct hw_perf_event *hwc,
153 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
154 s64 left = local64_read(&hwc->period_left);
155 s64 period = hwc->sample_period;
158 if (unlikely(left <= -period)) {
160 local64_set(&hwc->period_left, left);
161 hwc->last_period = period;
165 if (unlikely(left <= 0)) {
167 local64_set(&hwc->period_left, left);
168 hwc->last_period = period;
172 if (left > (s64)armpmu->max_period)
173 left = armpmu->max_period;
175 local64_set(&hwc->prev_count, (u64)-left);
177 armpmu->write_counter(idx, (u64)(-left) & 0xffffffff);
179 perf_event_update_userpage(event);
185 armpmu_event_update(struct perf_event *event,
186 struct hw_perf_event *hwc,
189 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
190 u64 delta, prev_raw_count, new_raw_count;
193 prev_raw_count = local64_read(&hwc->prev_count);
194 new_raw_count = armpmu->read_counter(idx);
196 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
197 new_raw_count) != prev_raw_count)
200 delta = (new_raw_count - prev_raw_count) & armpmu->max_period;
202 local64_add(delta, &event->count);
203 local64_sub(delta, &hwc->period_left);
205 return new_raw_count;
209 armpmu_read(struct perf_event *event)
211 struct hw_perf_event *hwc = &event->hw;
213 /* Don't read disabled counters! */
217 armpmu_event_update(event, hwc, hwc->idx);
221 armpmu_stop(struct perf_event *event, int flags)
223 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
224 struct hw_perf_event *hwc = &event->hw;
227 * ARM pmu always has to update the counter, so ignore
228 * PERF_EF_UPDATE, see comments in armpmu_start().
230 if (!(hwc->state & PERF_HES_STOPPED)) {
231 armpmu->disable(hwc, hwc->idx);
232 barrier(); /* why? */
233 armpmu_event_update(event, hwc, hwc->idx);
234 hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
239 armpmu_start(struct perf_event *event, int flags)
241 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
242 struct hw_perf_event *hwc = &event->hw;
245 * ARM pmu always has to reprogram the period, so ignore
246 * PERF_EF_RELOAD, see the comment below.
248 if (flags & PERF_EF_RELOAD)
249 WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
253 * Set the period again. Some counters can't be stopped, so when we
254 * were stopped we simply disabled the IRQ source and the counter
255 * may have been left counting. If we don't do this step then we may
256 * get an interrupt too soon or *way* too late if the overflow has
257 * happened since disabling.
259 armpmu_event_set_period(event, hwc, hwc->idx);
260 armpmu->enable(hwc, hwc->idx);
264 armpmu_del(struct perf_event *event, int flags)
266 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
267 struct pmu_hw_events *hw_events = armpmu->get_hw_events();
268 struct hw_perf_event *hwc = &event->hw;
273 armpmu_stop(event, PERF_EF_UPDATE);
274 hw_events->events[idx] = NULL;
275 clear_bit(idx, hw_events->used_mask);
277 perf_event_update_userpage(event);
281 armpmu_add(struct perf_event *event, int flags)
283 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
284 struct pmu_hw_events *hw_events = armpmu->get_hw_events();
285 struct hw_perf_event *hwc = &event->hw;
289 perf_pmu_disable(event->pmu);
291 /* If we don't have a space for the counter then finish early. */
292 idx = armpmu->get_event_idx(hw_events, hwc);
299 * If there is an event in the counter we are going to use then make
300 * sure it is disabled.
303 armpmu->disable(hwc, idx);
304 hw_events->events[idx] = event;
306 hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
307 if (flags & PERF_EF_START)
308 armpmu_start(event, PERF_EF_RELOAD);
310 /* Propagate our changes to the userspace mapping. */
311 perf_event_update_userpage(event);
314 perf_pmu_enable(event->pmu);
319 validate_event(struct pmu_hw_events *hw_events,
320 struct perf_event *event)
322 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
323 struct hw_perf_event fake_event = event->hw;
324 struct pmu *leader_pmu = event->group_leader->pmu;
326 if (is_software_event(event))
329 if (event->pmu != leader_pmu || event->state < PERF_EVENT_STATE_OFF)
332 if (event->state == PERF_EVENT_STATE_OFF && !event->attr.enable_on_exec)
335 return armpmu->get_event_idx(hw_events, &fake_event) >= 0;
339 validate_group(struct perf_event *event)
341 struct perf_event *sibling, *leader = event->group_leader;
342 struct pmu_hw_events fake_pmu;
343 DECLARE_BITMAP(fake_used_mask, ARMPMU_MAX_HWEVENTS);
346 * Initialise the fake PMU. We only need to populate the
347 * used_mask for the purposes of validation.
349 memset(fake_used_mask, 0, sizeof(fake_used_mask));
350 fake_pmu.used_mask = fake_used_mask;
352 if (!validate_event(&fake_pmu, leader))
355 list_for_each_entry(sibling, &leader->sibling_list, group_entry) {
356 if (!validate_event(&fake_pmu, sibling))
360 if (!validate_event(&fake_pmu, event))
367 armpmu_disable_percpu_irq(void *data)
369 unsigned int irq = *(unsigned int *)data;
370 disable_percpu_irq(irq);
374 armpmu_release_hardware(struct arm_pmu *armpmu)
377 unsigned int i, irqs;
378 struct platform_device *pmu_device = armpmu->plat_device;
380 irqs = min(pmu_device->num_resources, num_possible_cpus());
384 irq = platform_get_irq(pmu_device, 0);
388 if (irq_is_percpu(irq)) {
389 on_each_cpu(armpmu_disable_percpu_irq, &irq, 1);
390 free_percpu_irq(irq, &cpu_hw_events);
392 for (i = 0; i < irqs; ++i) {
393 if (!cpumask_test_and_clear_cpu(i, &armpmu->active_irqs))
395 irq = platform_get_irq(pmu_device, i);
397 free_irq(irq, armpmu);
403 armpmu_enable_percpu_irq(void *data)
405 unsigned int irq = *(unsigned int *)data;
406 enable_percpu_irq(irq, IRQ_TYPE_NONE);
410 armpmu_reserve_hardware(struct arm_pmu *armpmu)
413 unsigned int i, irqs;
414 struct platform_device *pmu_device = armpmu->plat_device;
417 pr_err("no PMU device registered\n");
421 irqs = min(pmu_device->num_resources, num_possible_cpus());
423 pr_err("no irqs for PMUs defined\n");
427 irq = platform_get_irq(pmu_device, 0);
429 pr_err("failed to get valid irq for PMU device\n");
433 if (irq_is_percpu(irq)) {
434 err = request_percpu_irq(irq, armpmu->handle_irq,
435 "arm-pmu", &cpu_hw_events);
438 pr_err("unable to request percpu IRQ%d for ARM PMU counters\n",
440 armpmu_release_hardware(armpmu);
444 on_each_cpu(armpmu_enable_percpu_irq, &irq, 1);
446 for (i = 0; i < irqs; ++i) {
448 irq = platform_get_irq(pmu_device, i);
453 * If we have a single PMU interrupt that we can't shift,
454 * assume that we're running on a uniprocessor machine and
455 * continue. Otherwise, continue without this interrupt.
457 if (irq_set_affinity(irq, cpumask_of(i)) && irqs > 1) {
458 pr_warning("unable to set irq affinity (irq=%d, cpu=%u)\n",
463 err = request_irq(irq, armpmu->handle_irq,
467 pr_err("unable to request IRQ%d for ARM PMU counters\n",
469 armpmu_release_hardware(armpmu);
473 cpumask_set_cpu(i, &armpmu->active_irqs);
481 hw_perf_event_destroy(struct perf_event *event)
483 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
484 atomic_t *active_events = &armpmu->active_events;
485 struct mutex *pmu_reserve_mutex = &armpmu->reserve_mutex;
487 if (atomic_dec_and_mutex_lock(active_events, pmu_reserve_mutex)) {
488 armpmu_release_hardware(armpmu);
489 mutex_unlock(pmu_reserve_mutex);
494 event_requires_mode_exclusion(struct perf_event_attr *attr)
496 return attr->exclude_idle || attr->exclude_user ||
497 attr->exclude_kernel || attr->exclude_hv;
501 __hw_perf_event_init(struct perf_event *event)
503 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
504 struct hw_perf_event *hwc = &event->hw;
507 mapping = armpmu->map_event(event);
510 pr_debug("event %x:%llx not supported\n", event->attr.type,
516 * We don't assign an index until we actually place the event onto
517 * hardware. Use -1 to signify that we haven't decided where to put it
518 * yet. For SMP systems, each core has it's own PMU so we can't do any
519 * clever allocation or constraints checking at this point.
522 hwc->config_base = 0;
527 * Check whether we need to exclude the counter from certain modes.
529 if ((!armpmu->set_event_filter ||
530 armpmu->set_event_filter(hwc, &event->attr)) &&
531 event_requires_mode_exclusion(&event->attr)) {
532 pr_debug("ARM performance counters do not support mode exclusion\n");
537 * Store the event encoding into the config_base field.
539 hwc->config_base |= (unsigned long)mapping;
541 if (!hwc->sample_period) {
543 * For non-sampling runs, limit the sample_period to half
544 * of the counter width. That way, the new counter value
545 * is far less likely to overtake the previous one unless
546 * you have some serious IRQ latency issues.
548 hwc->sample_period = armpmu->max_period >> 1;
549 hwc->last_period = hwc->sample_period;
550 local64_set(&hwc->period_left, hwc->sample_period);
554 if (event->group_leader != event) {
555 err = validate_group(event);
563 static int armpmu_event_init(struct perf_event *event)
565 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
567 atomic_t *active_events = &armpmu->active_events;
569 if (armpmu->map_event(event) == -ENOENT)
572 event->destroy = hw_perf_event_destroy;
574 if (!atomic_inc_not_zero(active_events)) {
575 mutex_lock(&armpmu->reserve_mutex);
576 if (atomic_read(active_events) == 0)
577 err = armpmu_reserve_hardware(armpmu);
580 atomic_inc(active_events);
581 mutex_unlock(&armpmu->reserve_mutex);
587 err = __hw_perf_event_init(event);
589 hw_perf_event_destroy(event);
594 static void armpmu_enable(struct pmu *pmu)
596 struct arm_pmu *armpmu = to_arm_pmu(pmu);
597 struct pmu_hw_events *hw_events = armpmu->get_hw_events();
598 int enabled = bitmap_weight(hw_events->used_mask, armpmu->num_events);
604 static void armpmu_disable(struct pmu *pmu)
606 struct arm_pmu *armpmu = to_arm_pmu(pmu);
610 static void __init armpmu_init(struct arm_pmu *armpmu)
612 atomic_set(&armpmu->active_events, 0);
613 mutex_init(&armpmu->reserve_mutex);
615 armpmu->pmu = (struct pmu) {
616 .pmu_enable = armpmu_enable,
617 .pmu_disable = armpmu_disable,
618 .event_init = armpmu_event_init,
621 .start = armpmu_start,
627 int __init armpmu_register(struct arm_pmu *armpmu, char *name, int type)
630 return perf_pmu_register(&armpmu->pmu, name, type);
634 * ARMv8 PMUv3 Performance Events handling code.
635 * Common event types.
637 enum armv8_pmuv3_perf_types {
638 /* Required events. */
639 ARMV8_PMUV3_PERFCTR_PMNC_SW_INCR = 0x00,
640 ARMV8_PMUV3_PERFCTR_L1_DCACHE_REFILL = 0x03,
641 ARMV8_PMUV3_PERFCTR_L1_DCACHE_ACCESS = 0x04,
642 ARMV8_PMUV3_PERFCTR_PC_BRANCH_MIS_PRED = 0x10,
643 ARMV8_PMUV3_PERFCTR_CLOCK_CYCLES = 0x11,
644 ARMV8_PMUV3_PERFCTR_PC_BRANCH_PRED = 0x12,
646 /* At least one of the following is required. */
647 ARMV8_PMUV3_PERFCTR_INSTR_EXECUTED = 0x08,
648 ARMV8_PMUV3_PERFCTR_OP_SPEC = 0x1B,
650 /* Common architectural events. */
651 ARMV8_PMUV3_PERFCTR_MEM_READ = 0x06,
652 ARMV8_PMUV3_PERFCTR_MEM_WRITE = 0x07,
653 ARMV8_PMUV3_PERFCTR_EXC_TAKEN = 0x09,
654 ARMV8_PMUV3_PERFCTR_EXC_EXECUTED = 0x0A,
655 ARMV8_PMUV3_PERFCTR_CID_WRITE = 0x0B,
656 ARMV8_PMUV3_PERFCTR_PC_WRITE = 0x0C,
657 ARMV8_PMUV3_PERFCTR_PC_IMM_BRANCH = 0x0D,
658 ARMV8_PMUV3_PERFCTR_PC_PROC_RETURN = 0x0E,
659 ARMV8_PMUV3_PERFCTR_MEM_UNALIGNED_ACCESS = 0x0F,
660 ARMV8_PMUV3_PERFCTR_TTBR_WRITE = 0x1C,
662 /* Common microarchitectural events. */
663 ARMV8_PMUV3_PERFCTR_L1_ICACHE_REFILL = 0x01,
664 ARMV8_PMUV3_PERFCTR_ITLB_REFILL = 0x02,
665 ARMV8_PMUV3_PERFCTR_DTLB_REFILL = 0x05,
666 ARMV8_PMUV3_PERFCTR_MEM_ACCESS = 0x13,
667 ARMV8_PMUV3_PERFCTR_L1_ICACHE_ACCESS = 0x14,
668 ARMV8_PMUV3_PERFCTR_L1_DCACHE_WB = 0x15,
669 ARMV8_PMUV3_PERFCTR_L2_CACHE_ACCESS = 0x16,
670 ARMV8_PMUV3_PERFCTR_L2_CACHE_REFILL = 0x17,
671 ARMV8_PMUV3_PERFCTR_L2_CACHE_WB = 0x18,
672 ARMV8_PMUV3_PERFCTR_BUS_ACCESS = 0x19,
673 ARMV8_PMUV3_PERFCTR_MEM_ERROR = 0x1A,
674 ARMV8_PMUV3_PERFCTR_BUS_CYCLES = 0x1D,
677 /* PMUv3 HW events mapping. */
678 static const unsigned armv8_pmuv3_perf_map[PERF_COUNT_HW_MAX] = {
679 [PERF_COUNT_HW_CPU_CYCLES] = ARMV8_PMUV3_PERFCTR_CLOCK_CYCLES,
680 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV8_PMUV3_PERFCTR_INSTR_EXECUTED,
681 [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV8_PMUV3_PERFCTR_L1_DCACHE_ACCESS,
682 [PERF_COUNT_HW_CACHE_MISSES] = ARMV8_PMUV3_PERFCTR_L1_DCACHE_REFILL,
683 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = HW_OP_UNSUPPORTED,
684 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV8_PMUV3_PERFCTR_PC_BRANCH_MIS_PRED,
685 [PERF_COUNT_HW_BUS_CYCLES] = HW_OP_UNSUPPORTED,
686 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = HW_OP_UNSUPPORTED,
687 [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = HW_OP_UNSUPPORTED,
690 static const unsigned armv8_pmuv3_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
691 [PERF_COUNT_HW_CACHE_OP_MAX]
692 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
695 [C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1_DCACHE_ACCESS,
696 [C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1_DCACHE_REFILL,
699 [C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1_DCACHE_ACCESS,
700 [C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1_DCACHE_REFILL,
703 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
704 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
709 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
710 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
713 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
714 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
717 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
718 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
723 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
724 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
727 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
728 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
731 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
732 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
737 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
738 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
741 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
742 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
745 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
746 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
751 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
752 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
755 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
756 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
759 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
760 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
765 [C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_PC_BRANCH_PRED,
766 [C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_PC_BRANCH_MIS_PRED,
769 [C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_PC_BRANCH_PRED,
770 [C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_PC_BRANCH_MIS_PRED,
773 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
774 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
779 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
780 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
783 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
784 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
787 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
788 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
794 * Perf Events' indices
796 #define ARMV8_IDX_CYCLE_COUNTER 0
797 #define ARMV8_IDX_COUNTER0 1
798 #define ARMV8_IDX_COUNTER_LAST (ARMV8_IDX_CYCLE_COUNTER + cpu_pmu->num_events - 1)
800 #define ARMV8_MAX_COUNTERS 32
801 #define ARMV8_COUNTER_MASK (ARMV8_MAX_COUNTERS - 1)
804 * ARMv8 low level PMU access
808 * Perf Event to low level counters mapping
810 #define ARMV8_IDX_TO_COUNTER(x) \
811 (((x) - ARMV8_IDX_COUNTER0) & ARMV8_COUNTER_MASK)
814 * Per-CPU PMCR: config reg
816 #define ARMV8_PMCR_E (1 << 0) /* Enable all counters */
817 #define ARMV8_PMCR_P (1 << 1) /* Reset all counters */
818 #define ARMV8_PMCR_C (1 << 2) /* Cycle counter reset */
819 #define ARMV8_PMCR_D (1 << 3) /* CCNT counts every 64th cpu cycle */
820 #define ARMV8_PMCR_X (1 << 4) /* Export to ETM */
821 #define ARMV8_PMCR_DP (1 << 5) /* Disable CCNT if non-invasive debug*/
822 #define ARMV8_PMCR_N_SHIFT 11 /* Number of counters supported */
823 #define ARMV8_PMCR_N_MASK 0x1f
824 #define ARMV8_PMCR_MASK 0x3f /* Mask for writable bits */
827 * PMOVSR: counters overflow flag status reg
829 #define ARMV8_OVSR_MASK 0xffffffff /* Mask for writable bits */
830 #define ARMV8_OVERFLOWED_MASK ARMV8_OVSR_MASK
833 * PMXEVTYPER: Event selection reg
835 #define ARMV8_EVTYPE_MASK 0xc80000ff /* Mask for writable bits */
836 #define ARMV8_EVTYPE_EVENT 0xff /* Mask for EVENT bits */
839 * Event filters for PMUv3
841 #define ARMV8_EXCLUDE_EL1 (1 << 31)
842 #define ARMV8_EXCLUDE_EL0 (1 << 30)
843 #define ARMV8_INCLUDE_EL2 (1 << 27)
845 static inline u32 armv8pmu_pmcr_read(void)
848 asm volatile("mrs %0, pmcr_el0" : "=r" (val));
852 static inline void armv8pmu_pmcr_write(u32 val)
854 val &= ARMV8_PMCR_MASK;
856 asm volatile("msr pmcr_el0, %0" :: "r" (val));
859 static inline int armv8pmu_has_overflowed(u32 pmovsr)
861 return pmovsr & ARMV8_OVERFLOWED_MASK;
864 static inline int armv8pmu_counter_valid(int idx)
866 return idx >= ARMV8_IDX_CYCLE_COUNTER && idx <= ARMV8_IDX_COUNTER_LAST;
869 static inline int armv8pmu_counter_has_overflowed(u32 pmnc, int idx)
874 if (!armv8pmu_counter_valid(idx)) {
875 pr_err("CPU%u checking wrong counter %d overflow status\n",
876 smp_processor_id(), idx);
878 counter = ARMV8_IDX_TO_COUNTER(idx);
879 ret = pmnc & BIT(counter);
885 static inline int armv8pmu_select_counter(int idx)
889 if (!armv8pmu_counter_valid(idx)) {
890 pr_err("CPU%u selecting wrong PMNC counter %d\n",
891 smp_processor_id(), idx);
895 counter = ARMV8_IDX_TO_COUNTER(idx);
896 asm volatile("msr pmselr_el0, %0" :: "r" (counter));
902 static inline u32 armv8pmu_read_counter(int idx)
906 if (!armv8pmu_counter_valid(idx))
907 pr_err("CPU%u reading wrong counter %d\n",
908 smp_processor_id(), idx);
909 else if (idx == ARMV8_IDX_CYCLE_COUNTER)
910 asm volatile("mrs %0, pmccntr_el0" : "=r" (value));
911 else if (armv8pmu_select_counter(idx) == idx)
912 asm volatile("mrs %0, pmxevcntr_el0" : "=r" (value));
917 static inline void armv8pmu_write_counter(int idx, u32 value)
919 if (!armv8pmu_counter_valid(idx))
920 pr_err("CPU%u writing wrong counter %d\n",
921 smp_processor_id(), idx);
922 else if (idx == ARMV8_IDX_CYCLE_COUNTER)
923 asm volatile("msr pmccntr_el0, %0" :: "r" (value));
924 else if (armv8pmu_select_counter(idx) == idx)
925 asm volatile("msr pmxevcntr_el0, %0" :: "r" (value));
928 static inline void armv8pmu_write_evtype(int idx, u32 val)
930 if (armv8pmu_select_counter(idx) == idx) {
931 val &= ARMV8_EVTYPE_MASK;
932 asm volatile("msr pmxevtyper_el0, %0" :: "r" (val));
936 static inline int armv8pmu_enable_counter(int idx)
940 if (!armv8pmu_counter_valid(idx)) {
941 pr_err("CPU%u enabling wrong PMNC counter %d\n",
942 smp_processor_id(), idx);
946 counter = ARMV8_IDX_TO_COUNTER(idx);
947 asm volatile("msr pmcntenset_el0, %0" :: "r" (BIT(counter)));
951 static inline int armv8pmu_disable_counter(int idx)
955 if (!armv8pmu_counter_valid(idx)) {
956 pr_err("CPU%u disabling wrong PMNC counter %d\n",
957 smp_processor_id(), idx);
961 counter = ARMV8_IDX_TO_COUNTER(idx);
962 asm volatile("msr pmcntenclr_el0, %0" :: "r" (BIT(counter)));
966 static inline int armv8pmu_enable_intens(int idx)
970 if (!armv8pmu_counter_valid(idx)) {
971 pr_err("CPU%u enabling wrong PMNC counter IRQ enable %d\n",
972 smp_processor_id(), idx);
976 counter = ARMV8_IDX_TO_COUNTER(idx);
977 asm volatile("msr pmintenset_el1, %0" :: "r" (BIT(counter)));
981 static inline int armv8pmu_disable_intens(int idx)
985 if (!armv8pmu_counter_valid(idx)) {
986 pr_err("CPU%u disabling wrong PMNC counter IRQ enable %d\n",
987 smp_processor_id(), idx);
991 counter = ARMV8_IDX_TO_COUNTER(idx);
992 asm volatile("msr pmintenclr_el1, %0" :: "r" (BIT(counter)));
994 /* Clear the overflow flag in case an interrupt is pending. */
995 asm volatile("msr pmovsclr_el0, %0" :: "r" (BIT(counter)));
1000 static inline u32 armv8pmu_getreset_flags(void)
1005 asm volatile("mrs %0, pmovsclr_el0" : "=r" (value));
1007 /* Write to clear flags */
1008 value &= ARMV8_OVSR_MASK;
1009 asm volatile("msr pmovsclr_el0, %0" :: "r" (value));
1014 static void armv8pmu_enable_event(struct hw_perf_event *hwc, int idx)
1016 unsigned long flags;
1017 struct pmu_hw_events *events = cpu_pmu->get_hw_events();
1020 * Enable counter and interrupt, and set the counter to count
1021 * the event that we're interested in.
1023 raw_spin_lock_irqsave(&events->pmu_lock, flags);
1028 armv8pmu_disable_counter(idx);
1031 * Set event (if destined for PMNx counters).
1033 armv8pmu_write_evtype(idx, hwc->config_base);
1036 * Enable interrupt for this counter
1038 armv8pmu_enable_intens(idx);
1043 armv8pmu_enable_counter(idx);
1045 raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
1048 static void armv8pmu_disable_event(struct hw_perf_event *hwc, int idx)
1050 unsigned long flags;
1051 struct pmu_hw_events *events = cpu_pmu->get_hw_events();
1054 * Disable counter and interrupt
1056 raw_spin_lock_irqsave(&events->pmu_lock, flags);
1061 armv8pmu_disable_counter(idx);
1064 * Disable interrupt for this counter
1066 armv8pmu_disable_intens(idx);
1068 raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
1071 static irqreturn_t armv8pmu_handle_irq(int irq_num, void *dev)
1074 struct perf_sample_data data;
1075 struct pmu_hw_events *cpuc;
1076 struct pt_regs *regs;
1080 * Get and reset the IRQ flags
1082 pmovsr = armv8pmu_getreset_flags();
1085 * Did an overflow occur?
1087 if (!armv8pmu_has_overflowed(pmovsr))
1091 * Handle the counter(s) overflow(s)
1093 regs = get_irq_regs();
1095 cpuc = &__get_cpu_var(cpu_hw_events);
1096 for (idx = 0; idx < cpu_pmu->num_events; ++idx) {
1097 struct perf_event *event = cpuc->events[idx];
1098 struct hw_perf_event *hwc;
1100 /* Ignore if we don't have an event. */
1105 * We have a single interrupt for all counters. Check that
1106 * each counter has overflowed before we process it.
1108 if (!armv8pmu_counter_has_overflowed(pmovsr, idx))
1112 armpmu_event_update(event, hwc, idx);
1113 perf_sample_data_init(&data, 0, hwc->last_period);
1114 if (!armpmu_event_set_period(event, hwc, idx))
1117 if (perf_event_overflow(event, &data, regs))
1118 cpu_pmu->disable(hwc, idx);
1122 * Handle the pending perf events.
1124 * Note: this call *must* be run with interrupts disabled. For
1125 * platforms that can have the PMU interrupts raised as an NMI, this
1133 static void armv8pmu_start(void)
1135 unsigned long flags;
1136 struct pmu_hw_events *events = cpu_pmu->get_hw_events();
1138 raw_spin_lock_irqsave(&events->pmu_lock, flags);
1139 /* Enable all counters */
1140 armv8pmu_pmcr_write(armv8pmu_pmcr_read() | ARMV8_PMCR_E);
1141 raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
1144 static void armv8pmu_stop(void)
1146 unsigned long flags;
1147 struct pmu_hw_events *events = cpu_pmu->get_hw_events();
1149 raw_spin_lock_irqsave(&events->pmu_lock, flags);
1150 /* Disable all counters */
1151 armv8pmu_pmcr_write(armv8pmu_pmcr_read() & ~ARMV8_PMCR_E);
1152 raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
1155 static int armv8pmu_get_event_idx(struct pmu_hw_events *cpuc,
1156 struct hw_perf_event *event)
1159 unsigned long evtype = event->config_base & ARMV8_EVTYPE_EVENT;
1161 /* Always place a cycle counter into the cycle counter. */
1162 if (evtype == ARMV8_PMUV3_PERFCTR_CLOCK_CYCLES) {
1163 if (test_and_set_bit(ARMV8_IDX_CYCLE_COUNTER, cpuc->used_mask))
1166 return ARMV8_IDX_CYCLE_COUNTER;
1170 * For anything other than a cycle counter, try and use
1171 * the events counters
1173 for (idx = ARMV8_IDX_COUNTER0; idx < cpu_pmu->num_events; ++idx) {
1174 if (!test_and_set_bit(idx, cpuc->used_mask))
1178 /* The counters are all in use. */
1183 * Add an event filter to a given event. This will only work for PMUv2 PMUs.
1185 static int armv8pmu_set_event_filter(struct hw_perf_event *event,
1186 struct perf_event_attr *attr)
1188 unsigned long config_base = 0;
1190 if (attr->exclude_idle)
1192 if (attr->exclude_user)
1193 config_base |= ARMV8_EXCLUDE_EL0;
1194 if (attr->exclude_kernel)
1195 config_base |= ARMV8_EXCLUDE_EL1;
1196 if (!attr->exclude_hv)
1197 config_base |= ARMV8_INCLUDE_EL2;
1200 * Install the filter into config_base as this is used to
1201 * construct the event type.
1203 event->config_base = config_base;
1208 static void armv8pmu_reset(void *info)
1210 u32 idx, nb_cnt = cpu_pmu->num_events;
1212 /* The counter and interrupt enable registers are unknown at reset. */
1213 for (idx = ARMV8_IDX_CYCLE_COUNTER; idx < nb_cnt; ++idx)
1214 armv8pmu_disable_event(NULL, idx);
1216 /* Initialize & Reset PMNC: C and P bits. */
1217 armv8pmu_pmcr_write(ARMV8_PMCR_P | ARMV8_PMCR_C);
1219 /* Disable access from userspace. */
1220 asm volatile("msr pmuserenr_el0, %0" :: "r" (0));
1223 static int armv8_pmuv3_map_event(struct perf_event *event)
1225 return map_cpu_event(event, &armv8_pmuv3_perf_map,
1226 &armv8_pmuv3_perf_cache_map, 0xFF);
1229 static struct arm_pmu armv8pmu = {
1230 .handle_irq = armv8pmu_handle_irq,
1231 .enable = armv8pmu_enable_event,
1232 .disable = armv8pmu_disable_event,
1233 .read_counter = armv8pmu_read_counter,
1234 .write_counter = armv8pmu_write_counter,
1235 .get_event_idx = armv8pmu_get_event_idx,
1236 .start = armv8pmu_start,
1237 .stop = armv8pmu_stop,
1238 .reset = armv8pmu_reset,
1239 .max_period = (1LLU << 32) - 1,
1242 static u32 __init armv8pmu_read_num_pmnc_events(void)
1246 /* Read the nb of CNTx counters supported from PMNC */
1247 nb_cnt = (armv8pmu_pmcr_read() >> ARMV8_PMCR_N_SHIFT) & ARMV8_PMCR_N_MASK;
1249 /* Add the CPU cycles counter and return */
1253 static struct arm_pmu *__init armv8_pmuv3_pmu_init(void)
1255 armv8pmu.name = "arm/armv8-pmuv3";
1256 armv8pmu.map_event = armv8_pmuv3_map_event;
1257 armv8pmu.num_events = armv8pmu_read_num_pmnc_events();
1258 armv8pmu.set_event_filter = armv8pmu_set_event_filter;
1263 * Ensure the PMU has sane values out of reset.
1264 * This requires SMP to be available, so exists as a separate initcall.
1269 if (cpu_pmu && cpu_pmu->reset)
1270 return on_each_cpu(cpu_pmu->reset, NULL, 1);
1273 arch_initcall(cpu_pmu_reset);
1276 * PMU platform driver and devicetree bindings.
1278 static struct of_device_id armpmu_of_device_ids[] = {
1279 {.compatible = "arm,armv8-pmuv3"},
1283 static int armpmu_device_probe(struct platform_device *pdev)
1288 cpu_pmu->plat_device = pdev;
1292 static struct platform_driver armpmu_driver = {
1295 .of_match_table = armpmu_of_device_ids,
1297 .probe = armpmu_device_probe,
1300 static int __init register_pmu_driver(void)
1302 return platform_driver_register(&armpmu_driver);
1304 device_initcall(register_pmu_driver);
1306 static struct pmu_hw_events *armpmu_get_cpu_events(void)
1308 return &__get_cpu_var(cpu_hw_events);
1311 static void __init cpu_pmu_init(struct arm_pmu *armpmu)
1314 for_each_possible_cpu(cpu) {
1315 struct pmu_hw_events *events = &per_cpu(cpu_hw_events, cpu);
1316 events->events = per_cpu(hw_events, cpu);
1317 events->used_mask = per_cpu(used_mask, cpu);
1318 raw_spin_lock_init(&events->pmu_lock);
1320 armpmu->get_hw_events = armpmu_get_cpu_events;
1323 static int __init init_hw_perf_events(void)
1325 u64 dfr = read_cpuid(ID_AA64DFR0_EL1);
1327 switch ((dfr >> 8) & 0xf) {
1328 case 0x1: /* PMUv3 */
1329 cpu_pmu = armv8_pmuv3_pmu_init();
1334 pr_info("enabled with %s PMU driver, %d counters available\n",
1335 cpu_pmu->name, cpu_pmu->num_events);
1336 cpu_pmu_init(cpu_pmu);
1337 armpmu_register(cpu_pmu, "cpu", PERF_TYPE_RAW);
1339 pr_info("no hardware support available\n");
1344 early_initcall(init_hw_perf_events);
1347 * Callchain handling code.
1350 struct frame_tail __user *fp;
1352 } __attribute__((packed));
1355 * Get the return address for a single stackframe and return a pointer to the
1358 static struct frame_tail __user *
1359 user_backtrace(struct frame_tail __user *tail,
1360 struct perf_callchain_entry *entry)
1362 struct frame_tail buftail;
1365 /* Also check accessibility of one struct frame_tail beyond */
1366 if (!access_ok(VERIFY_READ, tail, sizeof(buftail)))
1369 pagefault_disable();
1370 err = __copy_from_user_inatomic(&buftail, tail, sizeof(buftail));
1376 perf_callchain_store(entry, buftail.lr);
1379 * Frame pointers should strictly progress back up the stack
1380 * (towards higher addresses).
1382 if (tail >= buftail.fp)
1388 #ifdef CONFIG_COMPAT
1390 * The registers we're interested in are at the end of the variable
1391 * length saved register structure. The fp points at the end of this
1392 * structure so the address of this struct is:
1393 * (struct compat_frame_tail *)(xxx->fp)-1
1395 * This code has been adapted from the ARM OProfile support.
1397 struct compat_frame_tail {
1398 compat_uptr_t fp; /* a (struct compat_frame_tail *) in compat mode */
1401 } __attribute__((packed));
1403 static struct compat_frame_tail __user *
1404 compat_user_backtrace(struct compat_frame_tail __user *tail,
1405 struct perf_callchain_entry *entry)
1407 struct compat_frame_tail buftail;
1410 /* Also check accessibility of one struct frame_tail beyond */
1411 if (!access_ok(VERIFY_READ, tail, sizeof(buftail)))
1414 pagefault_disable();
1415 err = __copy_from_user_inatomic(&buftail, tail, sizeof(buftail));
1421 perf_callchain_store(entry, buftail.lr);
1424 * Frame pointers should strictly progress back up the stack
1425 * (towards higher addresses).
1427 if (tail + 1 >= (struct compat_frame_tail __user *)
1428 compat_ptr(buftail.fp))
1431 return (struct compat_frame_tail __user *)compat_ptr(buftail.fp) - 1;
1433 #endif /* CONFIG_COMPAT */
1435 void perf_callchain_user(struct perf_callchain_entry *entry,
1436 struct pt_regs *regs)
1438 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1439 /* We don't support guest os callchain now */
1443 perf_callchain_store(entry, regs->pc);
1445 if (!compat_user_mode(regs)) {
1447 struct frame_tail __user *tail;
1449 tail = (struct frame_tail __user *)regs->regs[29];
1451 while (entry->nr < PERF_MAX_STACK_DEPTH &&
1452 tail && !((unsigned long)tail & 0xf))
1453 tail = user_backtrace(tail, entry);
1455 #ifdef CONFIG_COMPAT
1456 /* AARCH32 compat mode */
1457 struct compat_frame_tail __user *tail;
1459 tail = (struct compat_frame_tail __user *)regs->compat_fp - 1;
1461 while ((entry->nr < PERF_MAX_STACK_DEPTH) &&
1462 tail && !((unsigned long)tail & 0x3))
1463 tail = compat_user_backtrace(tail, entry);
1469 * Gets called by walk_stackframe() for every stackframe. This will be called
1470 * whist unwinding the stackframe and is like a subroutine return so we use
1473 static int callchain_trace(struct stackframe *frame, void *data)
1475 struct perf_callchain_entry *entry = data;
1476 perf_callchain_store(entry, frame->pc);
1480 void perf_callchain_kernel(struct perf_callchain_entry *entry,
1481 struct pt_regs *regs)
1483 struct stackframe frame;
1485 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1486 /* We don't support guest os callchain now */
1490 frame.fp = regs->regs[29];
1491 frame.sp = regs->sp;
1492 frame.pc = regs->pc;
1494 walk_stackframe(&frame, callchain_trace, entry);
1497 unsigned long perf_instruction_pointer(struct pt_regs *regs)
1499 if (perf_guest_cbs && perf_guest_cbs->is_in_guest())
1500 return perf_guest_cbs->get_guest_ip();
1502 return instruction_pointer(regs);
1505 unsigned long perf_misc_flags(struct pt_regs *regs)
1509 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1510 if (perf_guest_cbs->is_user_mode())
1511 misc |= PERF_RECORD_MISC_GUEST_USER;
1513 misc |= PERF_RECORD_MISC_GUEST_KERNEL;
1515 if (user_mode(regs))
1516 misc |= PERF_RECORD_MISC_USER;
1518 misc |= PERF_RECORD_MISC_KERNEL;