2 * AArch64 loadable module support.
4 * Copyright (C) 2012 ARM Limited
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 * Author: Will Deacon <will.deacon@arm.com>
21 #include <linux/bitops.h>
22 #include <linux/elf.h>
23 #include <linux/gfp.h>
24 #include <linux/kasan.h>
25 #include <linux/kernel.h>
27 #include <linux/moduleloader.h>
28 #include <linux/vmalloc.h>
29 #include <asm/alternative.h>
31 #include <asm/sections.h>
33 void *module_alloc(unsigned long size)
37 p = __vmalloc_node_range(size, MODULE_ALIGN, MODULES_VADDR, MODULES_END,
38 GFP_KERNEL, PAGE_KERNEL_EXEC, 0,
39 NUMA_NO_NODE, __builtin_return_address(0));
41 if (p && (kasan_module_alloc(p, size) < 0)) {
49 enum aarch64_reloc_op {
56 static u64 do_reloc(enum aarch64_reloc_op reloc_op, void *place, u64 val)
62 return val - (u64)place;
64 return (val & ~0xfff) - ((u64)place & ~0xfff);
69 pr_err("do_reloc: unknown relocation operation %d\n", reloc_op);
73 static int reloc_data(enum aarch64_reloc_op op, void *place, u64 val, int len)
75 u64 imm_mask = (1 << len) - 1;
76 s64 sval = do_reloc(op, place, val);
89 pr_err("Invalid length (%d) for data relocation\n", len);
94 * Extract the upper value bits (including the sign bit) and
95 * shift them to bit 0.
97 sval = (s64)(sval & ~(imm_mask >> 1)) >> (len - 1);
100 * Overflow has occurred if the value is not representable in
101 * len bits (i.e the bottom len bits are not sign-extended and
102 * the top bits are not all zero).
104 if ((u64)(sval + 1) > 2)
110 enum aarch64_insn_movw_imm_type {
111 AARCH64_INSN_IMM_MOVNZ,
112 AARCH64_INSN_IMM_MOVKZ,
115 static int reloc_insn_movw(enum aarch64_reloc_op op, void *place, u64 val,
116 int lsb, enum aarch64_insn_movw_imm_type imm_type)
120 u32 insn = le32_to_cpu(*(u32 *)place);
122 sval = do_reloc(op, place, val);
125 if (imm_type == AARCH64_INSN_IMM_MOVNZ) {
127 * For signed MOVW relocations, we have to manipulate the
128 * instruction encoding depending on whether or not the
129 * immediate is less than zero.
133 /* >=0: Set the instruction to MOVZ (opcode 10b). */
137 * <0: Set the instruction to MOVN (opcode 00b).
138 * Since we've masked the opcode already, we
139 * don't need to do anything other than
140 * inverting the new immediate field.
146 /* Update the instruction with the new encoding. */
147 insn = aarch64_insn_encode_immediate(AARCH64_INSN_IMM_16, insn, imm);
148 *(u32 *)place = cpu_to_le32(insn);
156 static int reloc_insn_imm(enum aarch64_reloc_op op, void *place, u64 val,
157 int lsb, int len, enum aarch64_insn_imm_type imm_type)
161 u32 insn = le32_to_cpu(*(u32 *)place);
163 /* Calculate the relocation value. */
164 sval = do_reloc(op, place, val);
167 /* Extract the value bits and shift them to bit 0. */
168 imm_mask = (BIT(lsb + len) - 1) >> lsb;
169 imm = sval & imm_mask;
171 /* Update the instruction's immediate field. */
172 insn = aarch64_insn_encode_immediate(imm_type, insn, imm);
173 *(u32 *)place = cpu_to_le32(insn);
176 * Extract the upper value bits (including the sign bit) and
177 * shift them to bit 0.
179 sval = (s64)(sval & ~(imm_mask >> 1)) >> (len - 1);
182 * Overflow has occurred if the upper bits are not all equal to
183 * the sign bit of the value.
185 if ((u64)(sval + 1) >= 2)
191 int apply_relocate_add(Elf64_Shdr *sechdrs,
193 unsigned int symindex,
203 Elf64_Rela *rel = (void *)sechdrs[relsec].sh_addr;
205 for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) {
206 /* loc corresponds to P in the AArch64 ELF document. */
207 loc = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr
210 /* sym is the ELF symbol we're referring to. */
211 sym = (Elf64_Sym *)sechdrs[symindex].sh_addr
212 + ELF64_R_SYM(rel[i].r_info);
214 /* val corresponds to (S + A) in the AArch64 ELF document. */
215 val = sym->st_value + rel[i].r_addend;
217 /* Check for overflow by default. */
218 overflow_check = true;
220 /* Perform the static relocation. */
221 switch (ELF64_R_TYPE(rel[i].r_info)) {
222 /* Null relocations. */
228 /* Data relocations. */
229 case R_AARCH64_ABS64:
230 overflow_check = false;
231 ovf = reloc_data(RELOC_OP_ABS, loc, val, 64);
233 case R_AARCH64_ABS32:
234 ovf = reloc_data(RELOC_OP_ABS, loc, val, 32);
236 case R_AARCH64_ABS16:
237 ovf = reloc_data(RELOC_OP_ABS, loc, val, 16);
239 case R_AARCH64_PREL64:
240 overflow_check = false;
241 ovf = reloc_data(RELOC_OP_PREL, loc, val, 64);
243 case R_AARCH64_PREL32:
244 ovf = reloc_data(RELOC_OP_PREL, loc, val, 32);
246 case R_AARCH64_PREL16:
247 ovf = reloc_data(RELOC_OP_PREL, loc, val, 16);
250 /* MOVW instruction relocations. */
251 case R_AARCH64_MOVW_UABS_G0_NC:
252 overflow_check = false;
253 case R_AARCH64_MOVW_UABS_G0:
254 ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 0,
255 AARCH64_INSN_IMM_MOVKZ);
257 case R_AARCH64_MOVW_UABS_G1_NC:
258 overflow_check = false;
259 case R_AARCH64_MOVW_UABS_G1:
260 ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 16,
261 AARCH64_INSN_IMM_MOVKZ);
263 case R_AARCH64_MOVW_UABS_G2_NC:
264 overflow_check = false;
265 case R_AARCH64_MOVW_UABS_G2:
266 ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 32,
267 AARCH64_INSN_IMM_MOVKZ);
269 case R_AARCH64_MOVW_UABS_G3:
270 /* We're using the top bits so we can't overflow. */
271 overflow_check = false;
272 ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 48,
273 AARCH64_INSN_IMM_MOVKZ);
275 case R_AARCH64_MOVW_SABS_G0:
276 ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 0,
277 AARCH64_INSN_IMM_MOVNZ);
279 case R_AARCH64_MOVW_SABS_G1:
280 ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 16,
281 AARCH64_INSN_IMM_MOVNZ);
283 case R_AARCH64_MOVW_SABS_G2:
284 ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 32,
285 AARCH64_INSN_IMM_MOVNZ);
287 case R_AARCH64_MOVW_PREL_G0_NC:
288 overflow_check = false;
289 ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 0,
290 AARCH64_INSN_IMM_MOVKZ);
292 case R_AARCH64_MOVW_PREL_G0:
293 ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 0,
294 AARCH64_INSN_IMM_MOVNZ);
296 case R_AARCH64_MOVW_PREL_G1_NC:
297 overflow_check = false;
298 ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 16,
299 AARCH64_INSN_IMM_MOVKZ);
301 case R_AARCH64_MOVW_PREL_G1:
302 ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 16,
303 AARCH64_INSN_IMM_MOVNZ);
305 case R_AARCH64_MOVW_PREL_G2_NC:
306 overflow_check = false;
307 ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 32,
308 AARCH64_INSN_IMM_MOVKZ);
310 case R_AARCH64_MOVW_PREL_G2:
311 ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 32,
312 AARCH64_INSN_IMM_MOVNZ);
314 case R_AARCH64_MOVW_PREL_G3:
315 /* We're using the top bits so we can't overflow. */
316 overflow_check = false;
317 ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 48,
318 AARCH64_INSN_IMM_MOVNZ);
321 /* Immediate instruction relocations. */
322 case R_AARCH64_LD_PREL_LO19:
323 ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 19,
324 AARCH64_INSN_IMM_19);
326 case R_AARCH64_ADR_PREL_LO21:
327 ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 0, 21,
328 AARCH64_INSN_IMM_ADR);
330 #ifndef CONFIG_ARM64_ERRATUM_843419
331 case R_AARCH64_ADR_PREL_PG_HI21_NC:
332 overflow_check = false;
333 case R_AARCH64_ADR_PREL_PG_HI21:
334 ovf = reloc_insn_imm(RELOC_OP_PAGE, loc, val, 12, 21,
335 AARCH64_INSN_IMM_ADR);
338 case R_AARCH64_ADD_ABS_LO12_NC:
339 case R_AARCH64_LDST8_ABS_LO12_NC:
340 overflow_check = false;
341 ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 0, 12,
342 AARCH64_INSN_IMM_12);
344 case R_AARCH64_LDST16_ABS_LO12_NC:
345 overflow_check = false;
346 ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 1, 11,
347 AARCH64_INSN_IMM_12);
349 case R_AARCH64_LDST32_ABS_LO12_NC:
350 overflow_check = false;
351 ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 2, 10,
352 AARCH64_INSN_IMM_12);
354 case R_AARCH64_LDST64_ABS_LO12_NC:
355 overflow_check = false;
356 ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 3, 9,
357 AARCH64_INSN_IMM_12);
359 case R_AARCH64_LDST128_ABS_LO12_NC:
360 overflow_check = false;
361 ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 4, 8,
362 AARCH64_INSN_IMM_12);
364 case R_AARCH64_TSTBR14:
365 ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 14,
366 AARCH64_INSN_IMM_14);
368 case R_AARCH64_CONDBR19:
369 ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 19,
370 AARCH64_INSN_IMM_19);
372 case R_AARCH64_JUMP26:
373 case R_AARCH64_CALL26:
374 ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 26,
375 AARCH64_INSN_IMM_26);
379 pr_err("module %s: unsupported RELA relocation: %llu\n",
380 me->name, ELF64_R_TYPE(rel[i].r_info));
384 if (overflow_check && ovf == -ERANGE)
392 pr_err("module %s: overflow in relocation type %d val %Lx\n",
393 me->name, (int)ELF64_R_TYPE(rel[i].r_info), val);
397 int module_finalize(const Elf_Ehdr *hdr,
398 const Elf_Shdr *sechdrs,
401 const Elf_Shdr *s, *se;
402 const char *secstrs = (void *)hdr + sechdrs[hdr->e_shstrndx].sh_offset;
404 for (s = sechdrs, se = sechdrs + hdr->e_shnum; s < se; s++) {
405 if (strcmp(".altinstructions", secstrs + s->sh_name) == 0) {
406 apply_alternatives((void *)s->sh_addr, s->sh_size);