2 * Copyright (C) 2013 Huawei Ltd.
3 * Author: Jiang Liu <liuj97@gmail.com>
5 * Copyright (C) 2014 Zi Shen Lim <zlim.lnx@gmail.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 #include <linux/bitops.h>
20 #include <linux/compiler.h>
21 #include <linux/kernel.h>
22 #include <linux/smp.h>
23 #include <linux/stop_machine.h>
24 #include <linux/uaccess.h>
26 #include <asm/cacheflush.h>
27 #include <asm/debug-monitors.h>
30 #define AARCH64_INSN_SF_BIT BIT(31)
31 #define AARCH64_INSN_N_BIT BIT(22)
33 static int aarch64_insn_encoding_class[] = {
34 AARCH64_INSN_CLS_UNKNOWN,
35 AARCH64_INSN_CLS_UNKNOWN,
36 AARCH64_INSN_CLS_UNKNOWN,
37 AARCH64_INSN_CLS_UNKNOWN,
38 AARCH64_INSN_CLS_LDST,
39 AARCH64_INSN_CLS_DP_REG,
40 AARCH64_INSN_CLS_LDST,
41 AARCH64_INSN_CLS_DP_FPSIMD,
42 AARCH64_INSN_CLS_DP_IMM,
43 AARCH64_INSN_CLS_DP_IMM,
44 AARCH64_INSN_CLS_BR_SYS,
45 AARCH64_INSN_CLS_BR_SYS,
46 AARCH64_INSN_CLS_LDST,
47 AARCH64_INSN_CLS_DP_REG,
48 AARCH64_INSN_CLS_LDST,
49 AARCH64_INSN_CLS_DP_FPSIMD,
52 enum aarch64_insn_encoding_class __kprobes aarch64_get_insn_class(u32 insn)
54 return aarch64_insn_encoding_class[(insn >> 25) & 0xf];
57 /* NOP is an alias of HINT */
58 bool __kprobes aarch64_insn_is_nop(u32 insn)
60 if (!aarch64_insn_is_hint(insn))
63 switch (insn & 0xFE0) {
64 case AARCH64_INSN_HINT_YIELD:
65 case AARCH64_INSN_HINT_WFE:
66 case AARCH64_INSN_HINT_WFI:
67 case AARCH64_INSN_HINT_SEV:
68 case AARCH64_INSN_HINT_SEVL:
76 * In ARMv8-A, A64 instructions have a fixed length of 32 bits and are always
79 int __kprobes aarch64_insn_read(void *addr, u32 *insnp)
84 ret = probe_kernel_read(&val, addr, AARCH64_INSN_SIZE);
86 *insnp = le32_to_cpu(val);
91 int __kprobes aarch64_insn_write(void *addr, u32 insn)
93 insn = cpu_to_le32(insn);
94 return probe_kernel_write(addr, &insn, AARCH64_INSN_SIZE);
97 static bool __kprobes __aarch64_insn_hotpatch_safe(u32 insn)
99 if (aarch64_get_insn_class(insn) != AARCH64_INSN_CLS_BR_SYS)
102 return aarch64_insn_is_b(insn) ||
103 aarch64_insn_is_bl(insn) ||
104 aarch64_insn_is_svc(insn) ||
105 aarch64_insn_is_hvc(insn) ||
106 aarch64_insn_is_smc(insn) ||
107 aarch64_insn_is_brk(insn) ||
108 aarch64_insn_is_nop(insn);
112 * ARM Architecture Reference Manual for ARMv8 Profile-A, Issue A.a
113 * Section B2.6.5 "Concurrent modification and execution of instructions":
114 * Concurrent modification and execution of instructions can lead to the
115 * resulting instruction performing any behavior that can be achieved by
116 * executing any sequence of instructions that can be executed from the
117 * same Exception level, except where the instruction before modification
118 * and the instruction after modification is a B, BL, NOP, BKPT, SVC, HVC,
119 * or SMC instruction.
121 bool __kprobes aarch64_insn_hotpatch_safe(u32 old_insn, u32 new_insn)
123 return __aarch64_insn_hotpatch_safe(old_insn) &&
124 __aarch64_insn_hotpatch_safe(new_insn);
127 int __kprobes aarch64_insn_patch_text_nosync(void *addr, u32 insn)
132 /* A64 instructions must be word aligned */
133 if ((uintptr_t)tp & 0x3)
136 ret = aarch64_insn_write(tp, insn);
138 flush_icache_range((uintptr_t)tp,
139 (uintptr_t)tp + AARCH64_INSN_SIZE);
144 struct aarch64_insn_patch {
151 static int __kprobes aarch64_insn_patch_text_cb(void *arg)
154 struct aarch64_insn_patch *pp = arg;
156 /* The first CPU becomes master */
157 if (atomic_inc_return(&pp->cpu_count) == 1) {
158 for (i = 0; ret == 0 && i < pp->insn_cnt; i++)
159 ret = aarch64_insn_patch_text_nosync(pp->text_addrs[i],
162 * aarch64_insn_patch_text_nosync() calls flush_icache_range(),
163 * which ends with "dsb; isb" pair guaranteeing global
166 atomic_set(&pp->cpu_count, -1);
168 while (atomic_read(&pp->cpu_count) != -1)
176 int __kprobes aarch64_insn_patch_text_sync(void *addrs[], u32 insns[], int cnt)
178 struct aarch64_insn_patch patch = {
182 .cpu_count = ATOMIC_INIT(0),
188 return stop_machine(aarch64_insn_patch_text_cb, &patch,
192 int __kprobes aarch64_insn_patch_text(void *addrs[], u32 insns[], int cnt)
197 /* Unsafe to patch multiple instructions without synchronizaiton */
199 ret = aarch64_insn_read(addrs[0], &insn);
203 if (aarch64_insn_hotpatch_safe(insn, insns[0])) {
205 * ARMv8 architecture doesn't guarantee all CPUs see
206 * the new instruction after returning from function
207 * aarch64_insn_patch_text_nosync(). So send IPIs to
208 * all other CPUs to achieve instruction
211 ret = aarch64_insn_patch_text_nosync(addrs[0], insns[0]);
212 kick_all_cpus_sync();
217 return aarch64_insn_patch_text_sync(addrs, insns, cnt);
220 u32 __kprobes aarch64_insn_encode_immediate(enum aarch64_insn_imm_type type,
223 u32 immlo, immhi, lomask, himask, mask;
227 case AARCH64_INSN_IMM_ADR:
230 immlo = imm & lomask;
232 immhi = imm & himask;
233 imm = (immlo << 24) | (immhi);
234 mask = (lomask << 24) | (himask);
237 case AARCH64_INSN_IMM_26:
241 case AARCH64_INSN_IMM_19:
245 case AARCH64_INSN_IMM_16:
249 case AARCH64_INSN_IMM_14:
253 case AARCH64_INSN_IMM_12:
257 case AARCH64_INSN_IMM_9:
261 case AARCH64_INSN_IMM_7:
265 case AARCH64_INSN_IMM_6:
266 case AARCH64_INSN_IMM_S:
270 case AARCH64_INSN_IMM_R:
275 pr_err("aarch64_insn_encode_immediate: unknown immediate encoding %d\n",
280 /* Update the immediate field. */
281 insn &= ~(mask << shift);
282 insn |= (imm & mask) << shift;
287 static u32 aarch64_insn_encode_register(enum aarch64_insn_register_type type,
289 enum aarch64_insn_register reg)
293 if (reg < AARCH64_INSN_REG_0 || reg > AARCH64_INSN_REG_SP) {
294 pr_err("%s: unknown register encoding %d\n", __func__, reg);
299 case AARCH64_INSN_REGTYPE_RT:
300 case AARCH64_INSN_REGTYPE_RD:
303 case AARCH64_INSN_REGTYPE_RN:
306 case AARCH64_INSN_REGTYPE_RT2:
307 case AARCH64_INSN_REGTYPE_RA:
310 case AARCH64_INSN_REGTYPE_RM:
314 pr_err("%s: unknown register type encoding %d\n", __func__,
319 insn &= ~(GENMASK(4, 0) << shift);
320 insn |= reg << shift;
325 static u32 aarch64_insn_encode_ldst_size(enum aarch64_insn_size_type type,
331 case AARCH64_INSN_SIZE_8:
334 case AARCH64_INSN_SIZE_16:
337 case AARCH64_INSN_SIZE_32:
340 case AARCH64_INSN_SIZE_64:
344 pr_err("%s: unknown size encoding %d\n", __func__, type);
348 insn &= ~GENMASK(31, 30);
354 static inline long branch_imm_common(unsigned long pc, unsigned long addr,
360 * PC: A 64-bit Program Counter holding the address of the current
361 * instruction. A64 instructions must be word-aligned.
363 BUG_ON((pc & 0x3) || (addr & 0x3));
365 offset = ((long)addr - (long)pc);
366 BUG_ON(offset < -range || offset >= range);
371 u32 __kprobes aarch64_insn_gen_branch_imm(unsigned long pc, unsigned long addr,
372 enum aarch64_insn_branch_type type)
378 * B/BL support [-128M, 128M) offset
379 * ARM64 virtual address arrangement guarantees all kernel and module
380 * texts are within +/-128M.
382 offset = branch_imm_common(pc, addr, SZ_128M);
385 case AARCH64_INSN_BRANCH_LINK:
386 insn = aarch64_insn_get_bl_value();
388 case AARCH64_INSN_BRANCH_NOLINK:
389 insn = aarch64_insn_get_b_value();
393 return AARCH64_BREAK_FAULT;
396 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_26, insn,
400 u32 aarch64_insn_gen_comp_branch_imm(unsigned long pc, unsigned long addr,
401 enum aarch64_insn_register reg,
402 enum aarch64_insn_variant variant,
403 enum aarch64_insn_branch_type type)
408 offset = branch_imm_common(pc, addr, SZ_1M);
411 case AARCH64_INSN_BRANCH_COMP_ZERO:
412 insn = aarch64_insn_get_cbz_value();
414 case AARCH64_INSN_BRANCH_COMP_NONZERO:
415 insn = aarch64_insn_get_cbnz_value();
419 return AARCH64_BREAK_FAULT;
423 case AARCH64_INSN_VARIANT_32BIT:
425 case AARCH64_INSN_VARIANT_64BIT:
426 insn |= AARCH64_INSN_SF_BIT;
430 return AARCH64_BREAK_FAULT;
433 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT, insn, reg);
435 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_19, insn,
439 u32 aarch64_insn_gen_cond_branch_imm(unsigned long pc, unsigned long addr,
440 enum aarch64_insn_condition cond)
445 offset = branch_imm_common(pc, addr, SZ_1M);
447 insn = aarch64_insn_get_bcond_value();
449 BUG_ON(cond < AARCH64_INSN_COND_EQ || cond > AARCH64_INSN_COND_AL);
452 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_19, insn,
456 u32 __kprobes aarch64_insn_gen_hint(enum aarch64_insn_hint_op op)
458 return aarch64_insn_get_hint_value() | op;
461 u32 __kprobes aarch64_insn_gen_nop(void)
463 return aarch64_insn_gen_hint(AARCH64_INSN_HINT_NOP);
466 u32 aarch64_insn_gen_branch_reg(enum aarch64_insn_register reg,
467 enum aarch64_insn_branch_type type)
472 case AARCH64_INSN_BRANCH_NOLINK:
473 insn = aarch64_insn_get_br_value();
475 case AARCH64_INSN_BRANCH_LINK:
476 insn = aarch64_insn_get_blr_value();
478 case AARCH64_INSN_BRANCH_RETURN:
479 insn = aarch64_insn_get_ret_value();
483 return AARCH64_BREAK_FAULT;
486 return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, reg);
489 u32 aarch64_insn_gen_load_store_reg(enum aarch64_insn_register reg,
490 enum aarch64_insn_register base,
491 enum aarch64_insn_register offset,
492 enum aarch64_insn_size_type size,
493 enum aarch64_insn_ldst_type type)
498 case AARCH64_INSN_LDST_LOAD_REG_OFFSET:
499 insn = aarch64_insn_get_ldr_reg_value();
501 case AARCH64_INSN_LDST_STORE_REG_OFFSET:
502 insn = aarch64_insn_get_str_reg_value();
506 return AARCH64_BREAK_FAULT;
509 insn = aarch64_insn_encode_ldst_size(size, insn);
511 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT, insn, reg);
513 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn,
516 return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM, insn,
520 u32 aarch64_insn_gen_load_store_pair(enum aarch64_insn_register reg1,
521 enum aarch64_insn_register reg2,
522 enum aarch64_insn_register base,
524 enum aarch64_insn_variant variant,
525 enum aarch64_insn_ldst_type type)
531 case AARCH64_INSN_LDST_LOAD_PAIR_PRE_INDEX:
532 insn = aarch64_insn_get_ldp_pre_value();
534 case AARCH64_INSN_LDST_STORE_PAIR_PRE_INDEX:
535 insn = aarch64_insn_get_stp_pre_value();
537 case AARCH64_INSN_LDST_LOAD_PAIR_POST_INDEX:
538 insn = aarch64_insn_get_ldp_post_value();
540 case AARCH64_INSN_LDST_STORE_PAIR_POST_INDEX:
541 insn = aarch64_insn_get_stp_post_value();
545 return AARCH64_BREAK_FAULT;
549 case AARCH64_INSN_VARIANT_32BIT:
550 /* offset must be multiples of 4 in the range [-256, 252] */
551 BUG_ON(offset & 0x3);
552 BUG_ON(offset < -256 || offset > 252);
555 case AARCH64_INSN_VARIANT_64BIT:
556 /* offset must be multiples of 8 in the range [-512, 504] */
557 BUG_ON(offset & 0x7);
558 BUG_ON(offset < -512 || offset > 504);
560 insn |= AARCH64_INSN_SF_BIT;
564 return AARCH64_BREAK_FAULT;
567 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT, insn,
570 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT2, insn,
573 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn,
576 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_7, insn,
580 u32 aarch64_insn_gen_add_sub_imm(enum aarch64_insn_register dst,
581 enum aarch64_insn_register src,
582 int imm, enum aarch64_insn_variant variant,
583 enum aarch64_insn_adsb_type type)
588 case AARCH64_INSN_ADSB_ADD:
589 insn = aarch64_insn_get_add_imm_value();
591 case AARCH64_INSN_ADSB_SUB:
592 insn = aarch64_insn_get_sub_imm_value();
594 case AARCH64_INSN_ADSB_ADD_SETFLAGS:
595 insn = aarch64_insn_get_adds_imm_value();
597 case AARCH64_INSN_ADSB_SUB_SETFLAGS:
598 insn = aarch64_insn_get_subs_imm_value();
602 return AARCH64_BREAK_FAULT;
606 case AARCH64_INSN_VARIANT_32BIT:
608 case AARCH64_INSN_VARIANT_64BIT:
609 insn |= AARCH64_INSN_SF_BIT;
613 return AARCH64_BREAK_FAULT;
616 BUG_ON(imm & ~(SZ_4K - 1));
618 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
620 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, src);
622 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_12, insn, imm);
625 u32 aarch64_insn_gen_bitfield(enum aarch64_insn_register dst,
626 enum aarch64_insn_register src,
628 enum aarch64_insn_variant variant,
629 enum aarch64_insn_bitfield_type type)
635 case AARCH64_INSN_BITFIELD_MOVE:
636 insn = aarch64_insn_get_bfm_value();
638 case AARCH64_INSN_BITFIELD_MOVE_UNSIGNED:
639 insn = aarch64_insn_get_ubfm_value();
641 case AARCH64_INSN_BITFIELD_MOVE_SIGNED:
642 insn = aarch64_insn_get_sbfm_value();
646 return AARCH64_BREAK_FAULT;
650 case AARCH64_INSN_VARIANT_32BIT:
651 mask = GENMASK(4, 0);
653 case AARCH64_INSN_VARIANT_64BIT:
654 insn |= AARCH64_INSN_SF_BIT | AARCH64_INSN_N_BIT;
655 mask = GENMASK(5, 0);
659 return AARCH64_BREAK_FAULT;
662 BUG_ON(immr & ~mask);
663 BUG_ON(imms & ~mask);
665 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
667 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, src);
669 insn = aarch64_insn_encode_immediate(AARCH64_INSN_IMM_R, insn, immr);
671 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_S, insn, imms);
674 u32 aarch64_insn_gen_movewide(enum aarch64_insn_register dst,
676 enum aarch64_insn_variant variant,
677 enum aarch64_insn_movewide_type type)
682 case AARCH64_INSN_MOVEWIDE_ZERO:
683 insn = aarch64_insn_get_movz_value();
685 case AARCH64_INSN_MOVEWIDE_KEEP:
686 insn = aarch64_insn_get_movk_value();
688 case AARCH64_INSN_MOVEWIDE_INVERSE:
689 insn = aarch64_insn_get_movn_value();
693 return AARCH64_BREAK_FAULT;
696 BUG_ON(imm & ~(SZ_64K - 1));
699 case AARCH64_INSN_VARIANT_32BIT:
700 BUG_ON(shift != 0 && shift != 16);
702 case AARCH64_INSN_VARIANT_64BIT:
703 insn |= AARCH64_INSN_SF_BIT;
704 BUG_ON(shift != 0 && shift != 16 && shift != 32 &&
709 return AARCH64_BREAK_FAULT;
712 insn |= (shift >> 4) << 21;
714 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
716 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_16, insn, imm);
719 u32 aarch64_insn_gen_add_sub_shifted_reg(enum aarch64_insn_register dst,
720 enum aarch64_insn_register src,
721 enum aarch64_insn_register reg,
723 enum aarch64_insn_variant variant,
724 enum aarch64_insn_adsb_type type)
729 case AARCH64_INSN_ADSB_ADD:
730 insn = aarch64_insn_get_add_value();
732 case AARCH64_INSN_ADSB_SUB:
733 insn = aarch64_insn_get_sub_value();
735 case AARCH64_INSN_ADSB_ADD_SETFLAGS:
736 insn = aarch64_insn_get_adds_value();
738 case AARCH64_INSN_ADSB_SUB_SETFLAGS:
739 insn = aarch64_insn_get_subs_value();
743 return AARCH64_BREAK_FAULT;
747 case AARCH64_INSN_VARIANT_32BIT:
748 BUG_ON(shift & ~(SZ_32 - 1));
750 case AARCH64_INSN_VARIANT_64BIT:
751 insn |= AARCH64_INSN_SF_BIT;
752 BUG_ON(shift & ~(SZ_64 - 1));
756 return AARCH64_BREAK_FAULT;
760 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
762 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, src);
764 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM, insn, reg);
766 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_6, insn, shift);
769 u32 aarch64_insn_gen_data1(enum aarch64_insn_register dst,
770 enum aarch64_insn_register src,
771 enum aarch64_insn_variant variant,
772 enum aarch64_insn_data1_type type)
777 case AARCH64_INSN_DATA1_REVERSE_16:
778 insn = aarch64_insn_get_rev16_value();
780 case AARCH64_INSN_DATA1_REVERSE_32:
781 insn = aarch64_insn_get_rev32_value();
783 case AARCH64_INSN_DATA1_REVERSE_64:
784 BUG_ON(variant != AARCH64_INSN_VARIANT_64BIT);
785 insn = aarch64_insn_get_rev64_value();
789 return AARCH64_BREAK_FAULT;
793 case AARCH64_INSN_VARIANT_32BIT:
795 case AARCH64_INSN_VARIANT_64BIT:
796 insn |= AARCH64_INSN_SF_BIT;
800 return AARCH64_BREAK_FAULT;
803 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
805 return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, src);
808 u32 aarch64_insn_gen_data2(enum aarch64_insn_register dst,
809 enum aarch64_insn_register src,
810 enum aarch64_insn_register reg,
811 enum aarch64_insn_variant variant,
812 enum aarch64_insn_data2_type type)
817 case AARCH64_INSN_DATA2_UDIV:
818 insn = aarch64_insn_get_udiv_value();
820 case AARCH64_INSN_DATA2_SDIV:
821 insn = aarch64_insn_get_sdiv_value();
823 case AARCH64_INSN_DATA2_LSLV:
824 insn = aarch64_insn_get_lslv_value();
826 case AARCH64_INSN_DATA2_LSRV:
827 insn = aarch64_insn_get_lsrv_value();
829 case AARCH64_INSN_DATA2_ASRV:
830 insn = aarch64_insn_get_asrv_value();
832 case AARCH64_INSN_DATA2_RORV:
833 insn = aarch64_insn_get_rorv_value();
837 return AARCH64_BREAK_FAULT;
841 case AARCH64_INSN_VARIANT_32BIT:
843 case AARCH64_INSN_VARIANT_64BIT:
844 insn |= AARCH64_INSN_SF_BIT;
848 return AARCH64_BREAK_FAULT;
851 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
853 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, src);
855 return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM, insn, reg);
858 u32 aarch64_insn_gen_data3(enum aarch64_insn_register dst,
859 enum aarch64_insn_register src,
860 enum aarch64_insn_register reg1,
861 enum aarch64_insn_register reg2,
862 enum aarch64_insn_variant variant,
863 enum aarch64_insn_data3_type type)
868 case AARCH64_INSN_DATA3_MADD:
869 insn = aarch64_insn_get_madd_value();
871 case AARCH64_INSN_DATA3_MSUB:
872 insn = aarch64_insn_get_msub_value();
876 return AARCH64_BREAK_FAULT;
880 case AARCH64_INSN_VARIANT_32BIT:
882 case AARCH64_INSN_VARIANT_64BIT:
883 insn |= AARCH64_INSN_SF_BIT;
887 return AARCH64_BREAK_FAULT;
890 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
892 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RA, insn, src);
894 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn,
897 return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM, insn,
901 u32 aarch64_insn_gen_logical_shifted_reg(enum aarch64_insn_register dst,
902 enum aarch64_insn_register src,
903 enum aarch64_insn_register reg,
905 enum aarch64_insn_variant variant,
906 enum aarch64_insn_logic_type type)
911 case AARCH64_INSN_LOGIC_AND:
912 insn = aarch64_insn_get_and_value();
914 case AARCH64_INSN_LOGIC_BIC:
915 insn = aarch64_insn_get_bic_value();
917 case AARCH64_INSN_LOGIC_ORR:
918 insn = aarch64_insn_get_orr_value();
920 case AARCH64_INSN_LOGIC_ORN:
921 insn = aarch64_insn_get_orn_value();
923 case AARCH64_INSN_LOGIC_EOR:
924 insn = aarch64_insn_get_eor_value();
926 case AARCH64_INSN_LOGIC_EON:
927 insn = aarch64_insn_get_eon_value();
929 case AARCH64_INSN_LOGIC_AND_SETFLAGS:
930 insn = aarch64_insn_get_ands_value();
932 case AARCH64_INSN_LOGIC_BIC_SETFLAGS:
933 insn = aarch64_insn_get_bics_value();
937 return AARCH64_BREAK_FAULT;
941 case AARCH64_INSN_VARIANT_32BIT:
942 BUG_ON(shift & ~(SZ_32 - 1));
944 case AARCH64_INSN_VARIANT_64BIT:
945 insn |= AARCH64_INSN_SF_BIT;
946 BUG_ON(shift & ~(SZ_64 - 1));
950 return AARCH64_BREAK_FAULT;
954 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
956 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, src);
958 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM, insn, reg);
960 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_6, insn, shift);