2 * Copyright (C) 2013 Huawei Ltd.
3 * Author: Jiang Liu <liuj97@gmail.com>
5 * Copyright (C) 2014 Zi Shen Lim <zlim.lnx@gmail.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 #include <linux/bitops.h>
20 #include <linux/bug.h>
21 #include <linux/compiler.h>
22 #include <linux/kernel.h>
24 #include <linux/smp.h>
25 #include <linux/spinlock.h>
26 #include <linux/stop_machine.h>
27 #include <linux/types.h>
28 #include <linux/uaccess.h>
30 #include <asm/cacheflush.h>
31 #include <asm/debug-monitors.h>
32 #include <asm/fixmap.h>
35 #define AARCH64_INSN_SF_BIT BIT(31)
36 #define AARCH64_INSN_N_BIT BIT(22)
38 static int aarch64_insn_encoding_class[] = {
39 AARCH64_INSN_CLS_UNKNOWN,
40 AARCH64_INSN_CLS_UNKNOWN,
41 AARCH64_INSN_CLS_UNKNOWN,
42 AARCH64_INSN_CLS_UNKNOWN,
43 AARCH64_INSN_CLS_LDST,
44 AARCH64_INSN_CLS_DP_REG,
45 AARCH64_INSN_CLS_LDST,
46 AARCH64_INSN_CLS_DP_FPSIMD,
47 AARCH64_INSN_CLS_DP_IMM,
48 AARCH64_INSN_CLS_DP_IMM,
49 AARCH64_INSN_CLS_BR_SYS,
50 AARCH64_INSN_CLS_BR_SYS,
51 AARCH64_INSN_CLS_LDST,
52 AARCH64_INSN_CLS_DP_REG,
53 AARCH64_INSN_CLS_LDST,
54 AARCH64_INSN_CLS_DP_FPSIMD,
57 enum aarch64_insn_encoding_class __kprobes aarch64_get_insn_class(u32 insn)
59 return aarch64_insn_encoding_class[(insn >> 25) & 0xf];
62 /* NOP is an alias of HINT */
63 bool __kprobes aarch64_insn_is_nop(u32 insn)
65 if (!aarch64_insn_is_hint(insn))
68 switch (insn & 0xFE0) {
69 case AARCH64_INSN_HINT_YIELD:
70 case AARCH64_INSN_HINT_WFE:
71 case AARCH64_INSN_HINT_WFI:
72 case AARCH64_INSN_HINT_SEV:
73 case AARCH64_INSN_HINT_SEVL:
80 static DEFINE_SPINLOCK(patch_lock);
82 static void __kprobes *patch_map(void *addr, int fixmap)
84 unsigned long uintaddr = (uintptr_t) addr;
85 bool module = !core_kernel_text(uintaddr);
88 if (module && IS_ENABLED(CONFIG_DEBUG_SET_MODULE_RONX))
89 page = vmalloc_to_page(addr);
90 else if (!module && IS_ENABLED(CONFIG_DEBUG_RODATA))
91 page = virt_to_page(addr);
96 set_fixmap(fixmap, page_to_phys(page));
98 return (void *) (__fix_to_virt(fixmap) + (uintaddr & ~PAGE_MASK));
101 static void __kprobes patch_unmap(int fixmap)
103 clear_fixmap(fixmap);
106 * In ARMv8-A, A64 instructions have a fixed length of 32 bits and are always
109 int __kprobes aarch64_insn_read(void *addr, u32 *insnp)
114 ret = probe_kernel_read(&val, addr, AARCH64_INSN_SIZE);
116 *insnp = le32_to_cpu(val);
121 static int __kprobes __aarch64_insn_write(void *addr, u32 insn)
124 unsigned long flags = 0;
127 spin_lock_irqsave(&patch_lock, flags);
128 waddr = patch_map(addr, FIX_TEXT_POKE0);
130 ret = probe_kernel_write(waddr, &insn, AARCH64_INSN_SIZE);
132 patch_unmap(FIX_TEXT_POKE0);
133 spin_unlock_irqrestore(&patch_lock, flags);
138 int __kprobes aarch64_insn_write(void *addr, u32 insn)
140 insn = cpu_to_le32(insn);
141 return __aarch64_insn_write(addr, insn);
144 static bool __kprobes __aarch64_insn_hotpatch_safe(u32 insn)
146 if (aarch64_get_insn_class(insn) != AARCH64_INSN_CLS_BR_SYS)
149 return aarch64_insn_is_b(insn) ||
150 aarch64_insn_is_bl(insn) ||
151 aarch64_insn_is_svc(insn) ||
152 aarch64_insn_is_hvc(insn) ||
153 aarch64_insn_is_smc(insn) ||
154 aarch64_insn_is_brk(insn) ||
155 aarch64_insn_is_nop(insn);
159 * ARM Architecture Reference Manual for ARMv8 Profile-A, Issue A.a
160 * Section B2.6.5 "Concurrent modification and execution of instructions":
161 * Concurrent modification and execution of instructions can lead to the
162 * resulting instruction performing any behavior that can be achieved by
163 * executing any sequence of instructions that can be executed from the
164 * same Exception level, except where the instruction before modification
165 * and the instruction after modification is a B, BL, NOP, BKPT, SVC, HVC,
166 * or SMC instruction.
168 bool __kprobes aarch64_insn_hotpatch_safe(u32 old_insn, u32 new_insn)
170 return __aarch64_insn_hotpatch_safe(old_insn) &&
171 __aarch64_insn_hotpatch_safe(new_insn);
174 int __kprobes aarch64_insn_patch_text_nosync(void *addr, u32 insn)
179 /* A64 instructions must be word aligned */
180 if ((uintptr_t)tp & 0x3)
183 ret = aarch64_insn_write(tp, insn);
185 flush_icache_range((uintptr_t)tp,
186 (uintptr_t)tp + AARCH64_INSN_SIZE);
191 struct aarch64_insn_patch {
198 static int __kprobes aarch64_insn_patch_text_cb(void *arg)
201 struct aarch64_insn_patch *pp = arg;
203 /* The first CPU becomes master */
204 if (atomic_inc_return(&pp->cpu_count) == 1) {
205 for (i = 0; ret == 0 && i < pp->insn_cnt; i++)
206 ret = aarch64_insn_patch_text_nosync(pp->text_addrs[i],
209 * aarch64_insn_patch_text_nosync() calls flush_icache_range(),
210 * which ends with "dsb; isb" pair guaranteeing global
213 /* Notify other processors with an additional increment. */
214 atomic_inc(&pp->cpu_count);
216 while (atomic_read(&pp->cpu_count) <= num_online_cpus())
224 int __kprobes aarch64_insn_patch_text_sync(void *addrs[], u32 insns[], int cnt)
226 struct aarch64_insn_patch patch = {
230 .cpu_count = ATOMIC_INIT(0),
236 return stop_machine(aarch64_insn_patch_text_cb, &patch,
240 int __kprobes aarch64_insn_patch_text(void *addrs[], u32 insns[], int cnt)
245 /* Unsafe to patch multiple instructions without synchronizaiton */
247 ret = aarch64_insn_read(addrs[0], &insn);
251 if (aarch64_insn_hotpatch_safe(insn, insns[0])) {
253 * ARMv8 architecture doesn't guarantee all CPUs see
254 * the new instruction after returning from function
255 * aarch64_insn_patch_text_nosync(). So send IPIs to
256 * all other CPUs to achieve instruction
259 ret = aarch64_insn_patch_text_nosync(addrs[0], insns[0]);
260 kick_all_cpus_sync();
265 return aarch64_insn_patch_text_sync(addrs, insns, cnt);
268 u32 __kprobes aarch64_insn_encode_immediate(enum aarch64_insn_imm_type type,
271 u32 immlo, immhi, lomask, himask, mask;
275 case AARCH64_INSN_IMM_ADR:
278 immlo = imm & lomask;
280 immhi = imm & himask;
281 imm = (immlo << 24) | (immhi);
282 mask = (lomask << 24) | (himask);
285 case AARCH64_INSN_IMM_26:
289 case AARCH64_INSN_IMM_19:
293 case AARCH64_INSN_IMM_16:
297 case AARCH64_INSN_IMM_14:
301 case AARCH64_INSN_IMM_12:
305 case AARCH64_INSN_IMM_9:
309 case AARCH64_INSN_IMM_7:
313 case AARCH64_INSN_IMM_6:
314 case AARCH64_INSN_IMM_S:
318 case AARCH64_INSN_IMM_R:
323 pr_err("aarch64_insn_encode_immediate: unknown immediate encoding %d\n",
328 /* Update the immediate field. */
329 insn &= ~(mask << shift);
330 insn |= (imm & mask) << shift;
335 static u32 aarch64_insn_encode_register(enum aarch64_insn_register_type type,
337 enum aarch64_insn_register reg)
341 if (reg < AARCH64_INSN_REG_0 || reg > AARCH64_INSN_REG_SP) {
342 pr_err("%s: unknown register encoding %d\n", __func__, reg);
347 case AARCH64_INSN_REGTYPE_RT:
348 case AARCH64_INSN_REGTYPE_RD:
351 case AARCH64_INSN_REGTYPE_RN:
354 case AARCH64_INSN_REGTYPE_RT2:
355 case AARCH64_INSN_REGTYPE_RA:
358 case AARCH64_INSN_REGTYPE_RM:
362 pr_err("%s: unknown register type encoding %d\n", __func__,
367 insn &= ~(GENMASK(4, 0) << shift);
368 insn |= reg << shift;
373 static u32 aarch64_insn_encode_ldst_size(enum aarch64_insn_size_type type,
379 case AARCH64_INSN_SIZE_8:
382 case AARCH64_INSN_SIZE_16:
385 case AARCH64_INSN_SIZE_32:
388 case AARCH64_INSN_SIZE_64:
392 pr_err("%s: unknown size encoding %d\n", __func__, type);
396 insn &= ~GENMASK(31, 30);
402 static inline long branch_imm_common(unsigned long pc, unsigned long addr,
408 * PC: A 64-bit Program Counter holding the address of the current
409 * instruction. A64 instructions must be word-aligned.
411 BUG_ON((pc & 0x3) || (addr & 0x3));
413 offset = ((long)addr - (long)pc);
414 BUG_ON(offset < -range || offset >= range);
419 u32 __kprobes aarch64_insn_gen_branch_imm(unsigned long pc, unsigned long addr,
420 enum aarch64_insn_branch_type type)
426 * B/BL support [-128M, 128M) offset
427 * ARM64 virtual address arrangement guarantees all kernel and module
428 * texts are within +/-128M.
430 offset = branch_imm_common(pc, addr, SZ_128M);
433 case AARCH64_INSN_BRANCH_LINK:
434 insn = aarch64_insn_get_bl_value();
436 case AARCH64_INSN_BRANCH_NOLINK:
437 insn = aarch64_insn_get_b_value();
441 return AARCH64_BREAK_FAULT;
444 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_26, insn,
448 u32 aarch64_insn_gen_comp_branch_imm(unsigned long pc, unsigned long addr,
449 enum aarch64_insn_register reg,
450 enum aarch64_insn_variant variant,
451 enum aarch64_insn_branch_type type)
456 offset = branch_imm_common(pc, addr, SZ_1M);
459 case AARCH64_INSN_BRANCH_COMP_ZERO:
460 insn = aarch64_insn_get_cbz_value();
462 case AARCH64_INSN_BRANCH_COMP_NONZERO:
463 insn = aarch64_insn_get_cbnz_value();
467 return AARCH64_BREAK_FAULT;
471 case AARCH64_INSN_VARIANT_32BIT:
473 case AARCH64_INSN_VARIANT_64BIT:
474 insn |= AARCH64_INSN_SF_BIT;
478 return AARCH64_BREAK_FAULT;
481 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT, insn, reg);
483 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_19, insn,
487 u32 aarch64_insn_gen_cond_branch_imm(unsigned long pc, unsigned long addr,
488 enum aarch64_insn_condition cond)
493 offset = branch_imm_common(pc, addr, SZ_1M);
495 insn = aarch64_insn_get_bcond_value();
497 BUG_ON(cond < AARCH64_INSN_COND_EQ || cond > AARCH64_INSN_COND_AL);
500 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_19, insn,
504 u32 __kprobes aarch64_insn_gen_hint(enum aarch64_insn_hint_op op)
506 return aarch64_insn_get_hint_value() | op;
509 u32 __kprobes aarch64_insn_gen_nop(void)
511 return aarch64_insn_gen_hint(AARCH64_INSN_HINT_NOP);
514 u32 aarch64_insn_gen_branch_reg(enum aarch64_insn_register reg,
515 enum aarch64_insn_branch_type type)
520 case AARCH64_INSN_BRANCH_NOLINK:
521 insn = aarch64_insn_get_br_value();
523 case AARCH64_INSN_BRANCH_LINK:
524 insn = aarch64_insn_get_blr_value();
526 case AARCH64_INSN_BRANCH_RETURN:
527 insn = aarch64_insn_get_ret_value();
531 return AARCH64_BREAK_FAULT;
534 return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, reg);
537 u32 aarch64_insn_gen_load_store_reg(enum aarch64_insn_register reg,
538 enum aarch64_insn_register base,
539 enum aarch64_insn_register offset,
540 enum aarch64_insn_size_type size,
541 enum aarch64_insn_ldst_type type)
546 case AARCH64_INSN_LDST_LOAD_REG_OFFSET:
547 insn = aarch64_insn_get_ldr_reg_value();
549 case AARCH64_INSN_LDST_STORE_REG_OFFSET:
550 insn = aarch64_insn_get_str_reg_value();
554 return AARCH64_BREAK_FAULT;
557 insn = aarch64_insn_encode_ldst_size(size, insn);
559 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT, insn, reg);
561 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn,
564 return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM, insn,
568 u32 aarch64_insn_gen_load_store_pair(enum aarch64_insn_register reg1,
569 enum aarch64_insn_register reg2,
570 enum aarch64_insn_register base,
572 enum aarch64_insn_variant variant,
573 enum aarch64_insn_ldst_type type)
579 case AARCH64_INSN_LDST_LOAD_PAIR_PRE_INDEX:
580 insn = aarch64_insn_get_ldp_pre_value();
582 case AARCH64_INSN_LDST_STORE_PAIR_PRE_INDEX:
583 insn = aarch64_insn_get_stp_pre_value();
585 case AARCH64_INSN_LDST_LOAD_PAIR_POST_INDEX:
586 insn = aarch64_insn_get_ldp_post_value();
588 case AARCH64_INSN_LDST_STORE_PAIR_POST_INDEX:
589 insn = aarch64_insn_get_stp_post_value();
593 return AARCH64_BREAK_FAULT;
597 case AARCH64_INSN_VARIANT_32BIT:
598 /* offset must be multiples of 4 in the range [-256, 252] */
599 BUG_ON(offset & 0x3);
600 BUG_ON(offset < -256 || offset > 252);
603 case AARCH64_INSN_VARIANT_64BIT:
604 /* offset must be multiples of 8 in the range [-512, 504] */
605 BUG_ON(offset & 0x7);
606 BUG_ON(offset < -512 || offset > 504);
608 insn |= AARCH64_INSN_SF_BIT;
612 return AARCH64_BREAK_FAULT;
615 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT, insn,
618 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT2, insn,
621 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn,
624 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_7, insn,
628 u32 aarch64_insn_gen_add_sub_imm(enum aarch64_insn_register dst,
629 enum aarch64_insn_register src,
630 int imm, enum aarch64_insn_variant variant,
631 enum aarch64_insn_adsb_type type)
636 case AARCH64_INSN_ADSB_ADD:
637 insn = aarch64_insn_get_add_imm_value();
639 case AARCH64_INSN_ADSB_SUB:
640 insn = aarch64_insn_get_sub_imm_value();
642 case AARCH64_INSN_ADSB_ADD_SETFLAGS:
643 insn = aarch64_insn_get_adds_imm_value();
645 case AARCH64_INSN_ADSB_SUB_SETFLAGS:
646 insn = aarch64_insn_get_subs_imm_value();
650 return AARCH64_BREAK_FAULT;
654 case AARCH64_INSN_VARIANT_32BIT:
656 case AARCH64_INSN_VARIANT_64BIT:
657 insn |= AARCH64_INSN_SF_BIT;
661 return AARCH64_BREAK_FAULT;
664 BUG_ON(imm & ~(SZ_4K - 1));
666 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
668 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, src);
670 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_12, insn, imm);
673 u32 aarch64_insn_gen_bitfield(enum aarch64_insn_register dst,
674 enum aarch64_insn_register src,
676 enum aarch64_insn_variant variant,
677 enum aarch64_insn_bitfield_type type)
683 case AARCH64_INSN_BITFIELD_MOVE:
684 insn = aarch64_insn_get_bfm_value();
686 case AARCH64_INSN_BITFIELD_MOVE_UNSIGNED:
687 insn = aarch64_insn_get_ubfm_value();
689 case AARCH64_INSN_BITFIELD_MOVE_SIGNED:
690 insn = aarch64_insn_get_sbfm_value();
694 return AARCH64_BREAK_FAULT;
698 case AARCH64_INSN_VARIANT_32BIT:
699 mask = GENMASK(4, 0);
701 case AARCH64_INSN_VARIANT_64BIT:
702 insn |= AARCH64_INSN_SF_BIT | AARCH64_INSN_N_BIT;
703 mask = GENMASK(5, 0);
707 return AARCH64_BREAK_FAULT;
710 BUG_ON(immr & ~mask);
711 BUG_ON(imms & ~mask);
713 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
715 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, src);
717 insn = aarch64_insn_encode_immediate(AARCH64_INSN_IMM_R, insn, immr);
719 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_S, insn, imms);
722 u32 aarch64_insn_gen_movewide(enum aarch64_insn_register dst,
724 enum aarch64_insn_variant variant,
725 enum aarch64_insn_movewide_type type)
730 case AARCH64_INSN_MOVEWIDE_ZERO:
731 insn = aarch64_insn_get_movz_value();
733 case AARCH64_INSN_MOVEWIDE_KEEP:
734 insn = aarch64_insn_get_movk_value();
736 case AARCH64_INSN_MOVEWIDE_INVERSE:
737 insn = aarch64_insn_get_movn_value();
741 return AARCH64_BREAK_FAULT;
744 BUG_ON(imm & ~(SZ_64K - 1));
747 case AARCH64_INSN_VARIANT_32BIT:
748 BUG_ON(shift != 0 && shift != 16);
750 case AARCH64_INSN_VARIANT_64BIT:
751 insn |= AARCH64_INSN_SF_BIT;
752 BUG_ON(shift != 0 && shift != 16 && shift != 32 &&
757 return AARCH64_BREAK_FAULT;
760 insn |= (shift >> 4) << 21;
762 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
764 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_16, insn, imm);
767 u32 aarch64_insn_gen_add_sub_shifted_reg(enum aarch64_insn_register dst,
768 enum aarch64_insn_register src,
769 enum aarch64_insn_register reg,
771 enum aarch64_insn_variant variant,
772 enum aarch64_insn_adsb_type type)
777 case AARCH64_INSN_ADSB_ADD:
778 insn = aarch64_insn_get_add_value();
780 case AARCH64_INSN_ADSB_SUB:
781 insn = aarch64_insn_get_sub_value();
783 case AARCH64_INSN_ADSB_ADD_SETFLAGS:
784 insn = aarch64_insn_get_adds_value();
786 case AARCH64_INSN_ADSB_SUB_SETFLAGS:
787 insn = aarch64_insn_get_subs_value();
791 return AARCH64_BREAK_FAULT;
795 case AARCH64_INSN_VARIANT_32BIT:
796 BUG_ON(shift & ~(SZ_32 - 1));
798 case AARCH64_INSN_VARIANT_64BIT:
799 insn |= AARCH64_INSN_SF_BIT;
800 BUG_ON(shift & ~(SZ_64 - 1));
804 return AARCH64_BREAK_FAULT;
808 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
810 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, src);
812 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM, insn, reg);
814 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_6, insn, shift);
817 u32 aarch64_insn_gen_data1(enum aarch64_insn_register dst,
818 enum aarch64_insn_register src,
819 enum aarch64_insn_variant variant,
820 enum aarch64_insn_data1_type type)
825 case AARCH64_INSN_DATA1_REVERSE_16:
826 insn = aarch64_insn_get_rev16_value();
828 case AARCH64_INSN_DATA1_REVERSE_32:
829 insn = aarch64_insn_get_rev32_value();
831 case AARCH64_INSN_DATA1_REVERSE_64:
832 BUG_ON(variant != AARCH64_INSN_VARIANT_64BIT);
833 insn = aarch64_insn_get_rev64_value();
837 return AARCH64_BREAK_FAULT;
841 case AARCH64_INSN_VARIANT_32BIT:
843 case AARCH64_INSN_VARIANT_64BIT:
844 insn |= AARCH64_INSN_SF_BIT;
848 return AARCH64_BREAK_FAULT;
851 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
853 return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, src);
856 u32 aarch64_insn_gen_data2(enum aarch64_insn_register dst,
857 enum aarch64_insn_register src,
858 enum aarch64_insn_register reg,
859 enum aarch64_insn_variant variant,
860 enum aarch64_insn_data2_type type)
865 case AARCH64_INSN_DATA2_UDIV:
866 insn = aarch64_insn_get_udiv_value();
868 case AARCH64_INSN_DATA2_SDIV:
869 insn = aarch64_insn_get_sdiv_value();
871 case AARCH64_INSN_DATA2_LSLV:
872 insn = aarch64_insn_get_lslv_value();
874 case AARCH64_INSN_DATA2_LSRV:
875 insn = aarch64_insn_get_lsrv_value();
877 case AARCH64_INSN_DATA2_ASRV:
878 insn = aarch64_insn_get_asrv_value();
880 case AARCH64_INSN_DATA2_RORV:
881 insn = aarch64_insn_get_rorv_value();
885 return AARCH64_BREAK_FAULT;
889 case AARCH64_INSN_VARIANT_32BIT:
891 case AARCH64_INSN_VARIANT_64BIT:
892 insn |= AARCH64_INSN_SF_BIT;
896 return AARCH64_BREAK_FAULT;
899 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
901 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, src);
903 return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM, insn, reg);
906 u32 aarch64_insn_gen_data3(enum aarch64_insn_register dst,
907 enum aarch64_insn_register src,
908 enum aarch64_insn_register reg1,
909 enum aarch64_insn_register reg2,
910 enum aarch64_insn_variant variant,
911 enum aarch64_insn_data3_type type)
916 case AARCH64_INSN_DATA3_MADD:
917 insn = aarch64_insn_get_madd_value();
919 case AARCH64_INSN_DATA3_MSUB:
920 insn = aarch64_insn_get_msub_value();
924 return AARCH64_BREAK_FAULT;
928 case AARCH64_INSN_VARIANT_32BIT:
930 case AARCH64_INSN_VARIANT_64BIT:
931 insn |= AARCH64_INSN_SF_BIT;
935 return AARCH64_BREAK_FAULT;
938 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
940 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RA, insn, src);
942 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn,
945 return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM, insn,
949 u32 aarch64_insn_gen_logical_shifted_reg(enum aarch64_insn_register dst,
950 enum aarch64_insn_register src,
951 enum aarch64_insn_register reg,
953 enum aarch64_insn_variant variant,
954 enum aarch64_insn_logic_type type)
959 case AARCH64_INSN_LOGIC_AND:
960 insn = aarch64_insn_get_and_value();
962 case AARCH64_INSN_LOGIC_BIC:
963 insn = aarch64_insn_get_bic_value();
965 case AARCH64_INSN_LOGIC_ORR:
966 insn = aarch64_insn_get_orr_value();
968 case AARCH64_INSN_LOGIC_ORN:
969 insn = aarch64_insn_get_orn_value();
971 case AARCH64_INSN_LOGIC_EOR:
972 insn = aarch64_insn_get_eor_value();
974 case AARCH64_INSN_LOGIC_EON:
975 insn = aarch64_insn_get_eon_value();
977 case AARCH64_INSN_LOGIC_AND_SETFLAGS:
978 insn = aarch64_insn_get_ands_value();
980 case AARCH64_INSN_LOGIC_BIC_SETFLAGS:
981 insn = aarch64_insn_get_bics_value();
985 return AARCH64_BREAK_FAULT;
989 case AARCH64_INSN_VARIANT_32BIT:
990 BUG_ON(shift & ~(SZ_32 - 1));
992 case AARCH64_INSN_VARIANT_64BIT:
993 insn |= AARCH64_INSN_SF_BIT;
994 BUG_ON(shift & ~(SZ_64 - 1));
998 return AARCH64_BREAK_FAULT;
1002 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
1004 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, src);
1006 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM, insn, reg);
1008 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_6, insn, shift);
1011 bool aarch32_insn_is_wide(u32 insn)
1013 return insn >= 0xe800;
1017 * Macros/defines for extracting register numbers from instruction.
1019 u32 aarch32_insn_extract_reg_num(u32 insn, int offset)
1021 return (insn & (0xf << offset)) >> offset;
1024 #define OPC2_MASK 0x7
1025 #define OPC2_OFFSET 5
1026 u32 aarch32_insn_mcr_extract_opc2(u32 insn)
1028 return (insn & (OPC2_MASK << OPC2_OFFSET)) >> OPC2_OFFSET;
1031 #define CRM_MASK 0xf
1032 u32 aarch32_insn_mcr_extract_crm(u32 insn)
1034 return insn & CRM_MASK;