2 * Low-level CPU initialisation
3 * Based on arch/arm/kernel/head.S
5 * Copyright (C) 1994-2002 Russell King
6 * Copyright (C) 2003-2012 ARM Ltd.
7 * Authors: Catalin Marinas <catalin.marinas@arm.com>
8 * Will Deacon <will.deacon@arm.com>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 #include <linux/linkage.h>
24 #include <linux/init.h>
25 #include <linux/irqchip/arm-gic-v3.h>
27 #include <asm/assembler.h>
28 #include <asm/ptrace.h>
29 #include <asm/asm-offsets.h>
30 #include <asm/cache.h>
31 #include <asm/cputype.h>
32 #include <asm/kernel-pgtable.h>
33 #include <asm/memory.h>
34 #include <asm/pgtable-hwdef.h>
35 #include <asm/pgtable.h>
37 #include <asm/sysreg.h>
38 #include <asm/thread_info.h>
41 #define __PHYS_OFFSET (KERNEL_START - TEXT_OFFSET)
43 #if (TEXT_OFFSET & 0xfff) != 0
44 #error TEXT_OFFSET must be at least 4KB aligned
45 #elif (PAGE_OFFSET & 0x1fffff) != 0
46 #error PAGE_OFFSET must be at least 2MB aligned
47 #elif TEXT_OFFSET > 0x1fffff
48 #error TEXT_OFFSET must be less than 2MB
51 #define KERNEL_START _text
52 #define KERNEL_END _end
55 * Kernel startup entry point.
56 * ---------------------------
58 * The requirements are:
59 * MMU = off, D-cache = off, I-cache = on or off,
60 * x0 = physical address to the FDT blob.
62 * This code is mostly position independent so you call this at
63 * __pa(PAGE_OFFSET + TEXT_OFFSET).
65 * Note that the callee-saved registers are used for storing variables
66 * that are useful before the MMU is enabled. The allocations are described
67 * in the entry routines.
72 * DO NOT MODIFY. Image header expected by Linux boot-loaders.
76 * This add instruction has no meaningful effect except that
77 * its opcode forms the magic "MZ" signature required by UEFI.
82 b stext // branch to kernel start, magic
85 le64sym _kernel_offset_le // Image load offset from start of RAM, little-endian
86 le64sym _kernel_size_le // Effective size of kernel image, little-endian
87 le64sym _kernel_flags_le // Informative flags, little-endian
91 .byte 0x41 // Magic number, "ARM\x64"
96 .long pe_header - _head // Offset to the PE header.
102 .globl __efistub_stext_offset
103 .set __efistub_stext_offset, stext - _head
109 .short 0xaa64 // AArch64
110 .short 2 // nr_sections
111 .long 0 // TimeDateStamp
112 .long 0 // PointerToSymbolTable
113 .long 1 // NumberOfSymbols
114 .short section_table - optional_header // SizeOfOptionalHeader
115 .short 0x206 // Characteristics.
116 // IMAGE_FILE_DEBUG_STRIPPED |
117 // IMAGE_FILE_EXECUTABLE_IMAGE |
118 // IMAGE_FILE_LINE_NUMS_STRIPPED
120 .short 0x20b // PE32+ format
121 .byte 0x02 // MajorLinkerVersion
122 .byte 0x14 // MinorLinkerVersion
123 .long _end - stext // SizeOfCode
124 .long 0 // SizeOfInitializedData
125 .long 0 // SizeOfUninitializedData
126 .long __efistub_entry - _head // AddressOfEntryPoint
127 .long __efistub_stext_offset // BaseOfCode
131 .long 0x1000 // SectionAlignment
132 .long PECOFF_FILE_ALIGNMENT // FileAlignment
133 .short 0 // MajorOperatingSystemVersion
134 .short 0 // MinorOperatingSystemVersion
135 .short 0 // MajorImageVersion
136 .short 0 // MinorImageVersion
137 .short 0 // MajorSubsystemVersion
138 .short 0 // MinorSubsystemVersion
139 .long 0 // Win32VersionValue
141 .long _end - _head // SizeOfImage
143 // Everything before the kernel image is considered part of the header
144 .long __efistub_stext_offset // SizeOfHeaders
146 .short 0xa // Subsystem (EFI application)
147 .short 0 // DllCharacteristics
148 .quad 0 // SizeOfStackReserve
149 .quad 0 // SizeOfStackCommit
150 .quad 0 // SizeOfHeapReserve
151 .quad 0 // SizeOfHeapCommit
152 .long 0 // LoaderFlags
153 .long 0x6 // NumberOfRvaAndSizes
155 .quad 0 // ExportTable
156 .quad 0 // ImportTable
157 .quad 0 // ResourceTable
158 .quad 0 // ExceptionTable
159 .quad 0 // CertificationTable
160 .quad 0 // BaseRelocationTable
166 * The EFI application loader requires a relocation section
167 * because EFI applications must be relocatable. This is a
168 * dummy section as far as we are concerned.
172 .byte 0 // end of 0 padding of section name
175 .long 0 // SizeOfRawData
176 .long 0 // PointerToRawData
177 .long 0 // PointerToRelocations
178 .long 0 // PointerToLineNumbers
179 .short 0 // NumberOfRelocations
180 .short 0 // NumberOfLineNumbers
181 .long 0x42100040 // Characteristics (section flags)
187 .byte 0 // end of 0 padding of section name
188 .long _end - stext // VirtualSize
189 .long __efistub_stext_offset // VirtualAddress
190 .long _edata - stext // SizeOfRawData
191 .long __efistub_stext_offset // PointerToRawData
193 .long 0 // PointerToRelocations (0 for executables)
194 .long 0 // PointerToLineNumbers (0 for executables)
195 .short 0 // NumberOfRelocations (0 for executables)
196 .short 0 // NumberOfLineNumbers (0 for executables)
197 .long 0xe0500020 // Characteristics (section flags)
200 * EFI will load stext onwards at the 4k section alignment
201 * described in the PE/COFF header. To ensure that instruction
202 * sequences using an adrp and a :lo12: immediate will function
203 * correctly at this alignment, we must ensure that stext is
204 * placed at a 4k boundary in the Image to begin with.
210 bl preserve_boot_args
211 bl el2_setup // Drop to EL1, w20=cpu_boot_mode
212 adrp x24, __PHYS_OFFSET
213 bl set_cpu_boot_mode_flag
214 bl __create_page_tables // x25=TTBR0, x26=TTBR1
216 * The following calls CPU setup code, see arch/arm64/mm/proc.S for
218 * On return, the CPU will be ready for the MMU to be turned on and
219 * the TCR will have been set.
221 ldr x27, 0f // address to jump to after
222 // MMU has been enabled
223 adr_l lr, __enable_mmu // return (PIC) address
224 b __cpu_setup // initialise processor
227 0: .quad __mmap_switched - (_head - TEXT_OFFSET) + KIMAGE_VADDR
230 * Preserve the arguments passed by the bootloader in x0 .. x3
233 mov x21, x0 // x21=FDT
235 adr_l x0, boot_args // record the contents of
236 stp x21, x1, [x0] // x0 .. x3 at kernel entry
237 stp x2, x3, [x0, #16]
239 dmb sy // needed before dc ivac with
242 add x1, x0, #0x20 // 4 x 8 bytes
243 b __inval_cache_range // tail call
244 ENDPROC(preserve_boot_args)
247 * Macro to create a table entry to the next page.
249 * tbl: page table address
250 * virt: virtual address
251 * shift: #imm page table shift
252 * ptrs: #imm pointers per table page
255 * Corrupts: tmp1, tmp2
256 * Returns: tbl -> next level table page address
258 .macro create_table_entry, tbl, virt, shift, ptrs, tmp1, tmp2
259 lsr \tmp1, \virt, #\shift
260 and \tmp1, \tmp1, #\ptrs - 1 // table index
261 add \tmp2, \tbl, #PAGE_SIZE
262 orr \tmp2, \tmp2, #PMD_TYPE_TABLE // address of next table and entry type
263 str \tmp2, [\tbl, \tmp1, lsl #3]
264 add \tbl, \tbl, #PAGE_SIZE // next level table page
268 * Macro to populate the PGD (and possibily PUD) for the corresponding
269 * block entry in the next level (tbl) for the given virtual address.
271 * Preserves: tbl, next, virt
272 * Corrupts: tmp1, tmp2
274 .macro create_pgd_entry, tbl, virt, tmp1, tmp2
275 create_table_entry \tbl, \virt, PGDIR_SHIFT, PTRS_PER_PGD, \tmp1, \tmp2
276 #if SWAPPER_PGTABLE_LEVELS > 3
277 create_table_entry \tbl, \virt, PUD_SHIFT, PTRS_PER_PUD, \tmp1, \tmp2
279 #if SWAPPER_PGTABLE_LEVELS > 2
280 create_table_entry \tbl, \virt, SWAPPER_TABLE_SHIFT, PTRS_PER_PTE, \tmp1, \tmp2
285 * Macro to populate block entries in the page table for the start..end
286 * virtual range (inclusive).
288 * Preserves: tbl, flags
289 * Corrupts: phys, start, end, pstate
291 .macro create_block_map, tbl, flags, phys, start, end
292 lsr \phys, \phys, #SWAPPER_BLOCK_SHIFT
293 lsr \start, \start, #SWAPPER_BLOCK_SHIFT
294 and \start, \start, #PTRS_PER_PTE - 1 // table index
295 orr \phys, \flags, \phys, lsl #SWAPPER_BLOCK_SHIFT // table entry
296 lsr \end, \end, #SWAPPER_BLOCK_SHIFT
297 and \end, \end, #PTRS_PER_PTE - 1 // table end index
298 9999: str \phys, [\tbl, \start, lsl #3] // store the entry
299 add \start, \start, #1 // next entry
300 add \phys, \phys, #SWAPPER_BLOCK_SIZE // next block
306 * Setup the initial page tables. We only setup the barest amount which is
307 * required to get the kernel running. The following sections are required:
308 * - identity mapping to enable the MMU (low address, TTBR0)
309 * - first few MB of the kernel linear mapping to jump to once the MMU has
312 __create_page_tables:
313 adrp x25, idmap_pg_dir
314 adrp x26, swapper_pg_dir
318 * Invalidate the idmap and swapper page tables to avoid potential
319 * dirty cache lines being evicted.
322 add x1, x26, #SWAPPER_DIR_SIZE
323 bl __inval_cache_range
326 * Clear the idmap and swapper page tables.
329 add x6, x26, #SWAPPER_DIR_SIZE
330 1: stp xzr, xzr, [x0], #16
331 stp xzr, xzr, [x0], #16
332 stp xzr, xzr, [x0], #16
333 stp xzr, xzr, [x0], #16
337 ldr x7, =SWAPPER_MM_MMUFLAGS
340 * Create the identity mapping.
342 mov x0, x25 // idmap_pg_dir
343 adrp x3, __idmap_text_start // __pa(__idmap_text_start)
345 #ifndef CONFIG_ARM64_VA_BITS_48
346 #define EXTRA_SHIFT (PGDIR_SHIFT + PAGE_SHIFT - 3)
347 #define EXTRA_PTRS (1 << (48 - EXTRA_SHIFT))
350 * If VA_BITS < 48, it may be too small to allow for an ID mapping to be
351 * created that covers system RAM if that is located sufficiently high
352 * in the physical address space. So for the ID map, use an extended
353 * virtual range in that case, by configuring an additional translation
355 * First, we have to verify our assumption that the current value of
356 * VA_BITS was chosen such that all translation levels are fully
357 * utilised, and that lowering T0SZ will always result in an additional
358 * translation level to be configured.
360 #if VA_BITS != EXTRA_SHIFT
361 #error "Mismatch between VA_BITS and page size/number of translation levels"
365 * Calculate the maximum allowed value for TCR_EL1.T0SZ so that the
366 * entire ID map region can be mapped. As T0SZ == (64 - #bits used),
367 * this number conveniently equals the number of leading zeroes in
368 * the physical address of __idmap_text_end.
370 adrp x5, __idmap_text_end
372 cmp x5, TCR_T0SZ(VA_BITS) // default T0SZ small enough?
373 b.ge 1f // .. then skip additional level
378 dc ivac, x6 // Invalidate potentially stale cache line
380 create_table_entry x0, x3, EXTRA_SHIFT, EXTRA_PTRS, x5, x6
384 create_pgd_entry x0, x3, x5, x6
385 mov x5, x3 // __pa(__idmap_text_start)
386 adr_l x6, __idmap_text_end // __pa(__idmap_text_end)
387 create_block_map x0, x7, x3, x5, x6
390 * Map the kernel image (starting with PHYS_OFFSET).
392 mov x0, x26 // swapper_pg_dir
393 ldr x5, =KIMAGE_VADDR
394 create_pgd_entry x0, x5, x3, x6
395 ldr w6, kernel_img_size
397 mov x3, x24 // phys offset
398 create_block_map x0, x7, x3, x5, x6
401 * Since the page tables have been populated with non-cacheable
402 * accesses (MMU disabled), invalidate the idmap and swapper page
403 * tables again to remove any speculatively loaded cache lines.
406 add x1, x26, #SWAPPER_DIR_SIZE
408 bl __inval_cache_range
412 ENDPROC(__create_page_tables)
415 .long _end - (_head - TEXT_OFFSET)
419 * The following fragment of code is executed with the MMU enabled.
421 .set initial_sp, init_thread_union + THREAD_START_SP
423 adr_l x8, vectors // load VBAR_EL1 with virtual
424 msr vbar_el1, x8 // vector table address
428 adr_l x0, __bss_start
433 dsb ishst // Make zero page visible to PTW
435 adr_l sp, initial_sp, x4
437 and x4, x4, #~(THREAD_SIZE - 1)
438 msr sp_el0, x4 // Save thread_info
439 str_l x21, __fdt_pointer, x5 // Save FDT pointer
441 ldr x4, =KIMAGE_VADDR // Save the offset between
442 sub x4, x4, x24 // the kernel virtual and
443 str_l x4, kimage_voffset, x5 // physical mappings
450 ENDPROC(__mmap_switched)
453 * end early head section, begin head code that is also used for
454 * hotplug and needs to have the same protections as the text region
456 .section ".text","ax"
458 * If we're fortunate enough to boot at EL2, ensure that the world is
459 * sane before dropping to EL1.
461 * Returns either BOOT_CPU_MODE_EL1 or BOOT_CPU_MODE_EL2 in x20 if
462 * booted in EL1 or EL2 respectively.
466 cmp x0, #CurrentEL_EL2
469 CPU_BE( orr x0, x0, #(1 << 25) ) // Set the EE bit for EL2
470 CPU_LE( bic x0, x0, #(1 << 25) ) // Clear the EE bit for EL2
474 CPU_BE( orr x0, x0, #(3 << 24) ) // Set the EE and E0E bits for EL1
475 CPU_LE( bic x0, x0, #(3 << 24) ) // Clear the EE and E0E bits for EL1
477 mov w20, #BOOT_CPU_MODE_EL1 // This cpu booted in EL1
481 /* Hyp configuration. */
482 2: mov x0, #(1 << 31) // 64-bit EL1
485 /* Generic timers. */
487 orr x0, x0, #3 // Enable EL1 physical timers
489 msr cntvoff_el2, xzr // Clear virtual offset
491 #ifdef CONFIG_ARM_GIC_V3
492 /* GICv3 system register access */
493 mrs x0, id_aa64pfr0_el1
498 mrs_s x0, ICC_SRE_EL2
499 orr x0, x0, #ICC_SRE_EL2_SRE // Set ICC_SRE_EL2.SRE==1
500 orr x0, x0, #ICC_SRE_EL2_ENABLE // Set ICC_SRE_EL2.Enable==1
501 msr_s ICC_SRE_EL2, x0
502 isb // Make sure SRE is now set
503 mrs_s x0, ICC_SRE_EL2 // Read SRE back,
504 tbz x0, #0, 3f // and check that it sticks
505 msr_s ICH_HCR_EL2, xzr // Reset ICC_HCR_EL2 to defaults
510 /* Populate ID registers. */
517 mov x0, #0x0800 // Set/clear RES{1,0} bits
518 CPU_BE( movk x0, #0x33d0, lsl #16 ) // Set EE and E0E on BE systems
519 CPU_LE( movk x0, #0x30d0, lsl #16 ) // Clear EE and E0E on LE systems
522 /* Coprocessor traps. */
524 msr cptr_el2, x0 // Disable copro. traps to EL2
527 msr hstr_el2, xzr // Disable CP15 traps to EL2
531 mrs x0, id_aa64dfr0_el1 // Check ID_AA64DFR0_EL1 PMUVer
534 b.lt 4f // Skip if no PMU present
535 mrs x0, pmcr_el0 // Disable debug access traps
536 ubfx x0, x0, #11, #5 // to EL2 and allow access to
537 msr mdcr_el2, x0 // all PMU counters from EL1
540 /* Stage-2 translation */
543 /* Hypervisor stub */
544 adrp x0, __hyp_stub_vectors
545 add x0, x0, #:lo12:__hyp_stub_vectors
549 mov x0, #(PSR_F_BIT | PSR_I_BIT | PSR_A_BIT | PSR_D_BIT |\
553 mov w20, #BOOT_CPU_MODE_EL2 // This CPU booted in EL2
558 * Sets the __boot_cpu_mode flag depending on the CPU boot mode passed
559 * in x20. See arch/arm64/include/asm/virt.h for more info.
561 ENTRY(set_cpu_boot_mode_flag)
562 adr_l x1, __boot_cpu_mode
563 cmp w20, #BOOT_CPU_MODE_EL2
566 1: str w20, [x1] // This CPU has booted in EL1
568 dc ivac, x1 // Invalidate potentially stale cache line
570 ENDPROC(set_cpu_boot_mode_flag)
573 * We need to find out the CPU boot mode long after boot, so we need to
574 * store it in a writable variable.
576 * This is not in .bss, because we set it sufficiently early that the boot-time
577 * zeroing of .bss would clobber it.
579 .pushsection .data..cacheline_aligned
580 .align L1_CACHE_SHIFT
581 ENTRY(__boot_cpu_mode)
582 .long BOOT_CPU_MODE_EL2
583 .long BOOT_CPU_MODE_EL1
587 * This provides a "holding pen" for platforms to hold all secondary
588 * cores are held until we're ready for them to initialise.
590 ENTRY(secondary_holding_pen)
591 bl el2_setup // Drop to EL1, w20=cpu_boot_mode
592 bl set_cpu_boot_mode_flag
594 ldr x1, =MPIDR_HWID_BITMASK
596 adr_l x3, secondary_holding_pen_release
599 b.eq secondary_startup
602 ENDPROC(secondary_holding_pen)
605 * Secondary entry point that jumps straight into the kernel. Only to
606 * be used where CPUs are brought online dynamically by the kernel.
608 ENTRY(secondary_entry)
609 bl el2_setup // Drop to EL1
610 bl set_cpu_boot_mode_flag
612 ENDPROC(secondary_entry)
614 ENTRY(secondary_startup)
616 * Common entry point for secondary CPUs.
618 adrp x25, idmap_pg_dir
619 adrp x26, swapper_pg_dir
620 bl __cpu_setup // initialise processor
622 ldr x8, =KIMAGE_VADDR
624 sub x27, x8, w9, sxtw // address to jump to after enabling the MMU
626 ENDPROC(secondary_startup)
627 0: .long (_text - TEXT_OFFSET) - __secondary_switched
629 ENTRY(__secondary_switched)
634 ldr_l x0, secondary_data // get secondary_data.stack
636 and x0, x0, #~(THREAD_SIZE - 1)
637 msr sp_el0, x0 // save thread_info
639 b secondary_start_kernel
640 ENDPROC(__secondary_switched)
645 * x0 = SCTLR_EL1 value for turning on the MMU.
646 * x27 = *virtual* address to jump to upon completion
648 * Other registers depend on the function called upon completion.
650 * Checks if the selected granule size is supported by the CPU.
651 * If it isn't, park the CPU
653 .section ".idmap.text", "ax"
655 mrs x1, ID_AA64MMFR0_EL1
656 ubfx x2, x1, #ID_AA64MMFR0_TGRAN_SHIFT, 4
657 cmp x2, #ID_AA64MMFR0_TGRAN_SUPPORTED
658 b.ne __no_granule_support
659 msr ttbr0_el1, x25 // load TTBR0
660 msr ttbr1_el1, x26 // load TTBR1
665 * Invalidate the local I-cache so that any instructions fetched
666 * speculatively from the PoC are discarded, since they may have
667 * been dynamically patched at the PoU.
673 ENDPROC(__enable_mmu)
675 __no_granule_support:
677 b __no_granule_support
678 ENDPROC(__no_granule_support)