arch/arm64/include/asm/topology.h

   1 #ifndef __ASM_TOPOLOGY_H
   2 #define __ASM_TOPOLOGY_H
   3
   4 #ifdef CONFIG_SMP
   5
   6 #include <linux/cpumask.h>
   7
   8 struct cpu_topology {
   9         int thread_id;
  10         int core_id;
  11         int cluster_id;
  12         cpumask_t thread_sibling;
  13         cpumask_t core_sibling;
  14 };
  15
  16 extern struct cpu_topology cpu_topology[NR_CPUS];
  17
  18 #define topology_physical_package_id(cpu)       (cpu_topology[cpu].cluster_id)
  19 #define topology_core_id(cpu)           (cpu_topology[cpu].core_id)
  20 #define topology_core_cpumask(cpu)      (&cpu_topology[cpu].core_sibling)
  21 #define topology_thread_cpumask(cpu)    (&cpu_topology[cpu].thread_sibling)
  22
  23 #define mc_capable()    (cpu_topology[0].cluster_id != -1)
  24 #define smt_capable()   (cpu_topology[0].thread_id != -1)
  25
  26 void init_cpu_topology(void);
  27 void store_cpu_topology(unsigned int cpuid);
  28 const struct cpumask *cpu_coregroup_mask(int cpu);
  29
  30 #ifdef CONFIG_DISABLE_CPU_SCHED_DOMAIN_BALANCE
  31 /* Common values for CPUs */
  32 #ifndef SD_CPU_INIT
  33 #define SD_CPU_INIT (struct sched_domain) {                             \
  34         .min_interval           = 1,                                    \
  35         .max_interval           = 4,                                    \
  36         .busy_factor            = 64,                                   \
  37         .imbalance_pct          = 125,                                  \
  38         .cache_nice_tries       = 1,                                    \
  39         .busy_idx               = 2,                                    \
  40         .idle_idx               = 1,                                    \
  41         .newidle_idx            = 0,                                    \
  42         .wake_idx               = 0,                                    \
  43         .forkexec_idx           = 0,                                    \
  44                                                                         \
  45         .flags                  = 0*SD_LOAD_BALANCE                     \
  46                                 | 1*SD_BALANCE_NEWIDLE                  \
  47                                 | 1*SD_BALANCE_EXEC                     \
  48                                 | 1*SD_BALANCE_FORK                     \
  49                                 | 0*SD_BALANCE_WAKE                     \
  50                                 | 1*SD_WAKE_AFFINE                      \
  51                                 | 0*SD_SHARE_CPUPOWER                   \
  52                                 | 0*SD_SHARE_PKG_RESOURCES              \
  53                                 | 0*SD_SERIALIZE                        \
  54                                 ,                                       \
  55         .last_balance            = jiffies,                             \
  56         .balance_interval       = 1,                                    \
  57 }
  58 #endif
  59 #endif /* CONFIG_DISABLE_CPU_SCHED_DOMAIN_BALANCE */
  60
  61 #else
  62
  63 static inline void init_cpu_topology(void) { }
  64 static inline void store_cpu_topology(unsigned int cpuid) { }
  65
  66 #endif
  67
  68 #include <asm-generic/topology.h>
  69
  70 #endif /* _ASM_ARM_TOPOLOGY_H */