2 * Copyright (C) 2012 ARM Ltd.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 #ifndef __ASM_SPINLOCK_H
17 #define __ASM_SPINLOCK_H
20 #include <asm/spinlock_types.h>
21 #include <asm/processor.h>
24 * Spinlock implementation.
26 * The memory barriers are implicit with the load-acquire and store-release
29 static inline void arch_spin_unlock_wait(arch_spinlock_t *lock)
32 arch_spinlock_t lockval;
38 " eor %w1, %w0, %w0, ror #16\n"
40 ARM64_LSE_ATOMIC_INSN(
42 " stxr %w1, %w0, %2\n"
43 " cbnz %w1, 2b\n", /* Serialise against any concurrent lockers */
47 : "=&r" (lockval), "=&r" (tmp), "+Q" (*lock)
52 #define arch_spin_lock_flags(lock, flags) arch_spin_lock(lock)
54 static inline void arch_spin_lock(arch_spinlock_t *lock)
57 arch_spinlock_t lockval, newval;
60 /* Atomically increment the next ticket. */
61 ARM64_LSE_ATOMIC_INSN(
63 " prfm pstl1strm, %3\n"
65 " add %w1, %w0, %w5\n"
66 " stxr %w2, %w1, %3\n"
70 " ldadda %w2, %w0, %3\n"
76 /* Did we get the lock? */
77 " eor %w1, %w0, %w0, ror #16\n"
80 * No: spin on the owner. Send a local event to avoid missing an
81 * unlock before the exclusive load.
86 " eor %w1, %w2, %w0, lsr #16\n"
88 /* We got the lock. Critical section starts here. */
90 : "=&r" (lockval), "=&r" (newval), "=&r" (tmp), "+Q" (*lock)
91 : "Q" (lock->owner), "I" (1 << TICKET_SHIFT)
95 static inline int arch_spin_trylock(arch_spinlock_t *lock)
98 arch_spinlock_t lockval;
100 asm volatile(ARM64_LSE_ATOMIC_INSN(
102 " prfm pstl1strm, %2\n"
104 " eor %w1, %w0, %w0, ror #16\n"
106 " add %w0, %w0, %3\n"
107 " stxr %w1, %w0, %2\n"
112 " eor %w1, %w0, %w0, ror #16\n"
114 " add %w1, %w0, %3\n"
115 " casa %w0, %w1, %2\n"
116 " and %w1, %w1, #0xffff\n"
117 " eor %w1, %w1, %w0, lsr #16\n"
119 : "=&r" (lockval), "=&r" (tmp), "+Q" (*lock)
120 : "I" (1 << TICKET_SHIFT)
126 static inline void arch_spin_unlock(arch_spinlock_t *lock)
130 asm volatile(ARM64_LSE_ATOMIC_INSN(
133 " add %w1, %w1, #1\n"
139 : "=Q" (lock->owner), "=&r" (tmp)
144 static inline int arch_spin_value_unlocked(arch_spinlock_t lock)
146 return lock.owner == lock.next;
149 static inline int arch_spin_is_locked(arch_spinlock_t *lock)
151 return !arch_spin_value_unlocked(READ_ONCE(*lock));
154 static inline int arch_spin_is_contended(arch_spinlock_t *lock)
156 arch_spinlock_t lockval = READ_ONCE(*lock);
157 return (lockval.next - lockval.owner) > 1;
159 #define arch_spin_is_contended arch_spin_is_contended
162 * Write lock implementation.
164 * Write locks set bit 31. Unlocking, is done by writing 0 since the lock is
167 * The memory barriers are implicit with the load-acquire and store-release
171 static inline void arch_write_lock(arch_rwlock_t *rw)
175 asm volatile(ARM64_LSE_ATOMIC_INSN(
181 " stxr %w0, %w2, %1\n"
186 "2: casa %w0, %w2, %1\n"
193 : "=&r" (tmp), "+Q" (rw->lock)
198 static inline int arch_write_trylock(arch_rwlock_t *rw)
202 asm volatile(ARM64_LSE_ATOMIC_INSN(
206 " stxr %w0, %w2, %1\n"
211 " casa %w0, %w2, %1\n"
214 : "=&r" (tmp), "+Q" (rw->lock)
221 static inline void arch_write_unlock(arch_rwlock_t *rw)
223 asm volatile(ARM64_LSE_ATOMIC_INSN(
225 " swpl wzr, wzr, %0")
226 : "=Q" (rw->lock) :: "memory");
229 /* write_can_lock - would write_trylock() succeed? */
230 #define arch_write_can_lock(x) ((x)->lock == 0)
233 * Read lock implementation.
235 * It exclusively loads the lock value, increments it and stores the new value
236 * back if positive and the CPU still exclusively owns the location. If the
237 * value is negative, the lock is already held.
239 * During unlocking there may be multiple active read locks but no write lock.
241 * The memory barriers are implicit with the load-acquire and store-release
244 * Note that in UNDEFINED cases, such as unlocking a lock twice, the LL/SC
245 * and LSE implementations may exhibit different behaviour (although this
246 * will have no effect on lockdep).
248 static inline void arch_read_lock(arch_rwlock_t *rw)
250 unsigned int tmp, tmp2;
254 ARM64_LSE_ATOMIC_INSN(
258 " add %w0, %w0, #1\n"
259 " tbnz %w0, #31, 1b\n"
260 " stxr %w1, %w0, %2\n"
266 " adds %w1, %w0, #1\n"
267 " tbnz %w1, #31, 1b\n"
268 " casa %w0, %w1, %2\n"
269 " sbc %w0, %w1, %w0\n"
271 : "=&r" (tmp), "=&r" (tmp2), "+Q" (rw->lock)
276 static inline void arch_read_unlock(arch_rwlock_t *rw)
278 unsigned int tmp, tmp2;
280 asm volatile(ARM64_LSE_ATOMIC_INSN(
283 " sub %w0, %w0, #1\n"
284 " stlxr %w1, %w0, %2\n"
291 : "=&r" (tmp), "=&r" (tmp2), "+Q" (rw->lock)
296 static inline int arch_read_trylock(arch_rwlock_t *rw)
298 unsigned int tmp, tmp2;
300 asm volatile(ARM64_LSE_ATOMIC_INSN(
304 " add %w0, %w0, #1\n"
305 " tbnz %w0, #31, 2f\n"
306 " stxr %w1, %w0, %2\n"
311 " adds %w1, %w0, #1\n"
312 " tbnz %w1, #31, 1f\n"
313 " casa %w0, %w1, %2\n"
314 " sbc %w1, %w1, %w0\n"
317 : "=&r" (tmp), "=&r" (tmp2), "+Q" (rw->lock)
324 /* read_can_lock - would read_trylock() succeed? */
325 #define arch_read_can_lock(x) ((x)->lock < 0x80000000)
327 #define arch_read_lock_flags(lock, flags) arch_read_lock(lock)
328 #define arch_write_lock_flags(lock, flags) arch_write_lock(lock)
330 #define arch_spin_relax(lock) cpu_relax()
331 #define arch_read_relax(lock) cpu_relax()
332 #define arch_write_relax(lock) cpu_relax()
335 * Accesses appearing in program order before a spin_lock() operation
336 * can be reordered with accesses inside the critical section, by virtue
337 * of arch_spin_lock being constructed using acquire semantics.
339 * In cases where this is problematic (e.g. try_to_wake_up), an
340 * smp_mb__before_spinlock() can restore the required ordering.
342 #define smp_mb__before_spinlock() smp_mb()
344 #endif /* __ASM_SPINLOCK_H */