2 * Copyright (C) 2012 ARM Ltd.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 #ifndef __ASM_CPUTYPE_H
17 #define __ASM_CPUTYPE_H
19 #define INVALID_HWID ULONG_MAX
21 #define MPIDR_UP_BITMASK (0x1 << 30)
22 #define MPIDR_MT_BITMASK (0x1 << 24)
23 #define MPIDR_HWID_BITMASK 0xff00ffffff
25 #define MPIDR_LEVEL_BITS_SHIFT 3
26 #define MPIDR_LEVEL_BITS (1 << MPIDR_LEVEL_BITS_SHIFT)
27 #define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1)
29 #define MPIDR_LEVEL_SHIFT(level) \
30 (((1 << level) >> 1) << MPIDR_LEVEL_BITS_SHIFT)
32 #define MPIDR_AFFINITY_LEVEL(mpidr, level) \
33 ((mpidr >> MPIDR_LEVEL_SHIFT(level)) & MPIDR_LEVEL_MASK)
35 #define read_cpuid(reg) ({ \
37 asm("mrs %0, " #reg : "=r" (__val)); \
41 #define MIDR_REVISION_MASK 0xf
42 #define MIDR_REVISION(midr) ((midr) & MIDR_REVISION_MASK)
43 #define MIDR_PARTNUM_SHIFT 4
44 #define MIDR_PARTNUM_MASK (0xfff << MIDR_PARTNUM_SHIFT)
45 #define MIDR_PARTNUM(midr) \
46 (((midr) & MIDR_PARTNUM_MASK) >> MIDR_PARTNUM_SHIFT)
47 #define MIDR_ARCHITECTURE_SHIFT 16
48 #define MIDR_ARCHITECTURE_MASK (0xf << MIDR_ARCHITECTURE_SHIFT)
49 #define MIDR_ARCHITECTURE(midr) \
50 (((midr) & MIDR_ARCHITECTURE_MASK) >> MIDR_ARCHITECTURE_SHIFT)
51 #define MIDR_VARIANT_SHIFT 20
52 #define MIDR_VARIANT_MASK (0xf << MIDR_VARIANT_SHIFT)
53 #define MIDR_VARIANT(midr) \
54 (((midr) & MIDR_VARIANT_MASK) >> MIDR_VARIANT_SHIFT)
55 #define MIDR_IMPLEMENTOR_SHIFT 24
56 #define MIDR_IMPLEMENTOR_MASK (0xff << MIDR_IMPLEMENTOR_SHIFT)
57 #define MIDR_IMPLEMENTOR(midr) \
58 (((midr) & MIDR_IMPLEMENTOR_MASK) >> MIDR_IMPLEMENTOR_SHIFT)
60 #define MIDR_CPU_MODEL(imp, partnum) \
61 (((imp) << MIDR_IMPLEMENTOR_SHIFT) | \
62 (0xf << MIDR_ARCHITECTURE_SHIFT) | \
63 ((partnum) << MIDR_PARTNUM_SHIFT))
65 #define MIDR_CPU_MODEL_MASK (MIDR_IMPLEMENTOR_MASK | MIDR_PARTNUM_MASK | \
66 MIDR_ARCHITECTURE_MASK)
68 #define MIDR_IS_CPU_MODEL_RANGE(midr, model, rv_min, rv_max) \
70 u32 _model = (midr) & MIDR_CPU_MODEL_MASK; \
71 u32 rv = (midr) & (MIDR_REVISION_MASK | MIDR_VARIANT_MASK); \
73 _model == (model) && rv >= (rv_min) && rv <= (rv_max); \
76 #define ARM_CPU_IMP_ARM 0x41
77 #define ARM_CPU_IMP_APM 0x50
78 #define ARM_CPU_IMP_CAVIUM 0x43
80 #define ARM_CPU_PART_AEM_V8 0xD0F
81 #define ARM_CPU_PART_FOUNDATION 0xD00
82 #define ARM_CPU_PART_CORTEX_A57 0xD07
83 #define ARM_CPU_PART_CORTEX_A53 0xD03
85 #define APM_CPU_PART_POTENZA 0x000
87 #define CAVIUM_CPU_PART_THUNDERX 0x0A1
89 #define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)
90 #define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)
91 #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
96 * The CPU ID never changes at run time, so we might as well tell the
97 * compiler that it's constant. Use this function to read the CPU ID
98 * rather than directly reading processor_id or read_cpuid() directly.
100 static inline u32 __attribute_const__ read_cpuid_id(void)
102 return read_cpuid(MIDR_EL1);
105 static inline u64 __attribute_const__ read_cpuid_mpidr(void)
107 return read_cpuid(MPIDR_EL1);
110 static inline unsigned int __attribute_const__ read_cpuid_implementor(void)
112 return MIDR_IMPLEMENTOR(read_cpuid_id());
115 static inline unsigned int __attribute_const__ read_cpuid_part_number(void)
117 return MIDR_PARTNUM(read_cpuid_id());
120 static inline u32 __attribute_const__ read_cpuid_cachetype(void)
122 return read_cpuid(CTR_EL0);
124 #endif /* __ASSEMBLY__ */