2 * Copyright (C) 2012 ARM Ltd.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 #ifndef __ASM_CPUTYPE_H
17 #define __ASM_CPUTYPE_H
19 #define ID_MIDR_EL1 "midr_el1"
20 #define ID_MPIDR_EL1 "mpidr_el1"
21 #define ID_CTR_EL0 "ctr_el0"
23 #define ID_AA64PFR0_EL1 "id_aa64pfr0_el1"
24 #define ID_AA64DFR0_EL1 "id_aa64dfr0_el1"
25 #define ID_AA64AFR0_EL1 "id_aa64afr0_el1"
26 #define ID_AA64ISAR0_EL1 "id_aa64isar0_el1"
27 #define ID_AA64MMFR0_EL1 "id_aa64mmfr0_el1"
29 #define INVALID_HWID ULONG_MAX
31 #define MPIDR_HWID_BITMASK 0xff00ffffff
33 #define read_cpuid(reg) ({ \
35 asm("mrs %0, " reg : "=r" (__val)); \
39 #define MIDR_REVISION_MASK 0xf
40 #define MIDR_REVISION(midr) ((midr) & MIDR_REVISION_MASK)
41 #define MIDR_PARTNUM_SHIFT 4
42 #define MIDR_PARTNUM_MASK (0xfff << MIDR_PARTNUM_SHIFT)
43 #define MIDR_PARTNUM(midr) \
44 (((midr) & MIDR_PARTNUM_MASK) >> MIDR_PARTNUM_SHIFT)
45 #define MIDR_ARCHITECTURE_SHIFT 16
46 #define MIDR_ARCHITECTURE_MASK (0xf << MIDR_ARCHITECTURE_SHIFT)
47 #define MIDR_ARCHITECTURE(midr) \
48 (((midr) & MIDR_ARCHITECTURE_MASK) >> MIDR_ARCHITECTURE_SHIFT)
49 #define MIDR_VARIANT_SHIFT 20
50 #define MIDR_VARIANT_MASK (0xf << MIDR_VARIANT_SHIFT)
51 #define MIDR_VARIANT(midr) \
52 (((midr) & MIDR_VARIANT_MASK) >> MIDR_VARIANT_SHIFT)
53 #define MIDR_IMPLEMENTOR_SHIFT 24
54 #define MIDR_IMPLEMENTOR_MASK (0xff << MIDR_IMPLEMENTOR_SHIFT)
55 #define MIDR_IMPLEMENTOR(midr) \
56 (((midr) & MIDR_IMPLEMENTOR_MASK) >> MIDR_IMPLEMENTOR_SHIFT)
58 #define ARM_CPU_IMP_ARM 0x41
59 #define ARM_CPU_IMP_APM 0x50
61 #define ARM_CPU_PART_AEM_V8 0xD0F
62 #define ARM_CPU_PART_FOUNDATION 0xD00
63 #define ARM_CPU_PART_CORTEX_A57 0xD07
64 #define ARM_CPU_PART_CORTEX_A53 0xD03
66 #define APM_CPU_PART_POTENZA 0x000
71 * The CPU ID never changes at run time, so we might as well tell the
72 * compiler that it's constant. Use this function to read the CPU ID
73 * rather than directly reading processor_id or read_cpuid() directly.
75 static inline u32 __attribute_const__ read_cpuid_id(void)
77 return read_cpuid(ID_MIDR_EL1);
80 static inline u64 __attribute_const__ read_cpuid_mpidr(void)
82 return read_cpuid(ID_MPIDR_EL1);
85 static inline unsigned int __attribute_const__ read_cpuid_implementor(void)
87 return MIDR_IMPLEMENTOR(read_cpuid_id());
90 static inline unsigned int __attribute_const__ read_cpuid_part_number(void)
92 return MIDR_PARTNUM(read_cpuid_id());
95 static inline u32 __attribute_const__ read_cpuid_cachetype(void)
97 return read_cpuid(ID_CTR_EL0);
100 #endif /* __ASSEMBLY__ */