2 * Based on arch/arm/include/asm/atomic.h
4 * Copyright (C) 1996 Russell King.
5 * Copyright (C) 2002 Deep Blue Solutions Ltd.
6 * Copyright (C) 2012 ARM Ltd.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 #ifndef __ASM_ATOMIC_H
21 #define __ASM_ATOMIC_H
23 #include <linux/compiler.h>
24 #include <linux/types.h>
26 #include <asm/barrier.h>
27 #include <asm/cmpxchg.h>
29 #define ATOMIC_INIT(i) { (i) }
34 * On ARM, ordinary assignment (str instruction) doesn't clear the local
35 * strex/ldrex monitor on some implementations. The reason we can use it for
36 * atomic_set() is the clrex or dummy strex done on every exception return.
38 #define atomic_read(v) (*(volatile int *)&(v)->counter)
39 #define atomic_set(v,i) (((v)->counter) = (i))
42 * AArch64 UP and SMP safe atomic ops. We use load exclusive and
43 * store exclusive to ensure that these are atomic. We may loop
44 * to ensure that the update happens.
46 static inline void atomic_add(int i, atomic_t *v)
51 asm volatile("// atomic_add\n"
53 " add %w0, %w0, %w3\n"
54 " stxr %w1, %w0, %2\n"
56 : "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
60 static inline int atomic_add_return(int i, atomic_t *v)
65 asm volatile("// atomic_add_return\n"
67 " add %w0, %w0, %w3\n"
68 " stlxr %w1, %w0, %2\n"
70 : "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
78 static inline void atomic_sub(int i, atomic_t *v)
83 asm volatile("// atomic_sub\n"
85 " sub %w0, %w0, %w3\n"
86 " stxr %w1, %w0, %2\n"
88 : "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
92 static inline int atomic_sub_return(int i, atomic_t *v)
97 asm volatile("// atomic_sub_return\n"
99 " sub %w0, %w0, %w3\n"
100 " stlxr %w1, %w0, %2\n"
102 : "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
110 static inline int atomic_cmpxchg(atomic_t *ptr, int old, int new)
117 asm volatile("// atomic_cmpxchg\n"
121 " stxr %w0, %w4, %2\n"
124 : "=&r" (tmp), "=&r" (oldval), "+Q" (ptr->counter)
125 : "Ir" (old), "r" (new)
132 static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr)
134 unsigned long tmp, tmp2;
136 asm volatile("// atomic_clear_mask\n"
139 " stxr %w1, %0, %2\n"
141 : "=&r" (tmp), "=&r" (tmp2), "+Q" (*addr)
146 #define atomic_xchg(v, new) (xchg(&((v)->counter), new))
148 static inline int __atomic_add_unless(atomic_t *v, int a, int u)
153 while (c != u && (old = atomic_cmpxchg((v), c, c + a)) != c)
158 #define atomic_inc(v) atomic_add(1, v)
159 #define atomic_dec(v) atomic_sub(1, v)
161 #define atomic_inc_and_test(v) (atomic_add_return(1, v) == 0)
162 #define atomic_dec_and_test(v) (atomic_sub_return(1, v) == 0)
163 #define atomic_inc_return(v) (atomic_add_return(1, v))
164 #define atomic_dec_return(v) (atomic_sub_return(1, v))
165 #define atomic_sub_and_test(i, v) (atomic_sub_return(i, v) == 0)
167 #define atomic_add_negative(i,v) (atomic_add_return(i, v) < 0)
169 #define smp_mb__before_atomic_dec() smp_mb()
170 #define smp_mb__after_atomic_dec() smp_mb()
171 #define smp_mb__before_atomic_inc() smp_mb()
172 #define smp_mb__after_atomic_inc() smp_mb()
175 * 64-bit atomic operations.
177 #define ATOMIC64_INIT(i) { (i) }
179 #define atomic64_read(v) (*(volatile long *)&(v)->counter)
180 #define atomic64_set(v,i) (((v)->counter) = (i))
182 static inline void atomic64_add(u64 i, atomic64_t *v)
187 asm volatile("// atomic64_add\n"
190 " stxr %w1, %0, %2\n"
192 : "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
196 static inline long atomic64_add_return(long i, atomic64_t *v)
201 asm volatile("// atomic64_add_return\n"
204 " stlxr %w1, %0, %2\n"
206 : "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
214 static inline void atomic64_sub(u64 i, atomic64_t *v)
219 asm volatile("// atomic64_sub\n"
222 " stxr %w1, %0, %2\n"
224 : "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
228 static inline long atomic64_sub_return(long i, atomic64_t *v)
233 asm volatile("// atomic64_sub_return\n"
236 " stlxr %w1, %0, %2\n"
238 : "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
246 static inline long atomic64_cmpxchg(atomic64_t *ptr, long old, long new)
253 asm volatile("// atomic64_cmpxchg\n"
257 " stxr %w0, %4, %2\n"
260 : "=&r" (res), "=&r" (oldval), "+Q" (ptr->counter)
261 : "Ir" (old), "r" (new)
268 #define atomic64_xchg(v, new) (xchg(&((v)->counter), new))
270 static inline long atomic64_dec_if_positive(atomic64_t *v)
275 asm volatile("// atomic64_dec_if_positive\n"
279 " stlxr %w1, %0, %2\n"
283 : "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
290 static inline int atomic64_add_unless(atomic64_t *v, long a, long u)
294 c = atomic64_read(v);
295 while (c != u && (old = atomic64_cmpxchg((v), c, c + a)) != c)
301 #define atomic64_add_negative(a, v) (atomic64_add_return((a), (v)) < 0)
302 #define atomic64_inc(v) atomic64_add(1LL, (v))
303 #define atomic64_inc_return(v) atomic64_add_return(1LL, (v))
304 #define atomic64_inc_and_test(v) (atomic64_inc_return(v) == 0)
305 #define atomic64_sub_and_test(a, v) (atomic64_sub_return((a), (v)) == 0)
306 #define atomic64_dec(v) atomic64_sub(1LL, (v))
307 #define atomic64_dec_return(v) atomic64_sub_return(1LL, (v))
308 #define atomic64_dec_and_test(v) (atomic64_dec_return((v)) == 0)
309 #define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1LL, 0LL)