2 * Based on arch/arm/include/asm/atomic.h
4 * Copyright (C) 1996 Russell King.
5 * Copyright (C) 2002 Deep Blue Solutions Ltd.
6 * Copyright (C) 2012 ARM Ltd.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 #ifndef __ASM_ATOMIC_H
21 #define __ASM_ATOMIC_H
23 #include <linux/compiler.h>
24 #include <linux/types.h>
26 #include <asm/barrier.h>
27 #include <asm/cmpxchg.h>
29 #define ATOMIC_INIT(i) { (i) }
34 * On ARM, ordinary assignment (str instruction) doesn't clear the local
35 * strex/ldrex monitor on some implementations. The reason we can use it for
36 * atomic_set() is the clrex or dummy strex done on every exception return.
38 #define atomic_read(v) (*(volatile int *)&(v)->counter)
39 #define atomic_set(v,i) (((v)->counter) = (i))
42 * AArch64 UP and SMP safe atomic ops. We use load exclusive and
43 * store exclusive to ensure that these are atomic. We may loop
44 * to ensure that the update happens.
46 static inline void atomic_add(int i, atomic_t *v)
51 asm volatile("// atomic_add\n"
53 " add %w0, %w0, %w3\n"
54 " stxr %w1, %w0, %2\n"
56 : "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
60 static inline int atomic_add_return(int i, atomic_t *v)
65 asm volatile("// atomic_add_return\n"
67 " add %w0, %w0, %w3\n"
68 " stlxr %w1, %w0, %2\n"
70 : "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
77 static inline void atomic_sub(int i, atomic_t *v)
82 asm volatile("// atomic_sub\n"
84 " sub %w0, %w0, %w3\n"
85 " stxr %w1, %w0, %2\n"
87 : "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
91 static inline int atomic_sub_return(int i, atomic_t *v)
96 asm volatile("// atomic_sub_return\n"
98 " sub %w0, %w0, %w3\n"
99 " stlxr %w1, %w0, %2\n"
101 : "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
108 static inline int atomic_cmpxchg(atomic_t *ptr, int old, int new)
113 asm volatile("// atomic_cmpxchg\n"
117 " stlxr %w0, %w4, %2\n"
120 : "=&r" (tmp), "=&r" (oldval), "+Q" (ptr->counter)
121 : "Ir" (old), "r" (new)
127 static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr)
129 unsigned long tmp, tmp2;
131 asm volatile("// atomic_clear_mask\n"
134 " stxr %w1, %0, %2\n"
136 : "=&r" (tmp), "=&r" (tmp2), "+Q" (*addr)
141 #define atomic_xchg(v, new) (xchg(&((v)->counter), new))
143 static inline int __atomic_add_unless(atomic_t *v, int a, int u)
148 while (c != u && (old = atomic_cmpxchg((v), c, c + a)) != c)
153 #define atomic_inc(v) atomic_add(1, v)
154 #define atomic_dec(v) atomic_sub(1, v)
156 #define atomic_inc_and_test(v) (atomic_add_return(1, v) == 0)
157 #define atomic_dec_and_test(v) (atomic_sub_return(1, v) == 0)
158 #define atomic_inc_return(v) (atomic_add_return(1, v))
159 #define atomic_dec_return(v) (atomic_sub_return(1, v))
160 #define atomic_sub_and_test(i, v) (atomic_sub_return(i, v) == 0)
162 #define atomic_add_negative(i,v) (atomic_add_return(i, v) < 0)
164 #define smp_mb__before_atomic_dec() smp_mb()
165 #define smp_mb__after_atomic_dec() smp_mb()
166 #define smp_mb__before_atomic_inc() smp_mb()
167 #define smp_mb__after_atomic_inc() smp_mb()
170 * 64-bit atomic operations.
172 #define ATOMIC64_INIT(i) { (i) }
174 #define atomic64_read(v) (*(volatile long *)&(v)->counter)
175 #define atomic64_set(v,i) (((v)->counter) = (i))
177 static inline void atomic64_add(u64 i, atomic64_t *v)
182 asm volatile("// atomic64_add\n"
185 " stxr %w1, %0, %2\n"
187 : "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
191 static inline long atomic64_add_return(long i, atomic64_t *v)
196 asm volatile("// atomic64_add_return\n"
199 " stlxr %w1, %0, %2\n"
201 : "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
208 static inline void atomic64_sub(u64 i, atomic64_t *v)
213 asm volatile("// atomic64_sub\n"
216 " stxr %w1, %0, %2\n"
218 : "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
222 static inline long atomic64_sub_return(long i, atomic64_t *v)
227 asm volatile("// atomic64_sub_return\n"
230 " stlxr %w1, %0, %2\n"
232 : "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
239 static inline long atomic64_cmpxchg(atomic64_t *ptr, long old, long new)
244 asm volatile("// atomic64_cmpxchg\n"
248 " stlxr %w0, %4, %2\n"
251 : "=&r" (res), "=&r" (oldval), "+Q" (ptr->counter)
252 : "Ir" (old), "r" (new)
258 #define atomic64_xchg(v, new) (xchg(&((v)->counter), new))
260 static inline long atomic64_dec_if_positive(atomic64_t *v)
265 asm volatile("// atomic64_dec_if_positive\n"
269 " stlxr %w1, %0, %2\n"
272 : "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
279 static inline int atomic64_add_unless(atomic64_t *v, long a, long u)
283 c = atomic64_read(v);
284 while (c != u && (old = atomic64_cmpxchg((v), c, c + a)) != c)
290 #define atomic64_add_negative(a, v) (atomic64_add_return((a), (v)) < 0)
291 #define atomic64_inc(v) atomic64_add(1LL, (v))
292 #define atomic64_inc_return(v) atomic64_add_return(1LL, (v))
293 #define atomic64_inc_and_test(v) (atomic64_inc_return(v) == 0)
294 #define atomic64_sub_and_test(a, v) (atomic64_sub_return((a), (v)) == 0)
295 #define atomic64_dec(v) atomic64_sub(1LL, (v))
296 #define atomic64_dec_return(v) atomic64_sub_return(1LL, (v))
297 #define atomic64_dec_and_test(v) (atomic64_dec_return((v)) == 0)
298 #define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1LL, 0LL)