2 * Based on arch/arm/include/asm/assembler.h, arch/arm/mm/proc-macros.S
4 * Copyright (C) 1996-2000 Russell King
5 * Copyright (C) 2012 ARM Ltd.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 #error "Only include this from assembly code"
23 #ifndef __ASM_ASSEMBLER_H
24 #define __ASM_ASSEMBLER_H
26 #include <asm/asm-offsets.h>
28 #include <asm/pgtable-hwdef.h>
29 #include <asm/ptrace.h>
30 #include <asm/thread_info.h>
33 * Stack pushing/popping (register pairs only). Equivalent to store decrement
34 * before, load increment after.
36 .macro push, xreg1, xreg2
37 stp \xreg1, \xreg2, [sp, #-16]!
40 .macro pop, xreg1, xreg2
41 ldp \xreg1, \xreg2, [sp], #16
45 * Enable and disable interrupts.
56 * Enable and disable debug exceptions.
66 .macro disable_step_tsk, flgs, tmp
67 tbz \flgs, #TIF_SINGLESTEP, 9990f
71 isb // Synchronise with enable_dbg
75 .macro enable_step_tsk, flgs, tmp
76 tbz \flgs, #TIF_SINGLESTEP, 9990f
85 * Enable both debug exceptions and interrupts. This is likely to be
86 * faster than two daifclr operations, since writes to this register
87 * are self-synchronising.
89 .macro enable_dbg_and_irq
94 * SMP data memory barrier
101 * Emit an entry into the exception table
103 .macro _asm_extable, from, to
104 .pushsection __ex_table, "a"
106 .long (\from - .), (\to - .)
110 #define USER(l, x...) \
112 _asm_extable 9999b, l
117 lr .req x30 // link register
128 * Select code when configured for BE.
130 #ifdef CONFIG_CPU_BIG_ENDIAN
131 #define CPU_BE(code...) code
133 #define CPU_BE(code...)
137 * Select code when configured for LE.
139 #ifdef CONFIG_CPU_BIG_ENDIAN
140 #define CPU_LE(code...)
142 #define CPU_LE(code...) code
146 * Define a macro that constructs a 64-bit value by concatenating two
147 * 32-bit registers. Note that on big endian systems the order of the
148 * registers is swapped.
150 #ifndef CONFIG_CPU_BIG_ENDIAN
151 .macro regs_to_64, rd, lbits, hbits
153 .macro regs_to_64, rd, hbits, lbits
155 orr \rd, \lbits, \hbits, lsl #32
159 * Pseudo-ops for PC-relative adr/ldr/str <reg>, <symbol> where
160 * <symbol> is within the range +/- 4 GB of the PC.
163 * @dst: destination register (64 bit wide)
164 * @sym: name of the symbol
165 * @tmp: optional scratch register to be used if <dst> == sp, which
166 * is not allowed in an adrp instruction
168 .macro adr_l, dst, sym, tmp=
171 add \dst, \dst, :lo12:\sym
174 add \dst, \tmp, :lo12:\sym
179 * @dst: destination register (32 or 64 bit wide)
180 * @sym: name of the symbol
181 * @tmp: optional 64-bit scratch register to be used if <dst> is a
182 * 32-bit wide register, in which case it cannot be used to hold
185 .macro ldr_l, dst, sym, tmp=
188 ldr \dst, [\dst, :lo12:\sym]
191 ldr \dst, [\tmp, :lo12:\sym]
196 * @src: source register (32 or 64 bit wide)
197 * @sym: name of the symbol
198 * @tmp: mandatory 64-bit scratch register to calculate the address
199 * while <src> needs to be preserved.
201 .macro str_l, src, sym, tmp
203 str \src, [\tmp, :lo12:\sym]
207 * @sym: The name of the per-cpu variable
208 * @reg: Result of per_cpu(sym, smp_processor_id())
209 * @tmp: scratch register
211 .macro this_cpu_ptr, sym, reg, tmp
218 * vma_vm_mm - get mm pointer from vma pointer (vma->vm_mm)
220 .macro vma_vm_mm, rd, rn
221 ldr \rd, [\rn, #VMA_VM_MM]
225 * mmid - get context id from mm pointer (mm->context.id)
228 ldr \rd, [\rn, #MM_CONTEXT_ID]
232 * dcache_line_size - get the minimum D-cache line size from the CTR register.
234 .macro dcache_line_size, reg, tmp
235 mrs \tmp, ctr_el0 // read CTR
236 ubfm \tmp, \tmp, #16, #19 // cache line size encoding
237 mov \reg, #4 // bytes per word
238 lsl \reg, \reg, \tmp // actual cache line size
242 * icache_line_size - get the minimum I-cache line size from the CTR register.
244 .macro icache_line_size, reg, tmp
245 mrs \tmp, ctr_el0 // read CTR
246 and \tmp, \tmp, #0xf // cache line size encoding
247 mov \reg, #4 // bytes per word
248 lsl \reg, \reg, \tmp // actual cache line size
252 * tcr_set_idmap_t0sz - update TCR.T0SZ so that we can load the ID map
254 .macro tcr_set_idmap_t0sz, valreg, tmpreg
255 #ifndef CONFIG_ARM64_VA_BITS_48
256 ldr_l \tmpreg, idmap_t0sz
257 bfi \valreg, \tmpreg, #TCR_T0SZ_OFFSET, #TCR_TxSZ_WIDTH
262 * Macro to perform a data cache maintenance for the interval
263 * [kaddr, kaddr + size)
265 * op: operation passed to dc instruction
266 * domain: domain used in dsb instruciton
267 * kaddr: starting virtual address of the region
268 * size: size of the region
269 * Corrupts: kaddr, size, tmp1, tmp2
271 .macro dcache_by_line_op op, domain, kaddr, size, tmp1, tmp2
272 dcache_line_size \tmp1, \tmp2
273 add \size, \kaddr, \size
275 bic \kaddr, \kaddr, \tmp2
277 add \kaddr, \kaddr, \tmp1
284 * reset_pmuserenr_el0 - reset PMUSERENR_EL0 if PMUv3 present
286 .macro reset_pmuserenr_el0, tmpreg
287 mrs \tmpreg, id_aa64dfr0_el1 // Check ID_AA64DFR0_EL1 PMUVer
288 sbfx \tmpreg, \tmpreg, #8, #4
289 cmp \tmpreg, #1 // Skip if no PMU present
291 msr pmuserenr_el0, xzr // Disable PMU access from EL0
296 * copy_page - copy src to dest using temp registers t1-t8
298 .macro copy_page dest:req src:req t1:req t2:req t3:req t4:req t5:req t6:req t7:req t8:req
299 9998: ldp \t1, \t2, [\src]
300 ldp \t3, \t4, [\src, #16]
301 ldp \t5, \t6, [\src, #32]
302 ldp \t7, \t8, [\src, #48]
304 stnp \t1, \t2, [\dest]
305 stnp \t3, \t4, [\dest, #16]
306 stnp \t5, \t6, [\dest, #32]
307 stnp \t7, \t8, [\dest, #48]
308 add \dest, \dest, #64
309 tst \src, #(PAGE_SIZE - 1)
314 * Annotate a function as position independent, i.e., safe to be called before
315 * the kernel virtual mapping is activated.
317 #define ENDPIPROC(x) \
319 .type __pi_##x, %function; \
321 .size __pi_##x, . - x; \
325 * Emit a 64-bit absolute little endian symbol reference in a way that
326 * ensures that it will be resolved at build time, even when building a
327 * PIE binary. This requires cooperation from the linker script, which
328 * must emit the lo32/hi32 halves individually.
336 * mov_q - move an immediate constant into a 64-bit register using
337 * between 2 and 4 movz/movk instructions (depending on the
338 * magnitude and sign of the operand)
340 .macro mov_q, reg, val
341 .if (((\val) >> 31) == 0 || ((\val) >> 31) == 0x1ffffffff)
342 movz \reg, :abs_g1_s:\val
344 .if (((\val) >> 47) == 0 || ((\val) >> 47) == 0x1ffff)
345 movz \reg, :abs_g2_s:\val
347 movz \reg, :abs_g3:\val
348 movk \reg, :abs_g2_nc:\val
350 movk \reg, :abs_g1_nc:\val
352 movk \reg, :abs_g0_nc:\val
355 #endif /* __ASM_ASSEMBLER_H */