2 * Based on arch/arm/include/asm/assembler.h
4 * Copyright (C) 1996-2000 Russell King
5 * Copyright (C) 2012 ARM Ltd.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 #error "Only include this from assembly code"
23 #ifndef __ASM_ASSEMBLER_H
24 #define __ASM_ASSEMBLER_H
26 #include <asm/ptrace.h>
27 #include <asm/thread_info.h>
30 * Stack pushing/popping (register pairs only). Equivalent to store decrement
31 * before, load increment after.
33 .macro push, xreg1, xreg2
34 stp \xreg1, \xreg2, [sp, #-16]!
37 .macro pop, xreg1, xreg2
38 ldp \xreg1, \xreg2, [sp], #16
42 * Enable and disable interrupts.
53 * Enable and disable debug exceptions.
63 .macro disable_step_tsk, flgs, tmp
64 tbz \flgs, #TIF_SINGLESTEP, 9990f
68 isb // Synchronise with enable_dbg
72 .macro enable_step_tsk, flgs, tmp
73 tbz \flgs, #TIF_SINGLESTEP, 9990f
82 * Enable both debug exceptions and interrupts. This is likely to be
83 * faster than two daifclr operations, since writes to this register
84 * are self-synchronising.
86 .macro enable_dbg_and_irq
91 * SMP data memory barrier
98 * Emit an entry into the exception table
100 .macro _asm_extable, from, to
101 .pushsection __ex_table, "a"
103 .long (\from - .), (\to - .)
107 #define USER(l, x...) \
109 _asm_extable 9999b, l
114 lr .req x30 // link register
125 * Select code when configured for BE.
127 #ifdef CONFIG_CPU_BIG_ENDIAN
128 #define CPU_BE(code...) code
130 #define CPU_BE(code...)
134 * Select code when configured for LE.
136 #ifdef CONFIG_CPU_BIG_ENDIAN
137 #define CPU_LE(code...)
139 #define CPU_LE(code...) code
143 * Define a macro that constructs a 64-bit value by concatenating two
144 * 32-bit registers. Note that on big endian systems the order of the
145 * registers is swapped.
147 #ifndef CONFIG_CPU_BIG_ENDIAN
148 .macro regs_to_64, rd, lbits, hbits
150 .macro regs_to_64, rd, hbits, lbits
152 orr \rd, \lbits, \hbits, lsl #32
156 * Pseudo-ops for PC-relative adr/ldr/str <reg>, <symbol> where
157 * <symbol> is within the range +/- 4 GB of the PC.
160 * @dst: destination register (64 bit wide)
161 * @sym: name of the symbol
162 * @tmp: optional scratch register to be used if <dst> == sp, which
163 * is not allowed in an adrp instruction
165 .macro adr_l, dst, sym, tmp=
168 add \dst, \dst, :lo12:\sym
171 add \dst, \tmp, :lo12:\sym
176 * @dst: destination register (32 or 64 bit wide)
177 * @sym: name of the symbol
178 * @tmp: optional 64-bit scratch register to be used if <dst> is a
179 * 32-bit wide register, in which case it cannot be used to hold
182 .macro ldr_l, dst, sym, tmp=
185 ldr \dst, [\dst, :lo12:\sym]
188 ldr \dst, [\tmp, :lo12:\sym]
193 * @src: source register (32 or 64 bit wide)
194 * @sym: name of the symbol
195 * @tmp: mandatory 64-bit scratch register to calculate the address
196 * while <src> needs to be preserved.
198 .macro str_l, src, sym, tmp
200 str \src, [\tmp, :lo12:\sym]
204 * @sym: The name of the per-cpu variable
205 * @reg: Result of per_cpu(sym, smp_processor_id())
206 * @tmp: scratch register
208 .macro this_cpu_ptr, sym, reg, tmp
215 * Annotate a function as position independent, i.e., safe to be called before
216 * the kernel virtual mapping is activated.
218 #define ENDPIPROC(x) \
220 .type __pi_##x, %function; \
222 .size __pi_##x, . - x; \
226 * Emit a 64-bit absolute little endian symbol reference in a way that
227 * ensures that it will be resolved at build time, even when building a
228 * PIE binary. This requires cooperation from the linker script, which
229 * must emit the lo32/hi32 halves individually.
237 * mov_q - move an immediate constant into a 64-bit register using
238 * between 2 and 4 movz/movk instructions (depending on the
239 * magnitude and sign of the operand)
241 .macro mov_q, reg, val
242 .if (((\val) >> 31) == 0 || ((\val) >> 31) == 0x1ffffffff)
243 movz \reg, :abs_g1_s:\val
245 .if (((\val) >> 47) == 0 || ((\val) >> 47) == 0x1ffff)
246 movz \reg, :abs_g2_s:\val
248 movz \reg, :abs_g3:\val
249 movk \reg, :abs_g2_nc:\val
251 movk \reg, :abs_g1_nc:\val
253 movk \reg, :abs_g0_nc:\val
256 #endif /* __ASM_ASSEMBLER_H */