2 * Based on arch/arm/include/asm/assembler.h
4 * Copyright (C) 1996-2000 Russell King
5 * Copyright (C) 2012 ARM Ltd.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 #error "Only include this from assembly code"
23 #ifndef __ASM_ASSEMBLER_H
24 #define __ASM_ASSEMBLER_H
26 #include <asm/ptrace.h>
27 #include <asm/thread_info.h>
30 * Stack pushing/popping (register pairs only). Equivalent to store decrement
31 * before, load increment after.
33 .macro push, xreg1, xreg2
34 stp \xreg1, \xreg2, [sp, #-16]!
37 .macro pop, xreg1, xreg2
38 ldp \xreg1, \xreg2, [sp], #16
42 * Enable and disable interrupts.
53 * Enable and disable debug exceptions.
63 .macro disable_step_tsk, flgs, tmp
64 tbz \flgs, #TIF_SINGLESTEP, 9990f
68 isb // Synchronise with enable_dbg
72 .macro enable_step_tsk, flgs, tmp
73 tbz \flgs, #TIF_SINGLESTEP, 9990f
82 * Enable both debug exceptions and interrupts. This is likely to be
83 * faster than two daifclr operations, since writes to this register
84 * are self-synchronising.
86 .macro enable_dbg_and_irq
91 * SMP data memory barrier
99 #define USER(l, x...) \
101 .section __ex_table,"a"; \
109 lr .req x30 // link register
120 * Select code when configured for BE.
122 #ifdef CONFIG_CPU_BIG_ENDIAN
123 #define CPU_BE(code...) code
125 #define CPU_BE(code...)
129 * Select code when configured for LE.
131 #ifdef CONFIG_CPU_BIG_ENDIAN
132 #define CPU_LE(code...)
134 #define CPU_LE(code...) code
138 * Define a macro that constructs a 64-bit value by concatenating two
139 * 32-bit registers. Note that on big endian systems the order of the
140 * registers is swapped.
142 #ifndef CONFIG_CPU_BIG_ENDIAN
143 .macro regs_to_64, rd, lbits, hbits
145 .macro regs_to_64, rd, hbits, lbits
147 orr \rd, \lbits, \hbits, lsl #32
151 * Pseudo-ops for PC-relative adr/ldr/str <reg>, <symbol> where
152 * <symbol> is within the range +/- 4 GB of the PC.
155 * @dst: destination register (64 bit wide)
156 * @sym: name of the symbol
157 * @tmp: optional scratch register to be used if <dst> == sp, which
158 * is not allowed in an adrp instruction
160 .macro adr_l, dst, sym, tmp=
163 add \dst, \dst, :lo12:\sym
166 add \dst, \tmp, :lo12:\sym
171 * @dst: destination register (32 or 64 bit wide)
172 * @sym: name of the symbol
173 * @tmp: optional 64-bit scratch register to be used if <dst> is a
174 * 32-bit wide register, in which case it cannot be used to hold
177 .macro ldr_l, dst, sym, tmp=
180 ldr \dst, [\dst, :lo12:\sym]
183 ldr \dst, [\tmp, :lo12:\sym]
188 * @src: source register (32 or 64 bit wide)
189 * @sym: name of the symbol
190 * @tmp: mandatory 64-bit scratch register to calculate the address
191 * while <src> needs to be preserved.
193 .macro str_l, src, sym, tmp
195 str \src, [\tmp, :lo12:\sym]
198 #endif /* __ASM_ASSEMBLER_H */