2 * Based on arch/arm/include/asm/assembler.h
4 * Copyright (C) 1996-2000 Russell King
5 * Copyright (C) 2012 ARM Ltd.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 #error "Only include this from assembly code"
23 #include <asm/ptrace.h>
24 #include <asm/thread_info.h>
27 * Stack pushing/popping (register pairs only). Equivalent to store decrement
28 * before, load increment after.
30 .macro push, xreg1, xreg2
31 stp \xreg1, \xreg2, [sp, #-16]!
34 .macro pop, xreg1, xreg2
35 ldp \xreg1, \xreg2, [sp], #16
39 * Enable and disable interrupts.
50 * Save/disable and restore interrupts.
52 .macro save_and_disable_irqs, olddaif
57 .macro restore_irqs, olddaif
62 * Enable and disable debug exceptions.
72 .macro disable_step_tsk, flgs, tmp
73 tbz \flgs, #TIF_SINGLESTEP, 9990f
77 isb // Synchronise with enable_dbg
81 .macro enable_step_tsk, flgs, tmp
82 tbz \flgs, #TIF_SINGLESTEP, 9990f
91 * Enable both debug exceptions and interrupts. This is likely to be
92 * faster than two daifclr operations, since writes to this register
93 * are self-synchronising.
95 .macro enable_dbg_and_irq
100 * SMP data memory barrier
108 #define USER(l, x...) \
110 .section __ex_table,"a"; \
118 lr .req x30 // link register
129 * Select code when configured for BE.
131 #ifdef CONFIG_CPU_BIG_ENDIAN
132 #define CPU_BE(code...) code
134 #define CPU_BE(code...)
138 * Select code when configured for LE.
140 #ifdef CONFIG_CPU_BIG_ENDIAN
141 #define CPU_LE(code...)
143 #define CPU_LE(code...) code
147 * Define a macro that constructs a 64-bit value by concatenating two
148 * 32-bit registers. Note that on big endian systems the order of the
149 * registers is swapped.
151 #ifndef CONFIG_CPU_BIG_ENDIAN
152 .macro regs_to_64, rd, lbits, hbits
154 .macro regs_to_64, rd, hbits, lbits
156 orr \rd, \lbits, \hbits, lsl #32