arch/arm64/boot/dts/rockchip/rk3399.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3399-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/interrupt-controller/irq.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/power/rk3399-power.h>
  49 #include <dt-bindings/soc/rockchip_boot-mode.h>
  50 #include <dt-bindings/thermal/thermal.h>
  51
  52 #include "rk3399-dram-default-timing.dtsi"
  53
  54 / {
  55         compatible = "rockchip,rk3399";
  56
  57         interrupt-parent = <&gic>;
  58         #address-cells = <2>;
  59         #size-cells = <2>;
  60
  61         aliases {
  62                 i2c0 = &i2c0;
  63                 i2c1 = &i2c1;
  64                 i2c2 = &i2c2;
  65                 i2c3 = &i2c3;
  66                 i2c4 = &i2c4;
  67                 i2c5 = &i2c5;
  68                 i2c6 = &i2c6;
  69                 i2c7 = &i2c7;
  70                 i2c8 = &i2c8;
  71                 serial0 = &uart0;
  72                 serial1 = &uart1;
  73                 serial2 = &uart2;
  74                 serial3 = &uart3;
  75                 serial4 = &uart4;
  76         };
  77
  78         psci {
  79                 compatible = "arm,psci-1.0";
  80                 method = "smc";
  81         };
  82
  83         cpus {
  84                 #address-cells = <2>;
  85                 #size-cells = <0>;
  86
  87                 cpu-map {
  88                         cluster0 {
  89                                 core0 {
  90                                         cpu = <&cpu_l0>;
  91                                 };
  92                                 core1 {
  93                                         cpu = <&cpu_l1>;
  94                                 };
  95                                 core2 {
  96                                         cpu = <&cpu_l2>;
  97                                 };
  98                                 core3 {
  99                                         cpu = <&cpu_l3>;
 100                                 };
 101                         };
 102
 103                         cluster1 {
 104                                 core0 {
 105                                         cpu = <&cpu_b0>;
 106                                 };
 107                                 core1 {
 108                                         cpu = <&cpu_b1>;
 109                                 };
 110                         };
 111                 };
 112
 113                 cpu_l0: cpu@0 {
 114                         device_type = "cpu";
 115                         compatible = "arm,cortex-a53", "arm,armv8";
 116                         reg = <0x0 0x0>;
 117                         enable-method = "psci";
 118                         #cooling-cells = <2>; /* min followed by max */
 119                         dynamic-power-coefficient = <100>;
 120                         clocks = <&cru ARMCLKL>;
 121                         cpu-idle-states = <&cpu_sleep>;
 122                         operating-points-v2 = <&cluster0_opp>;
 123                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
 124                 };
 125
 126                 cpu_l1: cpu@1 {
 127                         device_type = "cpu";
 128                         compatible = "arm,cortex-a53", "arm,armv8";
 129                         reg = <0x0 0x1>;
 130                         enable-method = "psci";
 131                         clocks = <&cru ARMCLKL>;
 132                         cpu-idle-states = <&cpu_sleep>;
 133                         operating-points-v2 = <&cluster0_opp>;
 134                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
 135                 };
 136
 137                 cpu_l2: cpu@2 {
 138                         device_type = "cpu";
 139                         compatible = "arm,cortex-a53", "arm,armv8";
 140                         reg = <0x0 0x2>;
 141                         enable-method = "psci";
 142                         clocks = <&cru ARMCLKL>;
 143                         cpu-idle-states = <&cpu_sleep>;
 144                         operating-points-v2 = <&cluster0_opp>;
 145                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
 146                 };
 147
 148                 cpu_l3: cpu@3 {
 149                         device_type = "cpu";
 150                         compatible = "arm,cortex-a53", "arm,armv8";
 151                         reg = <0x0 0x3>;
 152                         enable-method = "psci";
 153                         clocks = <&cru ARMCLKL>;
 154                         cpu-idle-states = <&cpu_sleep>;
 155                         operating-points-v2 = <&cluster0_opp>;
 156                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
 157                 };
 158
 159                 cpu_b0: cpu@100 {
 160                         device_type = "cpu";
 161                         compatible = "arm,cortex-a72", "arm,armv8";
 162                         reg = <0x0 0x100>;
 163                         enable-method = "psci";
 164                         #cooling-cells = <2>; /* min followed by max */
 165                         dynamic-power-coefficient = <436>;
 166                         clocks = <&cru ARMCLKB>;
 167                         cpu-idle-states = <&cpu_sleep>;
 168                         operating-points-v2 = <&cluster1_opp>;
 169                         sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>;
 170                 };
 171
 172                 cpu_b1: cpu@101 {
 173                         device_type = "cpu";
 174                         compatible = "arm,cortex-a72", "arm,armv8";
 175                         reg = <0x0 0x101>;
 176                         enable-method = "psci";
 177                         clocks = <&cru ARMCLKB>;
 178                         cpu-idle-states = <&cpu_sleep>;
 179                         operating-points-v2 = <&cluster1_opp>;
 180                         sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>;
 181                 };
 182
 183                 idle-states {
 184                         entry-method = "psci";
 185                         cpu_sleep: cpu-sleep-0 {
 186                                 compatible = "arm,idle-state";
 187                                 local-timer-stop;
 188                                 arm,psci-suspend-param = <0x0010000>;
 189                                 entry-latency-us = <350>;
 190                                 exit-latency-us = <600>;
 191                                 min-residency-us = <1150>;
 192                         };
 193                 };
 194
 195                 /include/ "rk3399-sched-energy.dtsi"
 196
 197         };
 198
 199         cluster0_opp: opp_table0 {
 200                 compatible = "operating-points-v2";
 201                 opp-shared;
 202
 203                 opp@408000000 {
 204                         opp-hz = /bits/ 64 <408000000>;
 205                         opp-microvolt = <800000>;
 206                         clock-latency-ns = <40000>;
 207                 };
 208                 opp@600000000 {
 209                         opp-hz = /bits/ 64 <600000000>;
 210                         opp-microvolt = <800000>;
 211                 };
 212                 opp@816000000 {
 213                         opp-hz = /bits/ 64 <816000000>;
 214                         opp-microvolt = <800000>;
 215                 };
 216                 opp@1008000000 {
 217                         opp-hz = /bits/ 64 <1008000000>;
 218                         opp-microvolt = <875000>;
 219                 };
 220                 opp@1200000000 {
 221                         opp-hz = /bits/ 64 <1200000000>;
 222                         opp-microvolt = <925000>;
 223                 };
 224                 opp@1416000000 {
 225                         opp-hz = /bits/ 64 <1416000000>;
 226                         opp-microvolt = <1025000>;
 227                 };
 228         };
 229
 230         cluster1_opp: opp_table1 {
 231                 compatible = "operating-points-v2";
 232                 opp-shared;
 233
 234                 opp@408000000 {
 235                         opp-hz = /bits/ 64 <408000000>;
 236                         opp-microvolt = <800000>;
 237                         clock-latency-ns = <40000>;
 238                 };
 239                 opp@600000000 {
 240                         opp-hz = /bits/ 64 <600000000>;
 241                         opp-microvolt = <800000>;
 242                 };
 243                 opp@816000000 {
 244                         opp-hz = /bits/ 64 <816000000>;
 245                         opp-microvolt = <800000>;
 246                 };
 247                 opp@1008000000 {
 248                         opp-hz = /bits/ 64 <1008000000>;
 249                         opp-microvolt = <850000>;
 250                 };
 251                 opp@1200000000 {
 252                         opp-hz = /bits/ 64 <1200000000>;
 253                         opp-microvolt = <925000>;
 254                 };
 255         };
 256
 257         timer {
 258                 compatible = "arm,armv8-timer";
 259                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
 260                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
 261                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
 262                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
 263         };
 264
 265         pmu_a53 {
 266                 compatible = "arm,cortex-a53-pmu";
 267                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &part0>;
 268         };
 269
 270         pmu_a72 {
 271                 compatible = "arm,cortex-a72-pmu";
 272                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &part1>;
 273         };
 274
 275         xin24m: xin24m {
 276                 compatible = "fixed-clock";
 277                 #clock-cells = <0>;
 278                 clock-frequency = <24000000>;
 279                 clock-output-names = "xin24m";
 280         };
 281
 282         amba {
 283                 compatible = "arm,amba-bus";
 284                 #address-cells = <2>;
 285                 #size-cells = <2>;
 286                 ranges;
 287
 288                 dmac_bus: dma-controller@ff6d0000 {
 289                         compatible = "arm,pl330", "arm,primecell";
 290                         reg = <0x0 0xff6d0000 0x0 0x4000>;
 291                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
 292                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
 293                         #dma-cells = <1>;
 294                         clocks = <&cru ACLK_DMAC0_PERILP>;
 295                         clock-names = "apb_pclk";
 296                         peripherals-req-type-burst;
 297                 };
 298
 299                 dmac_peri: dma-controller@ff6e0000 {
 300                         compatible = "arm,pl330", "arm,primecell";
 301                         reg = <0x0 0xff6e0000 0x0 0x4000>;
 302                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
 303                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>;
 304                         #dma-cells = <1>;
 305                         clocks = <&cru ACLK_DMAC1_PERILP>;
 306                         clock-names = "apb_pclk";
 307                         peripherals-req-type-burst;
 308                 };
 309         };
 310
 311         gmac: eth@fe300000 {
 312                 compatible = "rockchip,rk3399-gmac";
 313                 reg = <0x0 0xfe300000 0x0 0x10000>;
 314                 rockchip,grf = <&grf>;
 315                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
 316                 interrupt-names = "macirq";
 317                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
 318                          <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
 319                          <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
 320                          <&cru PCLK_GMAC>;
 321                 clock-names = "stmmaceth", "mac_clk_rx",
 322                               "mac_clk_tx", "clk_mac_ref",
 323                               "clk_mac_refout", "aclk_mac",
 324                               "pclk_mac";
 325                 resets = <&cru SRST_A_GMAC>;
 326                 reset-names = "stmmaceth";
 327                 power-domains = <&power RK3399_PD_GMAC>;
 328                 status = "disabled";
 329         };
 330
 331         emmc_phy: phy {
 332                 compatible = "rockchip,rk3399-emmc-phy";
 333                 reg-offset = <0xf780>;
 334                 #phy-cells = <0>;
 335                 rockchip,grf = <&grf>;
 336                 ctrl-base = <0xfe330000>;
 337                 status = "disabled";
 338         };
 339
 340         sdio0: dwmmc@fe310000 {
 341                 compatible = "rockchip,rk3399-dw-mshc",
 342                              "rockchip,rk3288-dw-mshc";
 343                 reg = <0x0 0xfe310000 0x0 0x4000>;
 344                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>;
 345                 clock-freq-min-max = <400000 150000000>;
 346                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 347                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 348                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 349                 fifo-depth = <0x100>;
 350                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
 351                 status = "disabled";
 352         };
 353
 354         sdmmc: dwmmc@fe320000 {
 355                 compatible = "rockchip,rk3399-dw-mshc",
 356                              "rockchip,rk3288-dw-mshc";
 357                 reg = <0x0 0xfe320000 0x0 0x4000>;
 358                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
 359                 clock-freq-min-max = <400000 150000000>;
 360                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 361                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 362                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 363                 fifo-depth = <0x100>;
 364                 power-domains = <&power RK3399_PD_SD>;
 365                 status = "disabled";
 366         };
 367
 368         sdhci: sdhci@fe330000 {
 369                 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
 370                 reg = <0x0 0xfe330000 0x0 0x10000>;
 371                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
 372                 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
 373                 clock-names = "clk_xin", "clk_ahb";
 374                 assigned-clocks = <&cru SCLK_EMMC>;
 375                 assigned-clock-parents = <&cru PLL_CPLL>;
 376                 assigned-clock-rates = <200000000>;
 377                 phys = <&emmc_phy>;
 378                 phy-names = "phy_arasan";
 379                 power-domains = <&power RK3399_PD_EMMC>;
 380                 status = "disabled";
 381         };
 382
 383         usb_host0_ehci: usb@fe380000 {
 384                 compatible = "generic-ehci";
 385                 reg = <0x0 0xfe380000 0x0 0x20000>;
 386                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
 387                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 388                          <&cru SCLK_USBPHY0_480M_SRC>;
 389                 clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m";
 390                 phys = <&u2phy0_host>;
 391                 phy-names = "usb";
 392                 power-domains = <&power RK3399_PD_PERIHP>;
 393                 status = "disabled";
 394         };
 395
 396         usb_host0_ohci: usb@fe3a0000 {
 397                 compatible = "generic-ohci";
 398                 reg = <0x0 0xfe3a0000 0x0 0x20000>;
 399                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
 400                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 401                          <&cru SCLK_USBPHY0_480M_SRC>;
 402                 clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m";
 403                 phys = <&u2phy0_host>;
 404                 phy-names = "usb";
 405                 power-domains = <&power RK3399_PD_PERIHP>;
 406                 status = "disabled";
 407         };
 408
 409         usb_host1_ehci: usb@fe3c0000 {
 410                 compatible = "generic-ehci";
 411                 reg = <0x0 0xfe3c0000 0x0 0x20000>;
 412                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
 413                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
 414                          <&cru SCLK_USBPHY1_480M_SRC>;
 415                 clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m";
 416                 phys = <&u2phy1_host>;
 417                 phy-names = "usb";
 418                 power-domains = <&power RK3399_PD_PERIHP>;
 419                 status = "disabled";
 420         };
 421
 422         usb_host1_ohci: usb@fe3e0000 {
 423                 compatible = "generic-ohci";
 424                 reg = <0x0 0xfe3e0000 0x0 0x20000>;
 425                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
 426                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
 427                          <&cru SCLK_USBPHY1_480M_SRC>;
 428                 clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m";
 429                 phys = <&u2phy1_host>;
 430                 phy-names = "usb";
 431                 power-domains = <&power RK3399_PD_PERIHP>;
 432                 status = "disabled";
 433         };
 434
 435         usbdrd3_0: usb@fe800000 {
 436                 compatible = "rockchip,rk3399-dwc3";
 437                 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
 438                          <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_GRF>;
 439                 clock-names = "ref_clk", "suspend_clk",
 440                               "bus_clk", "grf_clk";
 441                 power-domains = <&power RK3399_PD_USB3>;
 442                 resets = <&cru SRST_A_USB3_OTG0>;
 443                 reset-names = "usb3-otg";
 444                 #address-cells = <2>;
 445                 #size-cells = <2>;
 446                 ranges;
 447                 status = "disabled";
 448                 usbdrd_dwc3_0: dwc3@fe800000 {
 449                         compatible = "snps,dwc3";
 450                         reg = <0x0 0xfe800000 0x0 0x100000>;
 451                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
 452                         dr_mode = "otg";
 453                         phys = <&u2phy0_otg>, <&tcphy0 1>;
 454                         phy-names = "usb2-phy", "usb3-phy";
 455                         phy_type = "utmi_wide";
 456                         snps,dis_enblslpm_quirk;
 457                         snps,dis-u2-freeclk-exists-quirk;
 458                         snps,dis-del-phy-power-chg-quirk;
 459                         snps,xhci-slow-suspend-quirk;
 460                         status = "disabled";
 461                 };
 462         };
 463
 464         usbdrd3_1: usb@fe900000 {
 465                 compatible = "rockchip,rk3399-dwc3";
 466                 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
 467                          <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_GRF>;
 468                 clock-names = "ref_clk", "suspend_clk",
 469                               "bus_clk", "grf_clk";
 470                 power-domains = <&power RK3399_PD_USB3>;
 471                 resets = <&cru SRST_A_USB3_OTG1>;
 472                 reset-names = "usb3-otg";
 473                 #address-cells = <2>;
 474                 #size-cells = <2>;
 475                 ranges;
 476                 status = "disabled";
 477                 usbdrd_dwc3_1: dwc3@fe900000 {
 478                         compatible = "snps,dwc3";
 479                         reg = <0x0 0xfe900000 0x0 0x100000>;
 480                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
 481                         dr_mode = "host";
 482                         phys = <&u2phy1_otg>, <&tcphy1 1>;
 483                         phy-names = "usb2-phy", "usb3-phy";
 484                         phy_type = "utmi_wide";
 485                         snps,dis_enblslpm_quirk;
 486                         snps,dis-u2-freeclk-exists-quirk;
 487                         snps,dis-del-phy-power-chg-quirk;
 488                         snps,xhci-slow-suspend-quirk;
 489                         status = "disabled";
 490                 };
 491         };
 492
 493         gic: interrupt-controller@fee00000 {
 494                 compatible = "arm,gic-v3";
 495                 #interrupt-cells = <4>;
 496                 #address-cells = <2>;
 497                 #size-cells = <2>;
 498                 ranges;
 499                 interrupt-controller;
 500
 501                 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
 502                       <0x0 0xfef00000 0 0xc0000>, /* GICR */
 503                       <0x0 0xfff00000 0 0x10000>, /* GICC */
 504                       <0x0 0xfff10000 0 0x10000>, /* GICH */
 505                       <0x0 0xfff20000 0 0x10000>; /* GICV */
 506                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
 507                 its: interrupt-controller@fee20000 {
 508                         compatible = "arm,gic-v3-its";
 509                         msi-controller;
 510                         reg = <0x0 0xfee20000 0x0 0x20000>;
 511                 };
 512
 513                 ppi-partitions {
 514                         part0: interrupt-partition-0 {
 515                                 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
 516                         };
 517
 518                         part1: interrupt-partition-1 {
 519                                 affinity = <&cpu_b0 &cpu_b1>;
 520                         };
 521                 };
 522         };
 523
 524         saradc: saradc@ff100000 {
 525                 compatible = "rockchip,rk3399-saradc";
 526                 reg = <0x0 0xff100000 0x0 0x100>;
 527                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>;
 528                 #io-channel-cells = <1>;
 529                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 530                 clock-names = "saradc", "apb_pclk";
 531                 status = "disabled";
 532         };
 533
 534         i2c0: i2c@ff3c0000 {
 535                 compatible = "rockchip,rk3399-i2c";
 536                 reg = <0x0 0xff3c0000 0x0 0x1000>;
 537                 clocks =  <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
 538                 clock-names = "i2c", "pclk";
 539                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
 540                 pinctrl-names = "default";
 541                 pinctrl-0 = <&i2c0_xfer>;
 542                 #address-cells = <1>;
 543                 #size-cells = <0>;
 544                 status = "disabled";
 545         };
 546
 547         i2c1: i2c@ff110000 {
 548                 compatible = "rockchip,rk3399-i2c";
 549                 reg = <0x0 0xff110000 0x0 0x1000>;
 550                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 551                 clock-names = "i2c", "pclk";
 552                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>;
 553                 pinctrl-names = "default";
 554                 pinctrl-0 = <&i2c1_xfer>;
 555                 #address-cells = <1>;
 556                 #size-cells = <0>;
 557                 status = "disabled";
 558         };
 559
 560         i2c2: i2c@ff120000 {
 561                 compatible = "rockchip,rk3399-i2c";
 562                 reg = <0x0 0xff120000 0x0 0x1000>;
 563                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 564                 clock-names = "i2c", "pclk";
 565                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>;
 566                 pinctrl-names = "default";
 567                 pinctrl-0 = <&i2c2_xfer>;
 568                 #address-cells = <1>;
 569                 #size-cells = <0>;
 570                 status = "disabled";
 571         };
 572
 573         i2c3: i2c@ff130000 {
 574                 compatible = "rockchip,rk3399-i2c";
 575                 reg = <0x0 0xff130000 0x0 0x1000>;
 576                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 577                 clock-names = "i2c", "pclk";
 578                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>;
 579                 pinctrl-names = "default";
 580                 pinctrl-0 = <&i2c3_xfer>;
 581                 #address-cells = <1>;
 582                 #size-cells = <0>;
 583                 status = "disabled";
 584         };
 585
 586         i2c5: i2c@ff140000 {
 587                 compatible = "rockchip,rk3399-i2c";
 588                 reg = <0x0 0xff140000 0x0 0x1000>;
 589                 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
 590                 clock-names = "i2c", "pclk";
 591                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>;
 592                 pinctrl-names = "default";
 593                 pinctrl-0 = <&i2c5_xfer>;
 594                 #address-cells = <1>;
 595                 #size-cells = <0>;
 596                 status = "disabled";
 597         };
 598
 599         i2c6: i2c@ff150000 {
 600                 compatible = "rockchip,rk3399-i2c";
 601                 reg = <0x0 0xff150000 0x0 0x1000>;
 602                 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
 603                 clock-names = "i2c", "pclk";
 604                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>;
 605                 pinctrl-names = "default";
 606                 pinctrl-0 = <&i2c6_xfer>;
 607                 #address-cells = <1>;
 608                 #size-cells = <0>;
 609                 status = "disabled";
 610         };
 611
 612         i2c7: i2c@ff160000 {
 613                 compatible = "rockchip,rk3399-i2c";
 614                 reg = <0x0 0xff160000 0x0 0x1000>;
 615                 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
 616                 clock-names = "i2c", "pclk";
 617                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>;
 618                 pinctrl-names = "default";
 619                 pinctrl-0 = <&i2c7_xfer>;
 620                 #address-cells = <1>;
 621                 #size-cells = <0>;
 622                 status = "disabled";
 623         };
 624
 625         uart0: serial@ff180000 {
 626                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 627                 reg = <0x0 0xff180000 0x0 0x100>;
 628                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 629                 clock-names = "baudclk", "apb_pclk";
 630                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
 631                 reg-shift = <2>;
 632                 reg-io-width = <4>;
 633                 pinctrl-names = "default";
 634                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 635                 status = "disabled";
 636         };
 637
 638         uart1: serial@ff190000 {
 639                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 640                 reg = <0x0 0xff190000 0x0 0x100>;
 641                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 642                 clock-names = "baudclk", "apb_pclk";
 643                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>;
 644                 reg-shift = <2>;
 645                 reg-io-width = <4>;
 646                 pinctrl-names = "default";
 647                 pinctrl-0 = <&uart1_xfer>;
 648                 status = "disabled";
 649         };
 650
 651         uart2: serial@ff1a0000 {
 652                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 653                 reg = <0x0 0xff1a0000 0x0 0x100>;
 654                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 655                 clock-names = "baudclk", "apb_pclk";
 656                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
 657                 reg-shift = <2>;
 658                 reg-io-width = <4>;
 659                 pinctrl-names = "default";
 660                 pinctrl-0 = <&uart2c_xfer>;
 661                 status = "disabled";
 662         };
 663
 664         uart3: serial@ff1b0000 {
 665                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 666                 reg = <0x0 0xff1b0000 0x0 0x100>;
 667                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 668                 clock-names = "baudclk", "apb_pclk";
 669                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
 670                 reg-shift = <2>;
 671                 reg-io-width = <4>;
 672                 pinctrl-names = "default";
 673                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 674                 status = "disabled";
 675         };
 676
 677         spi0: spi@ff1c0000 {
 678                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 679                 reg = <0x0 0xff1c0000 0x0 0x1000>;
 680                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 681                 clock-names = "spiclk", "apb_pclk";
 682                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>;
 683                 pinctrl-names = "default";
 684                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 685                 #address-cells = <1>;
 686                 #size-cells = <0>;
 687                 status = "disabled";
 688         };
 689
 690         spi1: spi@ff1d0000 {
 691                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 692                 reg = <0x0 0xff1d0000 0x0 0x1000>;
 693                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 694                 clock-names = "spiclk", "apb_pclk";
 695                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>;
 696                 pinctrl-names = "default";
 697                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 698                 #address-cells = <1>;
 699                 #size-cells = <0>;
 700                 status = "disabled";
 701         };
 702
 703         spi2: spi@ff1e0000 {
 704                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 705                 reg = <0x0 0xff1e0000 0x0 0x1000>;
 706                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 707                 clock-names = "spiclk", "apb_pclk";
 708                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>;
 709                 pinctrl-names = "default";
 710                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 711                 #address-cells = <1>;
 712                 #size-cells = <0>;
 713                 status = "disabled";
 714         };
 715
 716         spi4: spi@ff1f0000 {
 717                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 718                 reg = <0x0 0xff1f0000 0x0 0x1000>;
 719                 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
 720                 clock-names = "spiclk", "apb_pclk";
 721                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>;
 722                 pinctrl-names = "default";
 723                 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
 724                 #address-cells = <1>;
 725                 #size-cells = <0>;
 726                 status = "disabled";
 727         };
 728
 729         spi5: spi@ff200000 {
 730                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 731                 reg = <0x0 0xff200000 0x0 0x1000>;
 732                 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
 733                 clock-names = "spiclk", "apb_pclk";
 734                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
 735                 pinctrl-names = "default";
 736                 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
 737                 #address-cells = <1>;
 738                 #size-cells = <0>;
 739                 status = "disabled";
 740         };
 741
 742         thermal-zones {
 743                 soc_thermal: soc-thermal {
 744                         polling-delay-passive = <20>; /* milliseconds */
 745                         polling-delay = <1000>; /* milliseconds */
 746                         sustainable-power = <1000>; /* milliwatts */
 747
 748                         thermal-sensors = <&tsadc 0>;
 749
 750                         trips {
 751                                 threshold: trip-point@0 {
 752                                         temperature = <70000>; /* millicelsius */
 753                                         hysteresis = <2000>; /* millicelsius */
 754                                         type = "passive";
 755                                 };
 756                                 target: trip-point@1 {
 757                                         temperature = <85000>; /* millicelsius */
 758                                         hysteresis = <2000>; /* millicelsius */
 759                                         type = "passive";
 760                                 };
 761                                 soc_crit: soc-crit {
 762                                         temperature = <95000>; /* millicelsius */
 763                                         hysteresis = <2000>; /* millicelsius */
 764                                         type = "critical";
 765                                 };
 766                         };
 767
 768                         cooling-maps {
 769                                 map0 {
 770                                         trip = <&target>;
 771                                         cooling-device =
 772                                                 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 773                                         contribution = <4096>;
 774                                 };
 775                                 map1 {
 776                                         trip = <&target>;
 777                                         cooling-device =
 778                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 779                                         contribution = <1024>;
 780                                 };
 781                                 map2 {
 782                                         trip = <&target>;
 783                                         cooling-device =
 784                                                 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 785                                         contribution = <4096>;
 786                                 };
 787                         };
 788                 };
 789
 790                 gpu_thermal: gpu-thermal {
 791                         polling-delay-passive = <100>; /* milliseconds */
 792                         polling-delay = <1000>; /* milliseconds */
 793
 794                         thermal-sensors = <&tsadc 1>;
 795                 };
 796         };
 797
 798         tsadc: tsadc@ff260000 {
 799                 compatible = "rockchip,rk3399-tsadc";
 800                 reg = <0x0 0xff260000 0x0 0x100>;
 801                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
 802                 rockchip,grf = <&grf>;
 803                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 804                 clock-names = "tsadc", "apb_pclk";
 805                 assigned-clocks = <&cru SCLK_TSADC>;
 806                 assigned-clock-rates = <750000>;
 807                 resets = <&cru SRST_TSADC>;
 808                 reset-names = "tsadc-apb";
 809                 pinctrl-names = "init", "default", "sleep";
 810                 pinctrl-0 = <&otp_gpio>;
 811                 pinctrl-1 = <&otp_out>;
 812                 pinctrl-2 = <&otp_gpio>;
 813                 #thermal-sensor-cells = <1>;
 814                 rockchip,hw-tshut-temp = <95000>;
 815                 status = "disabled";
 816         };
 817
 818         qos_emmc: qos@ffa58000 {
 819                 compatible = "syscon";
 820                 reg = <0x0 0xffa58000 0x0 0x20>;
 821         };
 822
 823         qos_gmac: qos@ffa5c000 {
 824                 compatible = "syscon";
 825                 reg = <0x0 0xffa5c000 0x0 0x20>;
 826         };
 827
 828         qos_pcie: qos@ffa60080 {
 829                 compatible = "syscon";
 830                 reg = <0x0 0xffa60080 0x0 0x20>;
 831         };
 832
 833         qos_usb_host0: qos@ffa60100 {
 834                 compatible = "syscon";
 835                 reg = <0x0 0xffa60100 0x0 0x20>;
 836         };
 837
 838         qos_usb_host1: qos@ffa60180 {
 839                 compatible = "syscon";
 840                 reg = <0x0 0xffa60180 0x0 0x20>;
 841         };
 842
 843         qos_usb_otg0: qos@ffa70000 {
 844                 compatible = "syscon";
 845                 reg = <0x0 0xffa70000 0x0 0x20>;
 846         };
 847
 848         qos_usb_otg1: qos@ffa70080 {
 849                 compatible = "syscon";
 850                 reg = <0x0 0xffa70080 0x0 0x20>;
 851         };
 852
 853         qos_sd: qos@ffa74000 {
 854                 compatible = "syscon";
 855                 reg = <0x0 0xffa74000 0x0 0x20>;
 856         };
 857
 858         qos_sdioaudio: qos@ffa76000 {
 859                 compatible = "syscon";
 860                 reg = <0x0 0xffa76000 0x0 0x20>;
 861         };
 862
 863         qos_hdcp: qos@ffa90000 {
 864                 compatible = "syscon";
 865                 reg = <0x0 0xffa90000 0x0 0x20>;
 866         };
 867
 868         qos_iep: qos@ffa98000 {
 869                 compatible = "syscon";
 870                 reg = <0x0 0xffa98000 0x0 0x20>;
 871         };
 872
 873         qos_isp0_m0: qos@ffaa0000 {
 874                 compatible = "syscon";
 875                 reg = <0x0 0xffaa0000 0x0 0x20>;
 876         };
 877
 878         qos_isp0_m1: qos@ffaa0080 {
 879                 compatible = "syscon";
 880                 reg = <0x0 0xffaa0080 0x0 0x20>;
 881         };
 882
 883         qos_isp1_m0: qos@ffaa8000 {
 884                 compatible = "syscon";
 885                 reg = <0x0 0xffaa8000 0x0 0x20>;
 886         };
 887
 888         qos_isp1_m1: qos@ffaa8080 {
 889                 compatible = "syscon";
 890                 reg = <0x0 0xffaa8080 0x0 0x20>;
 891         };
 892
 893         qos_rga_r: qos@ffab0000 {
 894                 compatible = "syscon";
 895                 reg = <0x0 0xffab0000 0x0 0x20>;
 896         };
 897
 898         qos_rga_w: qos@ffab0080 {
 899                 compatible = "syscon";
 900                 reg = <0x0 0xffab0080 0x0 0x20>;
 901         };
 902
 903         qos_video_m0: qos@ffab8000 {
 904                 compatible = "syscon";
 905                 reg = <0x0 0xffab8000 0x0 0x20>;
 906         };
 907
 908         qos_video_m1_r: qos@ffac0000 {
 909                 compatible = "syscon";
 910                 reg = <0x0 0xffac0000 0x0 0x20>;
 911         };
 912
 913         qos_video_m1_w: qos@ffac0080 {
 914                 compatible = "syscon";
 915                 reg = <0x0 0xffac0080 0x0 0x20>;
 916         };
 917
 918         qos_vop_big_r: qos@ffac8000 {
 919                 compatible = "syscon";
 920                 reg = <0x0 0xffac8000 0x0 0x20>;
 921         };
 922
 923         qos_vop_big_w: qos@ffac8080 {
 924                 compatible = "syscon";
 925                 reg = <0x0 0xffac8080 0x0 0x20>;
 926         };
 927
 928         qos_vop_little: qos@ffad0000 {
 929                 compatible = "syscon";
 930                 reg = <0x0 0xffad0000 0x0 0x20>;
 931         };
 932
 933         qos_perihp: qos@ffad8080 {
 934                 compatible = "syscon";
 935                 reg = <0x0 0xffad8080 0x0 0x20>;
 936         };
 937
 938         qos_gpu: qos@ffae0000 {
 939                 compatible = "syscon";
 940                 reg = <0x0 0xffae0000 0x0 0x20>;
 941         };
 942
 943         pmu: power-management@ff310000 {
 944                 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
 945                 reg = <0x0 0xff310000 0x0 0x1000>;
 946
 947                 /*
 948                  * Note: RK3399 supports 6 voltage domains including VD_CORE_L,
 949                  * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
 950                  * Some of the power domains are grouped together for every
 951                  * voltage domain.
 952                  * The detail contents as below.
 953                  */
 954                 power: power-controller {
 955                         compatible = "rockchip,rk3399-power-controller";
 956                         #power-domain-cells = <1>;
 957                         #address-cells = <1>;
 958                         #size-cells = <0>;
 959
 960                         /* These power domains are grouped by VD_CENTER */
 961                         pd_iep@RK3399_PD_IEP {
 962                                 reg = <RK3399_PD_IEP>;
 963                                 clocks = <&cru ACLK_IEP>,
 964                                          <&cru HCLK_IEP>;
 965                                 pm_qos = <&qos_iep>;
 966                         };
 967                         pd_rga@RK3399_PD_RGA {
 968                                 reg = <RK3399_PD_RGA>;
 969                                 clocks = <&cru ACLK_RGA>,
 970                                          <&cru HCLK_RGA>;
 971                                 pm_qos = <&qos_rga_r>,
 972                                          <&qos_rga_w>;
 973                         };
 974                         pd_vcodec@RK3399_PD_VCODEC {
 975                                 reg = <RK3399_PD_VCODEC>;
 976                                 clocks = <&cru ACLK_VCODEC>,
 977                                          <&cru HCLK_VCODEC>;
 978                                 pm_qos = <&qos_video_m0>;
 979                         };
 980                         pd_vdu@RK3399_PD_VDU {
 981                                 reg = <RK3399_PD_VDU>;
 982                                 clocks = <&cru ACLK_VDU>,
 983                                          <&cru HCLK_VDU>;
 984                                 pm_qos = <&qos_video_m1_r>,
 985                                          <&qos_video_m1_w>;
 986                         };
 987
 988                         /* These power domains are grouped by VD_GPU */
 989                         pd_gpu@RK3399_PD_GPU {
 990                                 reg = <RK3399_PD_GPU>;
 991                                 clocks = <&cru ACLK_GPU>;
 992                                 pm_qos = <&qos_gpu>;
 993                         };
 994
 995                         /* These power domains are grouped by VD_LOGIC */
 996                         pd_edp@RK3399_PD_EDP {
 997                                 reg = <RK3399_PD_EDP>;
 998                                 clocks = <&cru PCLK_EDP_CTRL>;
 999                         };
1000                         pd_emmc@RK3399_PD_EMMC {
1001                                 reg = <RK3399_PD_EMMC>;
1002                                 clocks = <&cru ACLK_EMMC>;
1003                                 pm_qos = <&qos_emmc>;
1004                         };
1005                         pd_gmac@RK3399_PD_GMAC {
1006                                 reg = <RK3399_PD_GMAC>;
1007                                 clocks = <&cru ACLK_GMAC>;
1008                                 pm_qos = <&qos_gmac>;
1009                         };
1010                         pd_perihp@RK3399_PD_PERIHP {
1011                                 reg = <RK3399_PD_PERIHP>;
1012                                 #address-cells = <1>;
1013                                 #size-cells = <0>;
1014                                 clocks = <&cru ACLK_PERIHP>;
1015                                 pm_qos = <&qos_perihp>,
1016                                          <&qos_pcie>,
1017                                          <&qos_usb_host0>,
1018                                          <&qos_usb_host1>;
1019
1020                                 pd_sd@RK3399_PD_SD {
1021                                         reg = <RK3399_PD_SD>;
1022                                         clocks = <&cru HCLK_SDMMC>,
1023                                                  <&cru SCLK_SDMMC>;
1024                                         pm_qos = <&qos_sd>;
1025                                 };
1026                         };
1027                         pd_sdioaudio@RK3399_PD_SDIOAUDIO {
1028                                 reg = <RK3399_PD_SDIOAUDIO>;
1029                                 clocks = <&cru HCLK_SDIO>;
1030                                 pm_qos = <&qos_sdioaudio>;
1031                         };
1032                         pd_usb3@RK3399_PD_USB3 {
1033                                 reg = <RK3399_PD_USB3>;
1034                                 clocks = <&cru ACLK_USB3>;
1035                                 pm_qos = <&qos_usb_otg0>,
1036                                          <&qos_usb_otg1>;
1037                         };
1038                         pd_vio@RK3399_PD_VIO {
1039                                 reg = <RK3399_PD_VIO>;
1040                                 #address-cells = <1>;
1041                                 #size-cells = <0>;
1042
1043                                 pd_hdcp@RK3399_PD_HDCP {
1044                                         reg = <RK3399_PD_HDCP>;
1045                                         clocks = <&cru ACLK_HDCP>,
1046                                                  <&cru HCLK_HDCP>,
1047                                                  <&cru PCLK_HDCP>;
1048                                         pm_qos = <&qos_hdcp>;
1049                                 };
1050                                 pd_isp0@RK3399_PD_ISP0 {
1051                                         reg = <RK3399_PD_ISP0>;
1052                                         clocks = <&cru ACLK_ISP0>,
1053                                                  <&cru HCLK_ISP0>;
1054                                         pm_qos = <&qos_isp0_m0>,
1055                                                  <&qos_isp0_m1>;
1056                                 };
1057                                 pd_isp1@RK3399_PD_ISP1 {
1058                                         reg = <RK3399_PD_ISP1>;
1059                                         clocks = <&cru ACLK_ISP1>,
1060                                                  <&cru HCLK_ISP1>;
1061                                         pm_qos = <&qos_isp1_m0>,
1062                                                  <&qos_isp1_m1>;
1063                                 };
1064                                 pd_vo@RK3399_PD_VO {
1065                                         reg = <RK3399_PD_VO>;
1066                                         #address-cells = <1>;
1067                                         #size-cells = <0>;
1068
1069                                         pd_vopb@RK3399_PD_VOPB {
1070                                                 reg = <RK3399_PD_VOPB>;
1071                                                 clocks = <&cru ACLK_VOP0>,
1072                                                          <&cru HCLK_VOP0>;
1073                                                 pm_qos = <&qos_vop_big_r>,
1074                                                          <&qos_vop_big_w>;
1075                                         };
1076                                         pd_vopl@RK3399_PD_VOPL {
1077                                                 reg = <RK3399_PD_VOPL>;
1078                                                 clocks = <&cru ACLK_VOP1>,
1079                                                          <&cru HCLK_VOP1>;
1080                                                 pm_qos = <&qos_vop_little>;
1081                                         };
1082                                 };
1083                         };
1084                 };
1085         };
1086
1087         pmugrf: syscon@ff320000 {
1088                 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
1089                 reg = <0x0 0xff320000 0x0 0x1000>;
1090
1091                 reboot-mode {
1092                         compatible = "syscon-reboot-mode";
1093                         offset = <0x300>;
1094                         mode-bootloader = <BOOT_LOADER>;
1095                         mode-charge = <BOOT_CHARGING>;
1096                         mode-fastboot = <BOOT_FASTBOOT>;
1097                         mode-loader = <BOOT_LOADER>;
1098                         mode-normal = <BOOT_NORMAL>;
1099                         mode-recovery = <BOOT_RECOVERY>;
1100                         mode-ums = <BOOT_UMS>;
1101                 };
1102         };
1103
1104         spi3: spi@ff350000 {
1105                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
1106                 reg = <0x0 0xff350000 0x0 0x1000>;
1107                 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
1108                 clock-names = "spiclk", "apb_pclk";
1109                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>;
1110                 pinctrl-names = "default";
1111                 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
1112                 #address-cells = <1>;
1113                 #size-cells = <0>;
1114                 status = "disabled";
1115         };
1116
1117         uart4: serial@ff370000 {
1118                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
1119                 reg = <0x0 0xff370000 0x0 0x100>;
1120                 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
1121                 clock-names = "baudclk", "apb_pclk";
1122                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>;
1123                 reg-shift = <2>;
1124                 reg-io-width = <4>;
1125                 pinctrl-names = "default";
1126                 pinctrl-0 = <&uart4_xfer>;
1127                 status = "disabled";
1128         };
1129
1130         i2c4: i2c@ff3d0000 {
1131                 compatible = "rockchip,rk3399-i2c";
1132                 reg = <0x0 0xff3d0000 0x0 0x1000>;
1133                 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
1134                 clock-names = "i2c", "pclk";
1135                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>;
1136                 pinctrl-names = "default";
1137                 pinctrl-0 = <&i2c4_xfer>;
1138                 #address-cells = <1>;
1139                 #size-cells = <0>;
1140                 status = "disabled";
1141         };
1142
1143         i2c8: i2c@ff3e0000 {
1144                 compatible = "rockchip,rk3399-i2c";
1145                 reg = <0x0 0xff3e0000 0x0 0x1000>;
1146                 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
1147                 clock-names = "i2c", "pclk";
1148                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
1149                 pinctrl-names = "default";
1150                 pinctrl-0 = <&i2c8_xfer>;
1151                 #address-cells = <1>;
1152                 #size-cells = <0>;
1153                 status = "disabled";
1154         };
1155
1156         pcie_phy: phy@e220 {
1157                 compatible = "rockchip,rk3399-pcie-phy";
1158                 #phy-cells = <0>;
1159                 rockchip,grf = <&grf>;
1160                 clocks = <&cru SCLK_PCIEPHY_REF>;
1161                 clock-names = "refclk";
1162                 resets = <&cru SRST_PCIEPHY>;
1163                 reset-names = "phy";
1164                 status = "disabled";
1165         };
1166
1167         pcie0: pcie@f8000000 {
1168                 compatible = "rockchip,rk3399-pcie";
1169                 #address-cells = <3>;
1170                 #size-cells = <2>;
1171                 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
1172                          <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
1173                 clock-names = "aclk", "aclk-perf",
1174                               "hclk", "pm";
1175                 bus-range = <0x0 0x1>;
1176                 msi-map = <0x0 &its 0x0 0x1000>;
1177                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
1178                              <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
1179                              <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
1180                 interrupt-names = "sys", "legacy", "client";
1181                 #interrupt-cells = <1>;
1182                 interrupt-map-mask = <0 0 0 7>;
1183                 interrupt-map = <0 0 0 1 &pcie0_intc 0>,
1184                                 <0 0 0 2 &pcie0_intc 1>,
1185                                 <0 0 0 3 &pcie0_intc 2>,
1186                                 <0 0 0 4 &pcie0_intc 3>;
1187                 phys = <&pcie_phy>;
1188                 phy-names = "pcie-phy";
1189                 ranges = <0x82000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000
1190                           0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>;
1191                 reg = <0x0 0xf8000000 0x0 0x2000000>,
1192                       <0x0 0xfd000000 0x0 0x1000000>;
1193                 reg-names = "axi-base", "apb-base";
1194                 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
1195                          <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>;
1196                 reset-names = "core", "mgmt", "mgmt-sticky", "pipe";
1197                 status = "disabled";
1198                 pcie0_intc: interrupt-controller {
1199                         interrupt-controller;
1200                         #address-cells = <0>;
1201                         #interrupt-cells = <1>;
1202                 };
1203         };
1204
1205         pwm0: pwm@ff420000 {
1206                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1207                 reg = <0x0 0xff420000 0x0 0x10>;
1208                 #pwm-cells = <3>;
1209                 pinctrl-names = "default";
1210                 pinctrl-0 = <&pwm0_pin>;
1211                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1212                 clock-names = "pwm";
1213                 status = "disabled";
1214         };
1215
1216         pwm1: pwm@ff420010 {
1217                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1218                 reg = <0x0 0xff420010 0x0 0x10>;
1219                 #pwm-cells = <3>;
1220                 pinctrl-names = "default";
1221                 pinctrl-0 = <&pwm1_pin>;
1222                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1223                 clock-names = "pwm";
1224                 status = "disabled";
1225         };
1226
1227         pwm2: pwm@ff420020 {
1228                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1229                 reg = <0x0 0xff420020 0x0 0x10>;
1230                 #pwm-cells = <3>;
1231                 pinctrl-names = "default";
1232                 pinctrl-0 = <&pwm2_pin>;
1233                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1234                 clock-names = "pwm";
1235                 status = "disabled";
1236         };
1237
1238         pwm3: pwm@ff420030 {
1239                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1240                 reg = <0x0 0xff420030 0x0 0x10>;
1241                 #pwm-cells = <3>;
1242                 pinctrl-names = "default";
1243                 pinctrl-0 = <&pwm3a_pin>;
1244                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1245                 clock-names = "pwm";
1246                 status = "disabled";
1247         };
1248
1249         dfi: dfi@ff630000 {
1250                 reg = <0x00 0xff630000 0x00 0x4000>;
1251                 compatible = "rockchip,rk3399-dfi";
1252                 rockchip,pmu = <&pmugrf>;
1253                 clocks = <&cru PCLK_DDR_MON>;
1254                 clock-names = "pclk_ddr_mon";
1255                 status = "disabled";
1256         };
1257
1258         dmc: dmc {
1259                 compatible = "rockchip,rk3399-dmc";
1260                 devfreq-events = <&dfi>;
1261                 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>;
1262                 clocks = <&cru SCLK_DDRCLK>;
1263                 clock-names = "dmc_clk";
1264                 ddr_timing = <&ddr_timing>;
1265                 operating-points-v2 = <&dmc_opp_table>;
1266                 status = "disabled";
1267         };
1268
1269         dmc_opp_table: dmc_opp_table {
1270                 compatible = "operating-points-v2";
1271
1272                 opp00 {
1273                         opp-hz = /bits/ 64 <666000000>;
1274                         opp-microvolt = <900000>;
1275                 };
1276         };
1277
1278         rga: rga@ff680000 {
1279                 compatible = "rockchip,rk3399-rga";
1280                 reg = <0x0 0xff680000 0x0 0x10000>;
1281                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
1282                 interrupt-names = "rga";
1283                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
1284                 clock-names = "aclk", "hclk", "sclk";
1285                 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
1286                 reset-names = "core", "axi", "ahb";
1287                 power-domains = <&power RK3399_PD_RGA>;
1288                 status = "disabled";
1289         };
1290
1291         efuse0: efuse@ff690000 {
1292                 compatible = "rockchip,rk3399-efuse";
1293                 reg = <0x0 0xff690000 0x0 0x80>;
1294                 #address-cells = <1>;
1295                 #size-cells = <1>;
1296                 clocks = <&cru PCLK_EFUSE1024NS>;
1297                 clock-names = "pclk_efuse";
1298
1299                 /* Data cells */
1300                 cpul_leakage: cpul-leakage {
1301                         reg = <0x1a 0x1>;
1302                 };
1303                 cpub_leakage: cpub-leakage {
1304                         reg = <0x17 0x1>;
1305                 };
1306                 gpu_leakage: gpu-leakage {
1307                         reg = <0x18 0x1>;
1308                 };
1309                 center_leakage: center-leakage {
1310                         reg = <0x19 0x1>;
1311                 };
1312                 logic_leakage: logic-leakage {
1313                         reg = <0x1b 0x1>;
1314                 };
1315                 wafer_info: wafer-info {
1316                         reg = <0x1c 0x1>;
1317                 };
1318         };
1319
1320         pmucru: pmu-clock-controller@ff750000 {
1321                 compatible = "rockchip,rk3399-pmucru";
1322                 reg = <0x0 0xff750000 0x0 0x1000>;
1323                 #clock-cells = <1>;
1324                 #reset-cells = <1>;
1325                 assigned-clocks = <&pmucru PLL_PPLL>;
1326                 assigned-clock-rates = <676000000>;
1327         };
1328
1329         cru: clock-controller@ff760000 {
1330                 compatible = "rockchip,rk3399-cru";
1331                 reg = <0x0 0xff760000 0x0 0x1000>;
1332                 #clock-cells = <1>;
1333                 #reset-cells = <1>;
1334                 assigned-clocks =
1335                         <&cru ACLK_VOP0>, <&cru HCLK_VOP0>,
1336                         <&cru ACLK_VOP1>, <&cru HCLK_VOP1>,
1337                         <&cru ARMCLKL>, <&cru ARMCLKB>,
1338                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1339                         <&cru PLL_NPLL>,
1340                         <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1341                         <&cru PCLK_PERIHP>,
1342                         <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1343                         <&cru PCLK_PERILP0>,
1344                         <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
1345                 assigned-clock-rates =
1346                          <400000000>,  <200000000>,
1347                          <400000000>,  <200000000>,
1348                          <816000000>, <816000000>,
1349                          <594000000>,  <800000000>,
1350                         <1000000000>,
1351                          <150000000>,   <75000000>,
1352                           <37500000>,
1353                          <100000000>,  <100000000>,
1354                           <50000000>,
1355                          <100000000>,   <50000000>;
1356         };
1357
1358         grf: syscon@ff770000 {
1359                 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
1360                 reg = <0x0 0xff770000 0x0 0x10000>;
1361                 #address-cells = <1>;
1362                 #size-cells = <1>;
1363
1364                 u2phy0: usb2-phy@e450 {
1365                         compatible = "rockchip,rk3399-usb2phy";
1366                         reg = <0xe450 0x10>;
1367                         clocks = <&cru SCLK_USB2PHY0_REF>;
1368                         clock-names = "phyclk";
1369                         #clock-cells = <0>;
1370                         clock-output-names = "clk_usbphy0_480m";
1371                         status = "disabled";
1372
1373                         u2phy0_otg: otg-port {
1374                                 #phy-cells = <0>;
1375                                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
1376                                              <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
1377                                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
1378                                 interrupt-names = "otg-bvalid", "otg-id",
1379                                                   "linestate";
1380                                 status = "disabled";
1381                         };
1382
1383                         u2phy0_host: host-port {
1384                                 #phy-cells = <0>;
1385                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
1386                                 interrupt-names = "linestate";
1387                                 status = "disabled";
1388                         };
1389                 };
1390
1391                 u2phy1: usb2-phy@e460 {
1392                         compatible = "rockchip,rk3399-usb2phy";
1393                         reg = <0xe460 0x10>;
1394                         clocks = <&cru SCLK_USB2PHY1_REF>;
1395                         clock-names = "phyclk";
1396                         #clock-cells = <0>;
1397                         clock-output-names = "clk_usbphy1_480m";
1398                         status = "disabled";
1399
1400                         u2phy1_otg: otg-port {
1401                                 #phy-cells = <0>;
1402                                 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
1403                                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
1404                                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1405                                 interrupt-names = "otg-bvalid", "otg-id",
1406                                                   "linestate";
1407                                 status = "disabled";
1408                         };
1409
1410                         u2phy1_host: host-port {
1411                                 #phy-cells = <0>;
1412                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
1413                                 interrupt-names = "linestate";
1414                                 status = "disabled";
1415                         };
1416                 };
1417         };
1418
1419         tcphy0: phy@ff7c0000 {
1420                 compatible = "rockchip,rk3399-typec-phy";
1421                 reg = <0x0 0xff7c0000 0x0 0x40000>;
1422                 rockchip,grf = <&grf>;
1423                 #phy-cells = <1>;
1424                 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1425                          <&cru SCLK_UPHY0_TCPDPHY_REF>;
1426                 clock-names = "tcpdcore", "tcpdphy-ref";
1427                 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
1428                 assigned-clock-rates = <50000000>;
1429                 resets = <&cru SRST_UPHY0>,
1430                          <&cru SRST_UPHY0_PIPE_L00>,
1431                          <&cru SRST_P_UPHY0_TCPHY>;
1432                 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1433                 rockchip,typec-conn-dir = <0xe580 0 16>;
1434                 rockchip,usb3tousb2-en = <0xe580 3 19>;
1435                 rockchip,external-psm = <0xe588 14 30>;
1436                 rockchip,pipe-status = <0xe5c0 0 0>;
1437                 rockchip,uphy-dp-sel = <0x6268 19 19>;
1438                 status = "disabled";
1439         };
1440
1441         tcphy1: phy@ff800000 {
1442                 compatible = "rockchip,rk3399-typec-phy";
1443                 reg = <0x0 0xff800000 0x0 0x40000>;
1444                 rockchip,grf = <&grf>;
1445                 #phy-cells = <1>;
1446                 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1447                          <&cru SCLK_UPHY1_TCPDPHY_REF>;
1448                 clock-names = "tcpdcore", "tcpdphy-ref";
1449                 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
1450                 assigned-clock-rates = <50000000>;
1451                 resets = <&cru SRST_UPHY1>,
1452                          <&cru SRST_UPHY1_PIPE_L00>,
1453                          <&cru SRST_P_UPHY1_TCPHY>;
1454                 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1455                 rockchip,typec-conn-dir = <0xe58c 0 16>;
1456                 rockchip,usb3tousb2-en = <0xe58c 3 19>;
1457                 rockchip,external-psm = <0xe594 14 30>;
1458                 rockchip,pipe-status = <0xe5c0 16 16>;
1459                 rockchip,uphy-dp-sel = <0x6268 3 19>;
1460                 status = "disabled";
1461         };
1462
1463         watchdog@ff848000 {
1464                 compatible = "snps,dw-wdt";
1465                 reg = <0x0 0xff848000 0x0 0x100>;
1466                 clocks = <&cru PCLK_WDT>;
1467                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
1468         };
1469
1470         rktimer: rktimer@ff850000 {
1471                 compatible = "rockchip,rk3399-timer";
1472                 reg = <0x0 0xff850000 0x0 0x1000>;
1473                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
1474                 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1475                 clock-names = "pclk", "timer";
1476         };
1477
1478         spdif: spdif@ff870000 {
1479                 compatible = "rockchip,rk3399-spdif";
1480                 reg = <0x0 0xff870000 0x0 0x1000>;
1481                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
1482                 dmas = <&dmac_bus 7>;
1483                 dma-names = "tx";
1484                 clock-names = "mclk", "hclk";
1485                 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1486                 pinctrl-names = "default";
1487                 pinctrl-0 = <&spdif_bus>;
1488                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1489                 status = "disabled";
1490         };
1491
1492         i2s0: i2s@ff880000 {
1493                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1494                 reg = <0x0 0xff880000 0x0 0x1000>;
1495                 rockchip,grf = <&grf>;
1496                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>;
1497                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1498                 dma-names = "tx", "rx";
1499                 clock-names = "i2s_clk", "i2s_hclk";
1500                 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1501                 pinctrl-names = "default";
1502                 pinctrl-0 = <&i2s0_8ch_bus>;
1503                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1504                 status = "disabled";
1505         };
1506
1507         i2s1: i2s@ff890000 {
1508                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1509                 reg = <0x0 0xff890000 0x0 0x1000>;
1510                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>;
1511                 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1512                 dma-names = "tx", "rx";
1513                 clock-names = "i2s_clk", "i2s_hclk";
1514                 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1515                 pinctrl-names = "default";
1516                 pinctrl-0 = <&i2s1_2ch_bus>;
1517                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1518                 status = "disabled";
1519         };
1520
1521         i2s2: i2s@ff8a0000 {
1522                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1523                 reg = <0x0 0xff8a0000 0x0 0x1000>;
1524                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>;
1525                 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1526                 dma-names = "tx", "rx";
1527                 clock-names = "i2s_clk", "i2s_hclk";
1528                 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1529                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1530                 status = "disabled";
1531         };
1532
1533         gpu: gpu@ff9a0000 {
1534                 compatible = "arm,malit860",
1535                              "arm,malit86x",
1536                              "arm,malit8xx",
1537                              "arm,mali-midgard";
1538
1539                 reg = <0x0 0xff9a0000 0x0 0x10000>;
1540
1541                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>,
1542                              <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
1543                              <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>;
1544                 interrupt-names = "GPU", "JOB", "MMU";
1545
1546                 clocks = <&cru ACLK_GPU>;
1547                 clock-names = "clk_mali";
1548                 #cooling-cells = <2>; /* min followed by max */
1549                 operating-points-v2 = <&gpu_opp_table>;
1550                 power-domains = <&power RK3399_PD_GPU>;
1551                 power-off-delay-ms = <200>;
1552                 status = "disabled";
1553
1554                 gpu_power_model: power_model {
1555                         compatible = "arm,mali-simple-power-model";
1556                         voltage = <900>;
1557                         frequency = <500>;
1558                         static-power = <300>;
1559                         dynamic-power = <396>;
1560                         ts = <32000 4700 (-80) 2>;
1561                         thermal-zone = "gpu-thermal";
1562                 };
1563         };
1564
1565         gpu_opp_table: gpu_opp_table {
1566                 compatible = "operating-points-v2";
1567                 opp-shared;
1568
1569                 opp@200000000 {
1570                         opp-hz = /bits/ 64 <200000000>;
1571                         opp-microvolt = <900000>;
1572                 };
1573                 opp@300000000 {
1574                         opp-hz = /bits/ 64 <300000000>;
1575                         opp-microvolt = <900000>;
1576                 };
1577                 opp@400000000 {
1578                         opp-hz = /bits/ 64 <400000000>;
1579                         opp-microvolt = <900000>;
1580                 };
1581
1582         };
1583
1584         vopl: vop@ff8f0000 {
1585                 compatible = "rockchip,rk3399-vop-lit";
1586                 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1587                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1588                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1589                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1590                 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1591                 reset-names = "axi", "ahb", "dclk";
1592                 power-domains = <&power RK3399_PD_VOPL>;
1593                 iommus = <&vopl_mmu>;
1594                 status = "disabled";
1595
1596                 vopl_out: port {
1597                         #address-cells = <1>;
1598                         #size-cells = <0>;
1599
1600                         vopl_out_mipi: endpoint@0 {
1601                                 reg = <0>;
1602                                 remote-endpoint = <&mipi_in_vopl>;
1603                         };
1604
1605                         vopl_out_edp: endpoint@1 {
1606                                 reg = <1>;
1607                                 remote-endpoint = <&edp_in_vopl>;
1608                         };
1609
1610                         vopl_out_hdmi: endpoint@2 {
1611                                 reg = <2>;
1612                                 remote-endpoint = <&hdmi_in_vopl>;
1613                         };
1614                 };
1615         };
1616
1617         vop1_pwm: voppwm@ff8f01a0 {
1618                 compatible = "rockchip,vop-pwm";
1619                 reg = <0x0 0xff8f01a0 0x0 0x10>;
1620                 #pwm-cells = <3>;
1621                 pinctrl-names = "default";
1622                 pinctrl-0 = <&vop1_pwm_pin>;
1623                 clocks = <&cru SCLK_VOP1_PWM>;
1624                 clock-names = "pwm";
1625                 status = "disabled";
1626         };
1627
1628         vopl_mmu: iommu@ff8f3f00 {
1629                 compatible = "rockchip,iommu";
1630                 reg = <0x0 0xff8f3f00 0x0 0x100>;
1631                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1632                 interrupt-names = "vopl_mmu";
1633                 #iommu-cells = <0>;
1634                 status = "disabled";
1635         };
1636
1637         vopb: vop@ff900000 {
1638                 compatible = "rockchip,rk3399-vop-big";
1639                 reg = <0x0 0xff900000 0x0 0x3efc>;
1640                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1641                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1642                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1643                 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1644                 reset-names = "axi", "ahb", "dclk";
1645                 power-domains = <&power RK3399_PD_VOPB>;
1646                 iommus = <&vopb_mmu>;
1647                 status = "disabled";
1648
1649                 vopb_out: port {
1650                         #address-cells = <1>;
1651                         #size-cells = <0>;
1652
1653                         vopb_out_edp: endpoint@0 {
1654                                 reg = <0>;
1655                                 remote-endpoint = <&edp_in_vopb>;
1656                         };
1657
1658                         vopb_out_mipi: endpoint@1 {
1659                                 reg = <1>;
1660                                 remote-endpoint = <&mipi_in_vopb>;
1661                         };
1662
1663                         vopb_out_hdmi: endpoint@2 {
1664                                 reg = <2>;
1665                                 remote-endpoint = <&hdmi_in_vopb>;
1666                         };
1667                 };
1668         };
1669
1670         vop0_pwm: voppwm@ff9001a0 {
1671                 compatible = "rockchip,vop-pwm";
1672                 reg = <0x0 0xff9001a0 0x0 0x10>;
1673                 #pwm-cells = <3>;
1674                 pinctrl-names = "default";
1675                 pinctrl-0 = <&vop0_pwm_pin>;
1676                 clocks = <&cru SCLK_VOP0_PWM>;
1677                 clock-names = "pwm";
1678                 status = "disabled";
1679         };
1680
1681         vopb_mmu: iommu@ff903f00 {
1682                 compatible = "rockchip,iommu";
1683                 reg = <0x0 0xff903f00 0x0 0x100>;
1684                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1685                 interrupt-names = "vopb_mmu";
1686                 #iommu-cells = <0>;
1687                 status = "disabled";
1688         };
1689
1690         hdmi: hdmi@ff940000 {
1691                 compatible = "rockchip,rk3399-dw-hdmi";
1692                 reg = <0x0 0xff940000 0x0 0x20000>;
1693                 reg-io-width = <4>;
1694                 rockchip,grf = <&grf>;
1695                 power-domains = <&power RK3399_PD_HDCP>;
1696                 pinctrl-names = "default";
1697                 pinctrl-0 = <&hdmi_i2c_xfer>;
1698                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
1699                 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_SFR>, <&cru SCLK_HDMI_SFR>, <&cru PCLK_EDP_CTRL>;
1700                 clock-names = "iahb", "isfr", "vpll", "grf";
1701                 status = "disabled";
1702
1703                 ports {
1704                         hdmi_in: port {
1705                                 #address-cells = <1>;
1706                                 #size-cells = <0>;
1707                                 hdmi_in_vopb: endpoint@0 {
1708                                         reg = <0>;
1709                                         remote-endpoint = <&vopb_out_hdmi>;
1710                                 };
1711                                 hdmi_in_vopl: endpoint@1 {
1712                                         reg = <1>;
1713                                         remote-endpoint = <&vopl_out_hdmi>;
1714                                 };
1715                         };
1716                 };
1717         };
1718
1719         mipi_dsi: mipi@ff960000 {
1720                 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1721                 reg = <0x0 0xff960000 0x0 0x8000>;
1722                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
1723                 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
1724                          <&cru SCLK_DPHY_TX0_CFG>;
1725                 clock-names = "ref", "pclk", "phy_cfg";
1726                 power-domains = <&power RK3399_PD_VIO>;
1727                 rockchip,grf = <&grf>;
1728                 #address-cells = <1>;
1729                 #size-cells = <0>;
1730                 status = "disabled";
1731
1732                 ports {
1733                         #address-cells = <1>;
1734                         #size-cells = <0>;
1735                         reg = <1>;
1736
1737                         mipi_in: port {
1738                                 #address-cells = <1>;
1739                                 #size-cells = <0>;
1740
1741                                 mipi_in_vopb: endpoint@0 {
1742                                         reg = <0>;
1743                                         remote-endpoint = <&vopb_out_mipi>;
1744                                 };
1745                                 mipi_in_vopl: endpoint@1 {
1746                                         reg = <1>;
1747                                         remote-endpoint = <&vopl_out_mipi>;
1748                                 };
1749                         };
1750                 };
1751         };
1752
1753         edp: edp@ff970000 {
1754                 compatible = "rockchip,rk3399-edp";
1755                 reg = <0x0 0xff970000 0x0 0x8000>;
1756                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
1757                 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1758                 clock-names = "dp", "pclk";
1759                 resets = <&cru SRST_P_EDP_CTRL>;
1760                 reset-names = "dp";
1761                 rockchip,grf = <&grf>;
1762                 status = "disabled";
1763                 pinctrl-names = "default";
1764                 pinctrl-0 = <&edp_hpd>;
1765
1766                 ports {
1767                         #address-cells = <1>;
1768                         #size-cells = <0>;
1769
1770                         edp_in: port@0 {
1771                                 reg = <0>;
1772                                 #address-cells = <1>;
1773                                 #size-cells = <0>;
1774
1775                                 edp_in_vopb: endpoint@0 {
1776                                         reg = <0>;
1777                                         remote-endpoint = <&vopb_out_edp>;
1778                                 };
1779
1780                                 edp_in_vopl: endpoint@1 {
1781                                         reg = <1>;
1782                                         remote-endpoint = <&vopl_out_edp>;
1783                                 };
1784                         };
1785                 };
1786         };
1787
1788         display_subsystem: display-subsystem {
1789                 compatible = "rockchip,display-subsystem";
1790                 ports = <&vopl_out>, <&vopb_out>;
1791                 status = "disabled";
1792         };
1793
1794         pinctrl: pinctrl {
1795                 compatible = "rockchip,rk3399-pinctrl";
1796                 rockchip,grf = <&grf>;
1797                 rockchip,pmu = <&pmugrf>;
1798                 #address-cells = <0x2>;
1799                 #size-cells = <0x2>;
1800                 ranges;
1801
1802                 gpio0: gpio0@ff720000 {
1803                         compatible = "rockchip,gpio-bank";
1804                         reg = <0x0 0xff720000 0x0 0x100>;
1805                         clocks = <&pmucru PCLK_GPIO0_PMU>;
1806                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
1807
1808                         gpio-controller;
1809                         #gpio-cells = <0x2>;
1810
1811                         interrupt-controller;
1812                         #interrupt-cells = <0x2>;
1813                 };
1814
1815                 gpio1: gpio1@ff730000 {
1816                         compatible = "rockchip,gpio-bank";
1817                         reg = <0x0 0xff730000 0x0 0x100>;
1818                         clocks = <&pmucru PCLK_GPIO1_PMU>;
1819                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
1820
1821                         gpio-controller;
1822                         #gpio-cells = <0x2>;
1823
1824                         interrupt-controller;
1825                         #interrupt-cells = <0x2>;
1826                 };
1827
1828                 gpio2: gpio2@ff780000 {
1829                         compatible = "rockchip,gpio-bank";
1830                         reg = <0x0 0xff780000 0x0 0x100>;
1831                         clocks = <&cru PCLK_GPIO2>;
1832                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>;
1833
1834                         gpio-controller;
1835                         #gpio-cells = <0x2>;
1836
1837                         interrupt-controller;
1838                         #interrupt-cells = <0x2>;
1839                 };
1840
1841                 gpio3: gpio3@ff788000 {
1842                         compatible = "rockchip,gpio-bank";
1843                         reg = <0x0 0xff788000 0x0 0x100>;
1844                         clocks = <&cru PCLK_GPIO3>;
1845                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
1846
1847                         gpio-controller;
1848                         #gpio-cells = <0x2>;
1849
1850                         interrupt-controller;
1851                         #interrupt-cells = <0x2>;
1852                 };
1853
1854                 gpio4: gpio4@ff790000 {
1855                         compatible = "rockchip,gpio-bank";
1856                         reg = <0x0 0xff790000 0x0 0x100>;
1857                         clocks = <&cru PCLK_GPIO4>;
1858                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
1859
1860                         gpio-controller;
1861                         #gpio-cells = <0x2>;
1862
1863                         interrupt-controller;
1864                         #interrupt-cells = <0x2>;
1865                 };
1866
1867                 pcfg_pull_up: pcfg-pull-up {
1868                         bias-pull-up;
1869                 };
1870
1871                 pcfg_pull_down: pcfg-pull-down {
1872                         bias-pull-down;
1873                 };
1874
1875                 pcfg_pull_none: pcfg-pull-none {
1876                         bias-disable;
1877                 };
1878
1879                 pcfg_pull_up_20ma: pcfg-pull-up-20ma {
1880                         bias-pull-up;
1881                         drive-strength = <20>;
1882                 };
1883
1884                 pcfg_pull_none_20ma: pcfg-pull-none-20ma {
1885                         bias-disable;
1886                         drive-strength = <20>;
1887                 };
1888
1889                 pcfg_pull_none_18ma: pcfg-pull-none-18ma {
1890                         bias-disable;
1891                         drive-strength = <18>;
1892                 };
1893
1894                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1895                         bias-disable;
1896                         drive-strength = <12>;
1897                 };
1898
1899                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1900                         bias-pull-up;
1901                         drive-strength = <8>;
1902                 };
1903
1904                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1905                         bias-pull-down;
1906                         drive-strength = <4>;
1907                 };
1908
1909                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1910                         bias-pull-up;
1911                         drive-strength = <2>;
1912                 };
1913
1914                 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
1915                         bias-pull-down;
1916                         drive-strength = <12>;
1917                 };
1918
1919                 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
1920                         bias-disable;
1921                         drive-strength = <13>;
1922                 };
1923
1924                 pcfg_output_high: pcfg-output-high {
1925                         output-high;
1926                 };
1927
1928                 pcfg_output_low: pcfg-output-low {
1929                         output-low;
1930                 };
1931
1932                 pcfg_input: pcfg-input {
1933                         input-enable;
1934                 };
1935
1936                 emmc {
1937                         emmc_pwr: emmc-pwr {
1938                                 rockchip,pins =
1939                                         <0 5 RK_FUNC_1 &pcfg_pull_up>;
1940                         };
1941                 };
1942
1943                 gmac {
1944                         rgmii_pins: rgmii-pins {
1945                                 rockchip,pins =
1946                                         /* mac_txclk */
1947                                         <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
1948                                         /* mac_rxclk */
1949                                         <3 14 RK_FUNC_1 &pcfg_pull_none>,
1950                                         /* mac_mdio */
1951                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
1952                                         /* mac_txen */
1953                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1954                                         /* mac_clk */
1955                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
1956                                         /* mac_rxdv */
1957                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
1958                                         /* mac_mdc */
1959                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
1960                                         /* mac_rxd1 */
1961                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
1962                                         /* mac_rxd0 */
1963                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
1964                                         /* mac_txd1 */
1965                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1966                                         /* mac_txd0 */
1967                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
1968                                         /* mac_rxd3 */
1969                                         <3 3 RK_FUNC_1 &pcfg_pull_none>,
1970                                         /* mac_rxd2 */
1971                                         <3 2 RK_FUNC_1 &pcfg_pull_none>,
1972                                         /* mac_txd3 */
1973                                         <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
1974                                         /* mac_txd2 */
1975                                         <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
1976                         };
1977
1978                         rmii_pins: rmii-pins {
1979                                 rockchip,pins =
1980                                         /* mac_mdio */
1981                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
1982                                         /* mac_txen */
1983                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1984                                         /* mac_clk */
1985                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
1986                                         /* mac_rxer */
1987                                         <3 10 RK_FUNC_1 &pcfg_pull_none>,
1988                                         /* mac_rxdv */
1989                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
1990                                         /* mac_mdc */
1991                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
1992                                         /* mac_rxd1 */
1993                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
1994                                         /* mac_rxd0 */
1995                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
1996                                         /* mac_txd1 */
1997                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1998                                         /* mac_txd0 */
1999                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
2000                         };
2001                 };
2002
2003                 i2c0 {
2004                         i2c0_xfer: i2c0-xfer {
2005                                 rockchip,pins =
2006                                         <1 15 RK_FUNC_2 &pcfg_pull_none>,
2007                                         <1 16 RK_FUNC_2 &pcfg_pull_none>;
2008                         };
2009                 };
2010
2011                 i2c1 {
2012                         i2c1_xfer: i2c1-xfer {
2013                                 rockchip,pins =
2014                                         <4 2 RK_FUNC_1 &pcfg_pull_none>,
2015                                         <4 1 RK_FUNC_1 &pcfg_pull_none>;
2016                         };
2017                 };
2018
2019                 i2c2 {
2020                         i2c2_xfer: i2c2-xfer {
2021                                 rockchip,pins =
2022                                         <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
2023                                         <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
2024                         };
2025                 };
2026
2027                 i2c3 {
2028                         i2c3_xfer: i2c3-xfer {
2029                                 rockchip,pins =
2030                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
2031                                         <4 16 RK_FUNC_1 &pcfg_pull_none>;
2032                         };
2033
2034                         i2c3_gpio: i2c3_gpio {
2035                                 rockchip,pins =
2036                                         <4 17 RK_FUNC_GPIO &pcfg_pull_none>,
2037                                         <4 16 RK_FUNC_GPIO &pcfg_pull_none>;
2038                         };
2039
2040                 };
2041
2042                 i2c4 {
2043                         i2c4_xfer: i2c4-xfer {
2044                                 rockchip,pins =
2045                                         <1 12 RK_FUNC_1 &pcfg_pull_none>,
2046                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
2047                         };
2048                 };
2049
2050                 i2c5 {
2051                         i2c5_xfer: i2c5-xfer {
2052                                 rockchip,pins =
2053                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
2054                                         <3 10 RK_FUNC_2 &pcfg_pull_none>;
2055                         };
2056                 };
2057
2058                 i2c6 {
2059                         i2c6_xfer: i2c6-xfer {
2060                                 rockchip,pins =
2061                                         <2 10 RK_FUNC_2 &pcfg_pull_none>,
2062                                         <2 9 RK_FUNC_2 &pcfg_pull_none>;
2063                         };
2064                 };
2065
2066                 i2c7 {
2067                         i2c7_xfer: i2c7-xfer {
2068                                 rockchip,pins =
2069                                         <2 8 RK_FUNC_2 &pcfg_pull_none>,
2070                                         <2 7 RK_FUNC_2 &pcfg_pull_none>;
2071                         };
2072                 };
2073
2074                 i2c8 {
2075                         i2c8_xfer: i2c8-xfer {
2076                                 rockchip,pins =
2077                                         <1 21 RK_FUNC_1 &pcfg_pull_none>,
2078                                         <1 20 RK_FUNC_1 &pcfg_pull_none>;
2079                         };
2080                 };
2081
2082                 i2s0 {
2083                         i2s0_8ch_bus: i2s0-8ch-bus {
2084                                 rockchip,pins =
2085                                         <3 24 RK_FUNC_1 &pcfg_pull_none>,
2086                                         <3 25 RK_FUNC_1 &pcfg_pull_none>,
2087                                         <3 26 RK_FUNC_1 &pcfg_pull_none>,
2088                                         <3 27 RK_FUNC_1 &pcfg_pull_none>,
2089                                         <3 28 RK_FUNC_1 &pcfg_pull_none>,
2090                                         <3 29 RK_FUNC_1 &pcfg_pull_none>,
2091                                         <3 30 RK_FUNC_1 &pcfg_pull_none>,
2092                                         <3 31 RK_FUNC_1 &pcfg_pull_none>,
2093                                         <4 0 RK_FUNC_1 &pcfg_pull_none>;
2094                         };
2095                 };
2096
2097                 i2s1 {
2098                         i2s1_2ch_bus: i2s1-2ch-bus {
2099                                 rockchip,pins =
2100                                         <4 3 RK_FUNC_1 &pcfg_pull_none>,
2101                                         <4 4 RK_FUNC_1 &pcfg_pull_none>,
2102                                         <4 5 RK_FUNC_1 &pcfg_pull_none>,
2103                                         <4 6 RK_FUNC_1 &pcfg_pull_none>,
2104                                         <4 7 RK_FUNC_1 &pcfg_pull_none>;
2105                         };
2106                 };
2107
2108                 sdio0 {
2109                         sdio0_bus1: sdio0-bus1 {
2110                                 rockchip,pins =
2111                                         <2 20 RK_FUNC_1 &pcfg_pull_up>;
2112                         };
2113
2114                         sdio0_bus4: sdio0-bus4 {
2115                                 rockchip,pins =
2116                                         <2 20 RK_FUNC_1 &pcfg_pull_up>,
2117                                         <2 21 RK_FUNC_1 &pcfg_pull_up>,
2118                                         <2 22 RK_FUNC_1 &pcfg_pull_up>,
2119                                         <2 23 RK_FUNC_1 &pcfg_pull_up>;
2120                         };
2121
2122                         sdio0_cmd: sdio0-cmd {
2123                                 rockchip,pins =
2124                                         <2 24 RK_FUNC_1 &pcfg_pull_up>;
2125                         };
2126
2127                         sdio0_clk: sdio0-clk {
2128                                 rockchip,pins =
2129                                         <2 25 RK_FUNC_1 &pcfg_pull_none>;
2130                         };
2131
2132                         sdio0_cd: sdio0-cd {
2133                                 rockchip,pins =
2134                                         <2 26 RK_FUNC_1 &pcfg_pull_up>;
2135                         };
2136
2137                         sdio0_pwr: sdio0-pwr {
2138                                 rockchip,pins =
2139                                         <2 27 RK_FUNC_1 &pcfg_pull_up>;
2140                         };
2141
2142                         sdio0_bkpwr: sdio0-bkpwr {
2143                                 rockchip,pins =
2144                                         <2 28 RK_FUNC_1 &pcfg_pull_up>;
2145                         };
2146
2147                         sdio0_wp: sdio0-wp {
2148                                 rockchip,pins =
2149                                         <0 3 RK_FUNC_1 &pcfg_pull_up>;
2150                         };
2151
2152                         sdio0_int: sdio0-int {
2153                                 rockchip,pins =
2154                                         <0 4 RK_FUNC_1 &pcfg_pull_up>;
2155                         };
2156                 };
2157
2158                 sdmmc {
2159                         sdmmc_bus1: sdmmc-bus1 {
2160                                 rockchip,pins =
2161                                         <4 8 RK_FUNC_1 &pcfg_pull_up>;
2162                         };
2163
2164                         sdmmc_bus4: sdmmc-bus4 {
2165                                 rockchip,pins =
2166                                         <4 8 RK_FUNC_1 &pcfg_pull_up>,
2167                                         <4 9 RK_FUNC_1 &pcfg_pull_up>,
2168                                         <4 10 RK_FUNC_1 &pcfg_pull_up>,
2169                                         <4 11 RK_FUNC_1 &pcfg_pull_up>;
2170                         };
2171
2172                         sdmmc_clk: sdmmc-clk {
2173                                 rockchip,pins =
2174                                         <4 12 RK_FUNC_1 &pcfg_pull_none>;
2175                         };
2176
2177                         sdmmc_cmd: sdmmc-cmd {
2178                                 rockchip,pins =
2179                                         <4 13 RK_FUNC_1 &pcfg_pull_up>;
2180                         };
2181
2182                         sdmmc_cd: sdmcc-cd {
2183                                 rockchip,pins =
2184                                         <0 7 RK_FUNC_1 &pcfg_pull_up>;
2185                         };
2186
2187                         sdmmc_wp: sdmmc-wp {
2188                                 rockchip,pins =
2189                                         <0 8 RK_FUNC_1 &pcfg_pull_up>;
2190                         };
2191                 };
2192
2193                 spdif {
2194                         spdif_bus: spdif-bus {
2195                                 rockchip,pins =
2196                                         <4 21 RK_FUNC_1 &pcfg_pull_none>;
2197                         };
2198
2199                         spdif_bus_1: spdif-bus-1 {
2200                                 rockchip,pins =
2201                                         <3 16 RK_FUNC_3 &pcfg_pull_none>;
2202                         };
2203                 };
2204
2205                 spi0 {
2206                         spi0_clk: spi0-clk {
2207                                 rockchip,pins =
2208                                         <3 6 RK_FUNC_2 &pcfg_pull_up>;
2209                         };
2210                         spi0_cs0: spi0-cs0 {
2211                                 rockchip,pins =
2212                                         <3 7 RK_FUNC_2 &pcfg_pull_up>;
2213                         };
2214                         spi0_cs1: spi0-cs1 {
2215                                 rockchip,pins =
2216                                         <3 8 RK_FUNC_2 &pcfg_pull_up>;
2217                         };
2218                         spi0_tx: spi0-tx {
2219                                 rockchip,pins =
2220                                         <3 5 RK_FUNC_2 &pcfg_pull_up>;
2221                         };
2222                         spi0_rx: spi0-rx {
2223                                 rockchip,pins =
2224                                         <3 4 RK_FUNC_2 &pcfg_pull_up>;
2225                         };
2226                 };
2227
2228                 spi1 {
2229                         spi1_clk: spi1-clk {
2230                                 rockchip,pins =
2231                                         <1 9 RK_FUNC_2 &pcfg_pull_up>;
2232                         };
2233                         spi1_cs0: spi1-cs0 {
2234                                 rockchip,pins =
2235                                         <1 10 RK_FUNC_2 &pcfg_pull_up>;
2236                         };
2237                         spi1_rx: spi1-rx {
2238                                 rockchip,pins =
2239                                         <1 7 RK_FUNC_2 &pcfg_pull_up>;
2240                         };
2241                         spi1_tx: spi1-tx {
2242                                 rockchip,pins =
2243                                         <1 8 RK_FUNC_2 &pcfg_pull_up>;
2244                         };
2245                 };
2246
2247                 spi2 {
2248                         spi2_clk: spi2-clk {
2249                                 rockchip,pins =
2250                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
2251                         };
2252                         spi2_cs0: spi2-cs0 {
2253                                 rockchip,pins =
2254                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
2255                         };
2256                         spi2_rx: spi2-rx {
2257                                 rockchip,pins =
2258                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
2259                         };
2260                         spi2_tx: spi2-tx {
2261                                 rockchip,pins =
2262                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
2263                         };
2264                 };
2265
2266                 spi3 {
2267                         spi3_clk: spi3-clk {
2268                                 rockchip,pins =
2269                                         <1 17 RK_FUNC_1 &pcfg_pull_up>;
2270                         };
2271                         spi3_cs0: spi3-cs0 {
2272                                 rockchip,pins =
2273                                         <1 18 RK_FUNC_1 &pcfg_pull_up>;
2274                         };
2275                         spi3_rx: spi3-rx {
2276                                 rockchip,pins =
2277                                         <1 15 RK_FUNC_1 &pcfg_pull_up>;
2278                         };
2279                         spi3_tx: spi3-tx {
2280                                 rockchip,pins =
2281                                         <1 16 RK_FUNC_1 &pcfg_pull_up>;
2282                         };
2283                 };
2284
2285                 spi4 {
2286                         spi4_clk: spi4-clk {
2287                                 rockchip,pins =
2288                                         <3 2 RK_FUNC_2 &pcfg_pull_up>;
2289                         };
2290                         spi4_cs0: spi4-cs0 {
2291                                 rockchip,pins =
2292                                         <3 3 RK_FUNC_2 &pcfg_pull_up>;
2293                         };
2294                         spi4_rx: spi4-rx {
2295                                 rockchip,pins =
2296                                         <3 0 RK_FUNC_2 &pcfg_pull_up>;
2297                         };
2298                         spi4_tx: spi4-tx {
2299                                 rockchip,pins =
2300                                         <3 1 RK_FUNC_2 &pcfg_pull_up>;
2301                         };
2302                 };
2303
2304                 spi5 {
2305                         spi5_clk: spi5-clk {
2306                                 rockchip,pins =
2307                                         <2 22 RK_FUNC_2 &pcfg_pull_up>;
2308                         };
2309                         spi5_cs0: spi5-cs0 {
2310                                 rockchip,pins =
2311                                         <2 23 RK_FUNC_2 &pcfg_pull_up>;
2312                         };
2313                         spi5_rx: spi5-rx {
2314                                 rockchip,pins =
2315                                         <2 20 RK_FUNC_2 &pcfg_pull_up>;
2316                         };
2317                         spi5_tx: spi5-tx {
2318                                 rockchip,pins =
2319                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
2320                         };
2321                 };
2322
2323                 tsadc {
2324                         otp_gpio: otp-gpio {
2325                                 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
2326                         };
2327
2328                         otp_out: otp-out {
2329                                 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
2330                         };
2331                 };
2332
2333                 uart0 {
2334                         uart0_xfer: uart0-xfer {
2335                                 rockchip,pins =
2336                                         <2 16 RK_FUNC_1 &pcfg_pull_up>,
2337                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
2338                         };
2339
2340                         uart0_cts: uart0-cts {
2341                                 rockchip,pins =
2342                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
2343                         };
2344
2345                         uart0_rts: uart0-rts {
2346                                 rockchip,pins =
2347                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
2348                         };
2349                 };
2350
2351                 uart1 {
2352                         uart1_xfer: uart1-xfer {
2353                                 rockchip,pins =
2354                                         <3 12 RK_FUNC_2 &pcfg_pull_up>,
2355                                         <3 13 RK_FUNC_2 &pcfg_pull_none>;
2356                         };
2357                 };
2358
2359                 uart2a {
2360                         uart2a_xfer: uart2a-xfer {
2361                                 rockchip,pins =
2362                                         <4 8 RK_FUNC_2 &pcfg_pull_up>,
2363                                         <4 9 RK_FUNC_2 &pcfg_pull_none>;
2364                         };
2365                 };
2366
2367                 uart2b {
2368                         uart2b_xfer: uart2b-xfer {
2369                                 rockchip,pins =
2370                                         <4 16 RK_FUNC_2 &pcfg_pull_up>,
2371                                         <4 17 RK_FUNC_2 &pcfg_pull_none>;
2372                         };
2373                 };
2374
2375                 uart2c {
2376                         uart2c_xfer: uart2c-xfer {
2377                                 rockchip,pins =
2378                                         <4 19 RK_FUNC_1 &pcfg_pull_up>,
2379                                         <4 20 RK_FUNC_1 &pcfg_pull_none>;
2380                         };
2381                 };
2382
2383                 uart3 {
2384                         uart3_xfer: uart3-xfer {
2385                                 rockchip,pins =
2386                                         <3 14 RK_FUNC_2 &pcfg_pull_up>,
2387                                         <3 15 RK_FUNC_2 &pcfg_pull_none>;
2388                         };
2389
2390                         uart3_cts: uart3-cts {
2391                                 rockchip,pins =
2392                                         <3 18 RK_FUNC_2 &pcfg_pull_none>;
2393                         };
2394
2395                         uart3_rts: uart3-rts {
2396                                 rockchip,pins =
2397                                         <3 19 RK_FUNC_2 &pcfg_pull_none>;
2398                         };
2399                 };
2400
2401                 uart4 {
2402                         uart4_xfer: uart4-xfer {
2403                                 rockchip,pins =
2404                                         <1 7 RK_FUNC_1 &pcfg_pull_up>,
2405                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
2406                         };
2407                 };
2408
2409                 uarthdcp {
2410                         uarthdcp_xfer: uarthdcp-xfer {
2411                                 rockchip,pins =
2412                                         <4 21 RK_FUNC_2 &pcfg_pull_up>,
2413                                         <4 22 RK_FUNC_2 &pcfg_pull_none>;
2414                         };
2415                 };
2416
2417                 pwm0 {
2418                         pwm0_pin: pwm0-pin {
2419                                 rockchip,pins =
2420                                         <4 18 RK_FUNC_1 &pcfg_pull_none>;
2421                         };
2422
2423                         vop0_pwm_pin: vop0-pwm-pin {
2424                                 rockchip,pins =
2425                                         <4 18 RK_FUNC_2 &pcfg_pull_none>;
2426                         };
2427                 };
2428
2429                 pwm1 {
2430                         pwm1_pin: pwm1-pin {
2431                                 rockchip,pins =
2432                                         <4 22 RK_FUNC_1 &pcfg_pull_none>;
2433                         };
2434
2435                         vop1_pwm_pin: vop1-pwm-pin {
2436                                 rockchip,pins =
2437                                         <4 18 RK_FUNC_3 &pcfg_pull_none>;
2438                         };
2439                 };
2440
2441                 pwm2 {
2442                         pwm2_pin: pwm2-pin {
2443                                 rockchip,pins =
2444                                         <1 19 RK_FUNC_1 &pcfg_pull_none>;
2445                         };
2446                 };
2447
2448                 pwm3a {
2449                         pwm3a_pin: pwm3a-pin {
2450                                 rockchip,pins =
2451                                         <0 6 RK_FUNC_1 &pcfg_pull_none>;
2452                         };
2453                 };
2454
2455                 pwm3b {
2456                         pwm3b_pin: pwm3b-pin {
2457                                 rockchip,pins =
2458                                         <1 14 RK_FUNC_1 &pcfg_pull_none>;
2459                         };
2460                 };
2461
2462                 edp {
2463                         edp_hpd: edp-hpd {
2464                                 rockchip,pins =
2465                                         <4 23 RK_FUNC_2 &pcfg_pull_none>;
2466                         };
2467                 };
2468
2469                 hdmi {
2470                         hdmi_i2c_xfer: hdmi-i2c-xfer {
2471                                 rockchip,pins =
2472                                         <4 17 RK_FUNC_3 &pcfg_pull_none>,
2473                                         <4 16 RK_FUNC_3 &pcfg_pull_none>;
2474                         };
2475
2476                         hdmi_cec: hdmi-cec {
2477                                 rockchip,pins =
2478                                         <4 23 RK_FUNC_1 &pcfg_pull_none>;
2479                         };
2480                 };
2481
2482                 pcie {
2483                         pcie_clkreqn: pci-clkreqn {
2484                                 rockchip,pins =
2485                                         <2 26 RK_FUNC_2 &pcfg_pull_none>;
2486                         };
2487
2488                         pcie_clkreqnb: pci-clkreqnb {
2489                                 rockchip,pins =
2490                                         <4 24 RK_FUNC_1 &pcfg_pull_none>;
2491                         };
2492                 };
2493         };
2494 };