arch/arm64/boot/dts/rockchip/rk3399.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3399-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/interrupt-controller/irq.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/power/rk3399-power.h>
  49 #include <dt-bindings/soc/rockchip_boot-mode.h>
  50 #include <dt-bindings/thermal/thermal.h>
  51
  52 / {
  53         compatible = "rockchip,rk3399";
  54
  55         interrupt-parent = <&gic>;
  56         #address-cells = <2>;
  57         #size-cells = <2>;
  58
  59         aliases {
  60                 i2c0 = &i2c0;
  61                 i2c1 = &i2c1;
  62                 i2c2 = &i2c2;
  63                 i2c3 = &i2c3;
  64                 i2c4 = &i2c4;
  65                 i2c5 = &i2c5;
  66                 i2c6 = &i2c6;
  67                 i2c7 = &i2c7;
  68                 i2c8 = &i2c8;
  69                 serial0 = &uart0;
  70                 serial1 = &uart1;
  71                 serial2 = &uart2;
  72                 serial3 = &uart3;
  73                 serial4 = &uart4;
  74         };
  75
  76         psci {
  77                 compatible = "arm,psci-1.0";
  78                 method = "smc";
  79         };
  80
  81         cpus {
  82                 #address-cells = <2>;
  83                 #size-cells = <0>;
  84
  85                 cpu-map {
  86                         cluster0 {
  87                                 core0 {
  88                                         cpu = <&cpu_l0>;
  89                                 };
  90                                 core1 {
  91                                         cpu = <&cpu_l1>;
  92                                 };
  93                                 core2 {
  94                                         cpu = <&cpu_l2>;
  95                                 };
  96                                 core3 {
  97                                         cpu = <&cpu_l3>;
  98                                 };
  99                         };
 100
 101                         cluster1 {
 102                                 core0 {
 103                                         cpu = <&cpu_b0>;
 104                                 };
 105                                 core1 {
 106                                         cpu = <&cpu_b1>;
 107                                 };
 108                         };
 109                 };
 110
 111                 cpu_l0: cpu@0 {
 112                         device_type = "cpu";
 113                         compatible = "arm,cortex-a53", "arm,armv8";
 114                         reg = <0x0 0x0>;
 115                         enable-method = "psci";
 116                         #cooling-cells = <2>; /* min followed by max */
 117                         dynamic-power-coefficient = <100>;
 118                         clocks = <&cru ARMCLKL>;
 119                         cpu-idle-states = <&cpu_sleep>;
 120                         operating-points-v2 = <&cluster0_opp>;
 121                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
 122                 };
 123
 124                 cpu_l1: cpu@1 {
 125                         device_type = "cpu";
 126                         compatible = "arm,cortex-a53", "arm,armv8";
 127                         reg = <0x0 0x1>;
 128                         enable-method = "psci";
 129                         clocks = <&cru ARMCLKL>;
 130                         cpu-idle-states = <&cpu_sleep>;
 131                         operating-points-v2 = <&cluster0_opp>;
 132                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
 133                 };
 134
 135                 cpu_l2: cpu@2 {
 136                         device_type = "cpu";
 137                         compatible = "arm,cortex-a53", "arm,armv8";
 138                         reg = <0x0 0x2>;
 139                         enable-method = "psci";
 140                         clocks = <&cru ARMCLKL>;
 141                         cpu-idle-states = <&cpu_sleep>;
 142                         operating-points-v2 = <&cluster0_opp>;
 143                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
 144                 };
 145
 146                 cpu_l3: cpu@3 {
 147                         device_type = "cpu";
 148                         compatible = "arm,cortex-a53", "arm,armv8";
 149                         reg = <0x0 0x3>;
 150                         enable-method = "psci";
 151                         clocks = <&cru ARMCLKL>;
 152                         cpu-idle-states = <&cpu_sleep>;
 153                         operating-points-v2 = <&cluster0_opp>;
 154                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
 155                 };
 156
 157                 cpu_b0: cpu@100 {
 158                         device_type = "cpu";
 159                         compatible = "arm,cortex-a72", "arm,armv8";
 160                         reg = <0x0 0x100>;
 161                         enable-method = "psci";
 162                         #cooling-cells = <2>; /* min followed by max */
 163                         dynamic-power-coefficient = <436>;
 164                         clocks = <&cru ARMCLKB>;
 165                         cpu-idle-states = <&cpu_sleep>;
 166                         operating-points-v2 = <&cluster1_opp>;
 167                         sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>;
 168                 };
 169
 170                 cpu_b1: cpu@101 {
 171                         device_type = "cpu";
 172                         compatible = "arm,cortex-a72", "arm,armv8";
 173                         reg = <0x0 0x101>;
 174                         enable-method = "psci";
 175                         clocks = <&cru ARMCLKB>;
 176                         cpu-idle-states = <&cpu_sleep>;
 177                         operating-points-v2 = <&cluster1_opp>;
 178                         sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>;
 179                 };
 180
 181                 idle-states {
 182                         entry-method = "psci";
 183                         cpu_sleep: cpu-sleep-0 {
 184                                 compatible = "arm,idle-state";
 185                                 local-timer-stop;
 186                                 arm,psci-suspend-param = <0x0010000>;
 187                                 entry-latency-us = <350>;
 188                                 exit-latency-us = <600>;
 189                                 min-residency-us = <1150>;
 190                         };
 191                 };
 192
 193                 /include/ "rk3399-sched-energy.dtsi"
 194
 195         };
 196
 197         cluster0_opp: opp_table0 {
 198                 compatible = "operating-points-v2";
 199                 opp-shared;
 200
 201                 opp@408000000 {
 202                         opp-hz = /bits/ 64 <408000000>;
 203                         opp-microvolt = <800000>;
 204                         clock-latency-ns = <40000>;
 205                 };
 206                 opp@600000000 {
 207                         opp-hz = /bits/ 64 <600000000>;
 208                         opp-microvolt = <800000>;
 209                 };
 210                 opp@816000000 {
 211                         opp-hz = /bits/ 64 <816000000>;
 212                         opp-microvolt = <800000>;
 213                 };
 214                 opp@1008000000 {
 215                         opp-hz = /bits/ 64 <1008000000>;
 216                         opp-microvolt = <875000>;
 217                 };
 218                 opp@1200000000 {
 219                         opp-hz = /bits/ 64 <1200000000>;
 220                         opp-microvolt = <925000>;
 221                 };
 222                 opp@1416000000 {
 223                         opp-hz = /bits/ 64 <1416000000>;
 224                         opp-microvolt = <1025000>;
 225                 };
 226         };
 227
 228         cluster1_opp: opp_table1 {
 229                 compatible = "operating-points-v2";
 230                 opp-shared;
 231
 232                 opp@408000000 {
 233                         opp-hz = /bits/ 64 <408000000>;
 234                         opp-microvolt = <800000>;
 235                         clock-latency-ns = <40000>;
 236                 };
 237                 opp@600000000 {
 238                         opp-hz = /bits/ 64 <600000000>;
 239                         opp-microvolt = <800000>;
 240                 };
 241                 opp@816000000 {
 242                         opp-hz = /bits/ 64 <816000000>;
 243                         opp-microvolt = <800000>;
 244                 };
 245                 opp@1008000000 {
 246                         opp-hz = /bits/ 64 <1008000000>;
 247                         opp-microvolt = <850000>;
 248                 };
 249                 opp@1200000000 {
 250                         opp-hz = /bits/ 64 <1200000000>;
 251                         opp-microvolt = <925000>;
 252                 };
 253         };
 254
 255         timer {
 256                 compatible = "arm,armv8-timer";
 257                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
 258                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
 259                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
 260                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
 261         };
 262
 263         pmu_a53 {
 264                 compatible = "arm,cortex-a53-pmu";
 265                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &part0>;
 266         };
 267
 268         pmu_a72 {
 269                 compatible = "arm,cortex-a72-pmu";
 270                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &part1>;
 271         };
 272
 273         xin24m: xin24m {
 274                 compatible = "fixed-clock";
 275                 #clock-cells = <0>;
 276                 clock-frequency = <24000000>;
 277                 clock-output-names = "xin24m";
 278         };
 279
 280         amba {
 281                 compatible = "arm,amba-bus";
 282                 #address-cells = <2>;
 283                 #size-cells = <2>;
 284                 ranges;
 285
 286                 dmac_bus: dma-controller@ff6d0000 {
 287                         compatible = "arm,pl330", "arm,primecell";
 288                         reg = <0x0 0xff6d0000 0x0 0x4000>;
 289                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
 290                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
 291                         #dma-cells = <1>;
 292                         clocks = <&cru ACLK_DMAC0_PERILP>;
 293                         clock-names = "apb_pclk";
 294                         peripherals-req-type-burst;
 295                 };
 296
 297                 dmac_peri: dma-controller@ff6e0000 {
 298                         compatible = "arm,pl330", "arm,primecell";
 299                         reg = <0x0 0xff6e0000 0x0 0x4000>;
 300                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
 301                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>;
 302                         #dma-cells = <1>;
 303                         clocks = <&cru ACLK_DMAC1_PERILP>;
 304                         clock-names = "apb_pclk";
 305                         peripherals-req-type-burst;
 306                 };
 307         };
 308
 309         gmac: eth@fe300000 {
 310                 compatible = "rockchip,rk3399-gmac";
 311                 reg = <0x0 0xfe300000 0x0 0x10000>;
 312                 rockchip,grf = <&grf>;
 313                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
 314                 interrupt-names = "macirq";
 315                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
 316                          <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
 317                          <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
 318                          <&cru PCLK_GMAC>;
 319                 clock-names = "stmmaceth", "mac_clk_rx",
 320                               "mac_clk_tx", "clk_mac_ref",
 321                               "clk_mac_refout", "aclk_mac",
 322                               "pclk_mac";
 323                 resets = <&cru SRST_A_GMAC>;
 324                 reset-names = "stmmaceth";
 325                 power-domains = <&power RK3399_PD_GMAC>;
 326                 status = "disabled";
 327         };
 328
 329         emmc_phy: phy {
 330                 compatible = "rockchip,rk3399-emmc-phy";
 331                 reg-offset = <0xf780>;
 332                 #phy-cells = <0>;
 333                 rockchip,grf = <&grf>;
 334                 ctrl-base = <0xfe330000>;
 335                 status = "disabled";
 336         };
 337
 338         sdio0: dwmmc@fe310000 {
 339                 compatible = "rockchip,rk3399-dw-mshc",
 340                              "rockchip,rk3288-dw-mshc";
 341                 reg = <0x0 0xfe310000 0x0 0x4000>;
 342                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>;
 343                 clock-freq-min-max = <400000 150000000>;
 344                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 345                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 346                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 347                 fifo-depth = <0x100>;
 348                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
 349                 status = "disabled";
 350         };
 351
 352         sdmmc: dwmmc@fe320000 {
 353                 compatible = "rockchip,rk3399-dw-mshc",
 354                              "rockchip,rk3288-dw-mshc";
 355                 reg = <0x0 0xfe320000 0x0 0x4000>;
 356                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
 357                 clock-freq-min-max = <400000 150000000>;
 358                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 359                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 360                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 361                 fifo-depth = <0x100>;
 362                 power-domains = <&power RK3399_PD_SD>;
 363                 status = "disabled";
 364         };
 365
 366         sdhci: sdhci@fe330000 {
 367                 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
 368                 reg = <0x0 0xfe330000 0x0 0x10000>;
 369                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
 370                 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
 371                 clock-names = "clk_xin", "clk_ahb";
 372                 assigned-clocks = <&cru SCLK_EMMC>;
 373                 assigned-clock-parents = <&cru PLL_CPLL>;
 374                 assigned-clock-rates = <200000000>;
 375                 phys = <&emmc_phy>;
 376                 phy-names = "phy_arasan";
 377                 power-domains = <&power RK3399_PD_EMMC>;
 378                 status = "disabled";
 379         };
 380
 381         usb_host0_ehci: usb@fe380000 {
 382                 compatible = "generic-ehci";
 383                 reg = <0x0 0xfe380000 0x0 0x20000>;
 384                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
 385                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 386                          <&cru SCLK_USBPHY0_480M_SRC>;
 387                 clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m";
 388                 phys = <&u2phy0_host>;
 389                 phy-names = "usb";
 390                 power-domains = <&power RK3399_PD_PERIHP>;
 391                 status = "disabled";
 392         };
 393
 394         usb_host0_ohci: usb@fe3a0000 {
 395                 compatible = "generic-ohci";
 396                 reg = <0x0 0xfe3a0000 0x0 0x20000>;
 397                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
 398                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 399                          <&cru SCLK_USBPHY0_480M_SRC>;
 400                 clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m";
 401                 phys = <&u2phy0_host>;
 402                 phy-names = "usb";
 403                 power-domains = <&power RK3399_PD_PERIHP>;
 404                 status = "disabled";
 405         };
 406
 407         usb_host1_ehci: usb@fe3c0000 {
 408                 compatible = "generic-ehci";
 409                 reg = <0x0 0xfe3c0000 0x0 0x20000>;
 410                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
 411                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
 412                          <&cru SCLK_USBPHY1_480M_SRC>;
 413                 clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m";
 414                 phys = <&u2phy1_host>;
 415                 phy-names = "usb";
 416                 power-domains = <&power RK3399_PD_PERIHP>;
 417                 status = "disabled";
 418         };
 419
 420         usb_host1_ohci: usb@fe3e0000 {
 421                 compatible = "generic-ohci";
 422                 reg = <0x0 0xfe3e0000 0x0 0x20000>;
 423                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
 424                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
 425                          <&cru SCLK_USBPHY1_480M_SRC>;
 426                 clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m";
 427                 phys = <&u2phy1_host>;
 428                 phy-names = "usb";
 429                 power-domains = <&power RK3399_PD_PERIHP>;
 430                 status = "disabled";
 431         };
 432
 433         usbdrd3_0: usb@fe800000 {
 434                 compatible = "rockchip,rk3399-dwc3";
 435                 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
 436                          <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
 437                          <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
 438                 clock-names = "clk_usb3otg0_ref", "clk_usb3otg0_suspend",
 439                               "aclk_usb3otg0", "aclk_usb3_rksoc_axi_perf",
 440                               "aclk_usb3", "aclk_usb3_grf";
 441                 power-domains = <&power RK3399_PD_USB3>;
 442                 resets = <&cru SRST_A_USB3_OTG0>;
 443                 reset-names = "usb3-otg";
 444                 #address-cells = <2>;
 445                 #size-cells = <2>;
 446                 ranges;
 447                 status = "disabled";
 448                 usbdrd_dwc3_0: dwc3@fe800000 {
 449                         compatible = "snps,dwc3";
 450                         reg = <0x0 0xfe800000 0x0 0x100000>;
 451                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
 452                         dr_mode = "otg";
 453                         phys = <&u2phy0_otg>;
 454                         phy-names = "usb2-phy";
 455                         phy_type = "utmi_wide";
 456                         snps,dis_enblslpm_quirk;
 457                         snps,dis-u2-freeclk-exists-quirk;
 458                         snps,dis-del-phy-power-chg-quirk;
 459                         snps,xhci-slow-suspend-quirk;
 460                         status = "disabled";
 461                 };
 462         };
 463
 464         usbdrd3_1: usb@fe900000 {
 465                 compatible = "rockchip,rk3399-dwc3";
 466                 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
 467                          <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
 468                          <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
 469                 clock-names = "clk_usb3otg1_ref", "clk_usb3otg1_suspend",
 470                               "aclk_usb3otg1", "aclk_usb3_rksoc_axi_perf",
 471                               "aclk_usb3", "aclk_usb3_grf";
 472                 power-domains = <&power RK3399_PD_USB3>;
 473                 resets = <&cru SRST_A_USB3_OTG1>;
 474                 reset-names = "usb3-otg";
 475                 #address-cells = <2>;
 476                 #size-cells = <2>;
 477                 ranges;
 478                 status = "disabled";
 479                 usbdrd_dwc3_1: dwc3@fe900000 {
 480                         compatible = "snps,dwc3";
 481                         reg = <0x0 0xfe900000 0x0 0x100000>;
 482                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
 483                         dr_mode = "otg";
 484                         phys = <&u2phy1_otg>;
 485                         phy-names = "usb2-phy";
 486                         phy_type = "utmi_wide";
 487                         snps,dis_enblslpm_quirk;
 488                         snps,dis-u2-freeclk-exists-quirk;
 489                         snps,dis-del-phy-power-chg-quirk;
 490                         snps,xhci-slow-suspend-quirk;
 491                         status = "disabled";
 492                 };
 493         };
 494
 495         gic: interrupt-controller@fee00000 {
 496                 compatible = "arm,gic-v3";
 497                 #interrupt-cells = <4>;
 498                 #address-cells = <2>;
 499                 #size-cells = <2>;
 500                 ranges;
 501                 interrupt-controller;
 502
 503                 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
 504                       <0x0 0xfef00000 0 0xc0000>, /* GICR */
 505                       <0x0 0xfff00000 0 0x10000>, /* GICC */
 506                       <0x0 0xfff10000 0 0x10000>, /* GICH */
 507                       <0x0 0xfff20000 0 0x10000>; /* GICV */
 508                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
 509                 its: interrupt-controller@fee20000 {
 510                         compatible = "arm,gic-v3-its";
 511                         msi-controller;
 512                         reg = <0x0 0xfee20000 0x0 0x20000>;
 513                 };
 514
 515                 ppi-partitions {
 516                         part0: interrupt-partition-0 {
 517                                 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
 518                         };
 519
 520                         part1: interrupt-partition-1 {
 521                                 affinity = <&cpu_b0 &cpu_b1>;
 522                         };
 523                 };
 524         };
 525
 526         saradc: saradc@ff100000 {
 527                 compatible = "rockchip,rk3399-saradc";
 528                 reg = <0x0 0xff100000 0x0 0x100>;
 529                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>;
 530                 #io-channel-cells = <1>;
 531                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 532                 clock-names = "saradc", "apb_pclk";
 533                 status = "disabled";
 534         };
 535
 536         i2c0: i2c@ff3c0000 {
 537                 compatible = "rockchip,rk3399-i2c";
 538                 reg = <0x0 0xff3c0000 0x0 0x1000>;
 539                 clocks =  <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
 540                 clock-names = "i2c", "pclk";
 541                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
 542                 pinctrl-names = "default";
 543                 pinctrl-0 = <&i2c0_xfer>;
 544                 #address-cells = <1>;
 545                 #size-cells = <0>;
 546                 status = "disabled";
 547         };
 548
 549         i2c1: i2c@ff110000 {
 550                 compatible = "rockchip,rk3399-i2c";
 551                 reg = <0x0 0xff110000 0x0 0x1000>;
 552                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 553                 clock-names = "i2c", "pclk";
 554                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>;
 555                 pinctrl-names = "default";
 556                 pinctrl-0 = <&i2c1_xfer>;
 557                 #address-cells = <1>;
 558                 #size-cells = <0>;
 559                 status = "disabled";
 560         };
 561
 562         i2c2: i2c@ff120000 {
 563                 compatible = "rockchip,rk3399-i2c";
 564                 reg = <0x0 0xff120000 0x0 0x1000>;
 565                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 566                 clock-names = "i2c", "pclk";
 567                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>;
 568                 pinctrl-names = "default";
 569                 pinctrl-0 = <&i2c2_xfer>;
 570                 #address-cells = <1>;
 571                 #size-cells = <0>;
 572                 status = "disabled";
 573         };
 574
 575         i2c3: i2c@ff130000 {
 576                 compatible = "rockchip,rk3399-i2c";
 577                 reg = <0x0 0xff130000 0x0 0x1000>;
 578                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 579                 clock-names = "i2c", "pclk";
 580                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>;
 581                 pinctrl-names = "default";
 582                 pinctrl-0 = <&i2c3_xfer>;
 583                 #address-cells = <1>;
 584                 #size-cells = <0>;
 585                 status = "disabled";
 586         };
 587
 588         i2c5: i2c@ff140000 {
 589                 compatible = "rockchip,rk3399-i2c";
 590                 reg = <0x0 0xff140000 0x0 0x1000>;
 591                 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
 592                 clock-names = "i2c", "pclk";
 593                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>;
 594                 pinctrl-names = "default";
 595                 pinctrl-0 = <&i2c5_xfer>;
 596                 #address-cells = <1>;
 597                 #size-cells = <0>;
 598                 status = "disabled";
 599         };
 600
 601         i2c6: i2c@ff150000 {
 602                 compatible = "rockchip,rk3399-i2c";
 603                 reg = <0x0 0xff150000 0x0 0x1000>;
 604                 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
 605                 clock-names = "i2c", "pclk";
 606                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>;
 607                 pinctrl-names = "default";
 608                 pinctrl-0 = <&i2c6_xfer>;
 609                 #address-cells = <1>;
 610                 #size-cells = <0>;
 611                 status = "disabled";
 612         };
 613
 614         i2c7: i2c@ff160000 {
 615                 compatible = "rockchip,rk3399-i2c";
 616                 reg = <0x0 0xff160000 0x0 0x1000>;
 617                 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
 618                 clock-names = "i2c", "pclk";
 619                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>;
 620                 pinctrl-names = "default";
 621                 pinctrl-0 = <&i2c7_xfer>;
 622                 #address-cells = <1>;
 623                 #size-cells = <0>;
 624                 status = "disabled";
 625         };
 626
 627         uart0: serial@ff180000 {
 628                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 629                 reg = <0x0 0xff180000 0x0 0x100>;
 630                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 631                 clock-names = "baudclk", "apb_pclk";
 632                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
 633                 reg-shift = <2>;
 634                 reg-io-width = <4>;
 635                 pinctrl-names = "default";
 636                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 637                 status = "disabled";
 638         };
 639
 640         uart1: serial@ff190000 {
 641                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 642                 reg = <0x0 0xff190000 0x0 0x100>;
 643                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 644                 clock-names = "baudclk", "apb_pclk";
 645                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>;
 646                 reg-shift = <2>;
 647                 reg-io-width = <4>;
 648                 pinctrl-names = "default";
 649                 pinctrl-0 = <&uart1_xfer>;
 650                 status = "disabled";
 651         };
 652
 653         uart2: serial@ff1a0000 {
 654                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 655                 reg = <0x0 0xff1a0000 0x0 0x100>;
 656                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 657                 clock-names = "baudclk", "apb_pclk";
 658                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
 659                 reg-shift = <2>;
 660                 reg-io-width = <4>;
 661                 pinctrl-names = "default";
 662                 pinctrl-0 = <&uart2c_xfer>;
 663                 status = "disabled";
 664         };
 665
 666         uart3: serial@ff1b0000 {
 667                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 668                 reg = <0x0 0xff1b0000 0x0 0x100>;
 669                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 670                 clock-names = "baudclk", "apb_pclk";
 671                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
 672                 reg-shift = <2>;
 673                 reg-io-width = <4>;
 674                 pinctrl-names = "default";
 675                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 676                 status = "disabled";
 677         };
 678
 679         spi0: spi@ff1c0000 {
 680                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 681                 reg = <0x0 0xff1c0000 0x0 0x1000>;
 682                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 683                 clock-names = "spiclk", "apb_pclk";
 684                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>;
 685                 pinctrl-names = "default";
 686                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 687                 #address-cells = <1>;
 688                 #size-cells = <0>;
 689                 status = "disabled";
 690         };
 691
 692         spi1: spi@ff1d0000 {
 693                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 694                 reg = <0x0 0xff1d0000 0x0 0x1000>;
 695                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 696                 clock-names = "spiclk", "apb_pclk";
 697                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>;
 698                 pinctrl-names = "default";
 699                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 700                 #address-cells = <1>;
 701                 #size-cells = <0>;
 702                 status = "disabled";
 703         };
 704
 705         spi2: spi@ff1e0000 {
 706                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 707                 reg = <0x0 0xff1e0000 0x0 0x1000>;
 708                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 709                 clock-names = "spiclk", "apb_pclk";
 710                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>;
 711                 pinctrl-names = "default";
 712                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 713                 #address-cells = <1>;
 714                 #size-cells = <0>;
 715                 status = "disabled";
 716         };
 717
 718         spi4: spi@ff1f0000 {
 719                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 720                 reg = <0x0 0xff1f0000 0x0 0x1000>;
 721                 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
 722                 clock-names = "spiclk", "apb_pclk";
 723                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>;
 724                 pinctrl-names = "default";
 725                 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
 726                 #address-cells = <1>;
 727                 #size-cells = <0>;
 728                 status = "disabled";
 729         };
 730
 731         spi5: spi@ff200000 {
 732                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 733                 reg = <0x0 0xff200000 0x0 0x1000>;
 734                 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
 735                 clock-names = "spiclk", "apb_pclk";
 736                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
 737                 pinctrl-names = "default";
 738                 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
 739                 #address-cells = <1>;
 740                 #size-cells = <0>;
 741                 status = "disabled";
 742         };
 743
 744         thermal-zones {
 745                 soc_thermal: soc-thermal {
 746                         polling-delay-passive = <20>; /* milliseconds */
 747                         polling-delay = <1000>; /* milliseconds */
 748                         sustainable-power = <1000>; /* milliwatts */
 749
 750                         thermal-sensors = <&tsadc 0>;
 751
 752                         trips {
 753                                 threshold: trip-point@0 {
 754                                         temperature = <70000>; /* millicelsius */
 755                                         hysteresis = <2000>; /* millicelsius */
 756                                         type = "passive";
 757                                 };
 758                                 target: trip-point@1 {
 759                                         temperature = <85000>; /* millicelsius */
 760                                         hysteresis = <2000>; /* millicelsius */
 761                                         type = "passive";
 762                                 };
 763                                 soc_crit: soc-crit {
 764                                         temperature = <95000>; /* millicelsius */
 765                                         hysteresis = <2000>; /* millicelsius */
 766                                         type = "critical";
 767                                 };
 768                         };
 769
 770                         cooling-maps {
 771                                 map0 {
 772                                         trip = <&target>;
 773                                         cooling-device =
 774                                                 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 775                                         contribution = <4096>;
 776                                 };
 777                                 map1 {
 778                                         trip = <&target>;
 779                                         cooling-device =
 780                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 781                                         contribution = <1024>;
 782                                 };
 783                                 map2 {
 784                                         trip = <&target>;
 785                                         cooling-device =
 786                                                 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 787                                         contribution = <4096>;
 788                                 };
 789                         };
 790                 };
 791
 792                 gpu_thermal: gpu-thermal {
 793                         polling-delay-passive = <100>; /* milliseconds */
 794                         polling-delay = <1000>; /* milliseconds */
 795
 796                         thermal-sensors = <&tsadc 1>;
 797                 };
 798         };
 799
 800         tsadc: tsadc@ff260000 {
 801                 compatible = "rockchip,rk3399-tsadc";
 802                 reg = <0x0 0xff260000 0x0 0x100>;
 803                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
 804                 rockchip,grf = <&grf>;
 805                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 806                 clock-names = "tsadc", "apb_pclk";
 807                 assigned-clocks = <&cru SCLK_TSADC>;
 808                 assigned-clock-rates = <750000>;
 809                 resets = <&cru SRST_TSADC>;
 810                 reset-names = "tsadc-apb";
 811                 pinctrl-names = "init", "default", "sleep";
 812                 pinctrl-0 = <&otp_gpio>;
 813                 pinctrl-1 = <&otp_out>;
 814                 pinctrl-2 = <&otp_gpio>;
 815                 #thermal-sensor-cells = <1>;
 816                 rockchip,hw-tshut-temp = <95000>;
 817                 status = "disabled";
 818         };
 819
 820         qos_emmc: qos@ffa58000 {
 821                 compatible = "syscon";
 822                 reg = <0x0 0xffa58000 0x0 0x20>;
 823         };
 824
 825         qos_gmac: qos@ffa5c000 {
 826                 compatible = "syscon";
 827                 reg = <0x0 0xffa5c000 0x0 0x20>;
 828         };
 829
 830         qos_pcie: qos@ffa60080 {
 831                 compatible = "syscon";
 832                 reg = <0x0 0xffa60080 0x0 0x20>;
 833         };
 834
 835         qos_usb_host0: qos@ffa60100 {
 836                 compatible = "syscon";
 837                 reg = <0x0 0xffa60100 0x0 0x20>;
 838         };
 839
 840         qos_usb_host1: qos@ffa60180 {
 841                 compatible = "syscon";
 842                 reg = <0x0 0xffa60180 0x0 0x20>;
 843         };
 844
 845         qos_usb_otg0: qos@ffa70000 {
 846                 compatible = "syscon";
 847                 reg = <0x0 0xffa70000 0x0 0x20>;
 848         };
 849
 850         qos_usb_otg1: qos@ffa70080 {
 851                 compatible = "syscon";
 852                 reg = <0x0 0xffa70080 0x0 0x20>;
 853         };
 854
 855         qos_sd: qos@ffa74000 {
 856                 compatible = "syscon";
 857                 reg = <0x0 0xffa74000 0x0 0x20>;
 858         };
 859
 860         qos_sdioaudio: qos@ffa76000 {
 861                 compatible = "syscon";
 862                 reg = <0x0 0xffa76000 0x0 0x20>;
 863         };
 864
 865         qos_hdcp: qos@ffa90000 {
 866                 compatible = "syscon";
 867                 reg = <0x0 0xffa90000 0x0 0x20>;
 868         };
 869
 870         qos_iep: qos@ffa98000 {
 871                 compatible = "syscon";
 872                 reg = <0x0 0xffa98000 0x0 0x20>;
 873         };
 874
 875         qos_isp0_m0: qos@ffaa0000 {
 876                 compatible = "syscon";
 877                 reg = <0x0 0xffaa0000 0x0 0x20>;
 878         };
 879
 880         qos_isp0_m1: qos@ffaa0080 {
 881                 compatible = "syscon";
 882                 reg = <0x0 0xffaa0080 0x0 0x20>;
 883         };
 884
 885         qos_isp1_m0: qos@ffaa8000 {
 886                 compatible = "syscon";
 887                 reg = <0x0 0xffaa8000 0x0 0x20>;
 888         };
 889
 890         qos_isp1_m1: qos@ffaa8080 {
 891                 compatible = "syscon";
 892                 reg = <0x0 0xffaa8080 0x0 0x20>;
 893         };
 894
 895         qos_rga_r: qos@ffab0000 {
 896                 compatible = "syscon";
 897                 reg = <0x0 0xffab0000 0x0 0x20>;
 898         };
 899
 900         qos_rga_w: qos@ffab0080 {
 901                 compatible = "syscon";
 902                 reg = <0x0 0xffab0080 0x0 0x20>;
 903         };
 904
 905         qos_video_m0: qos@ffab8000 {
 906                 compatible = "syscon";
 907                 reg = <0x0 0xffab8000 0x0 0x20>;
 908         };
 909
 910         qos_video_m1_r: qos@ffac0000 {
 911                 compatible = "syscon";
 912                 reg = <0x0 0xffac0000 0x0 0x20>;
 913         };
 914
 915         qos_video_m1_w: qos@ffac0080 {
 916                 compatible = "syscon";
 917                 reg = <0x0 0xffac0080 0x0 0x20>;
 918         };
 919
 920         qos_vop_big_r: qos@ffac8000 {
 921                 compatible = "syscon";
 922                 reg = <0x0 0xffac8000 0x0 0x20>;
 923         };
 924
 925         qos_vop_big_w: qos@ffac8080 {
 926                 compatible = "syscon";
 927                 reg = <0x0 0xffac8080 0x0 0x20>;
 928         };
 929
 930         qos_vop_little: qos@ffad0000 {
 931                 compatible = "syscon";
 932                 reg = <0x0 0xffad0000 0x0 0x20>;
 933         };
 934
 935         qos_perihp: qos@ffad8080 {
 936                 compatible = "syscon";
 937                 reg = <0x0 0xffad8080 0x0 0x20>;
 938         };
 939
 940         qos_gpu: qos@ffae0000 {
 941                 compatible = "syscon";
 942                 reg = <0x0 0xffae0000 0x0 0x20>;
 943         };
 944
 945         pmu: power-management@ff310000 {
 946                 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
 947                 reg = <0x0 0xff310000 0x0 0x1000>;
 948
 949                 /*
 950                  * Note: RK3399 supports 6 voltage domains including VD_CORE_L,
 951                  * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
 952                  * Some of the power domains are grouped together for every
 953                  * voltage domain.
 954                  * The detail contents as below.
 955                  */
 956                 power: power-controller {
 957                         compatible = "rockchip,rk3399-power-controller";
 958                         #power-domain-cells = <1>;
 959                         #address-cells = <1>;
 960                         #size-cells = <0>;
 961
 962                         /* These power domains are grouped by VD_CENTER */
 963                         pd_iep@RK3399_PD_IEP {
 964                                 reg = <RK3399_PD_IEP>;
 965                                 clocks = <&cru ACLK_IEP>,
 966                                          <&cru HCLK_IEP>;
 967                                 pm_qos = <&qos_iep>;
 968                         };
 969                         pd_rga@RK3399_PD_RGA {
 970                                 reg = <RK3399_PD_RGA>;
 971                                 clocks = <&cru ACLK_RGA>,
 972                                          <&cru HCLK_RGA>;
 973                                 pm_qos = <&qos_rga_r>,
 974                                          <&qos_rga_w>;
 975                         };
 976                         pd_vcodec@RK3399_PD_VCODEC {
 977                                 reg = <RK3399_PD_VCODEC>;
 978                                 clocks = <&cru ACLK_VCODEC>,
 979                                          <&cru HCLK_VCODEC>;
 980                                 pm_qos = <&qos_video_m0>;
 981                         };
 982                         pd_vdu@RK3399_PD_VDU {
 983                                 reg = <RK3399_PD_VDU>;
 984                                 clocks = <&cru ACLK_VDU>,
 985                                          <&cru HCLK_VDU>;
 986                                 pm_qos = <&qos_video_m1_r>,
 987                                          <&qos_video_m1_w>;
 988                         };
 989
 990                         /* These power domains are grouped by VD_GPU */
 991                         pd_gpu@RK3399_PD_GPU {
 992                                 reg = <RK3399_PD_GPU>;
 993                                 clocks = <&cru ACLK_GPU>;
 994                                 pm_qos = <&qos_gpu>;
 995                         };
 996
 997                         /* These power domains are grouped by VD_LOGIC */
 998                         pd_emmc@RK3399_PD_EMMC {
 999                                 reg = <RK3399_PD_EMMC>;
1000                                 clocks = <&cru ACLK_EMMC>;
1001                                 pm_qos = <&qos_emmc>;
1002                         };
1003                         pd_gmac@RK3399_PD_GMAC {
1004                                 reg = <RK3399_PD_GMAC>;
1005                                 clocks = <&cru ACLK_GMAC>;
1006                                 pm_qos = <&qos_gmac>;
1007                         };
1008                         pd_perihp@RK3399_PD_PERIHP {
1009                                 reg = <RK3399_PD_PERIHP>;
1010                                 #address-cells = <1>;
1011                                 #size-cells = <0>;
1012                                 clocks = <&cru ACLK_PERIHP>;
1013                                 pm_qos = <&qos_perihp>,
1014                                          <&qos_pcie>,
1015                                          <&qos_usb_host0>,
1016                                          <&qos_usb_host1>;
1017
1018                                 pd_sd@RK3399_PD_SD {
1019                                         reg = <RK3399_PD_SD>;
1020                                         clocks = <&cru HCLK_SDMMC>,
1021                                                  <&cru SCLK_SDMMC>;
1022                                         pm_qos = <&qos_sd>;
1023                                 };
1024                         };
1025                         pd_sdioaudio@RK3399_PD_SDIOAUDIO {
1026                                 reg = <RK3399_PD_SDIOAUDIO>;
1027                                 clocks = <&cru HCLK_SDIO>;
1028                                 pm_qos = <&qos_sdioaudio>;
1029                         };
1030                         pd_usb3@RK3399_PD_USB3 {
1031                                 reg = <RK3399_PD_USB3>;
1032                                 clocks = <&cru ACLK_USB3>;
1033                                 pm_qos = <&qos_usb_otg0>,
1034                                          <&qos_usb_otg1>;
1035                         };
1036                         pd_vio@RK3399_PD_VIO {
1037                                 reg = <RK3399_PD_VIO>;
1038                                 #address-cells = <1>;
1039                                 #size-cells = <0>;
1040
1041                                 pd_hdcp@RK3399_PD_HDCP {
1042                                         reg = <RK3399_PD_HDCP>;
1043                                         clocks = <&cru ACLK_HDCP>,
1044                                                  <&cru HCLK_HDCP>,
1045                                                  <&cru PCLK_HDCP>;
1046                                         pm_qos = <&qos_hdcp>;
1047                                 };
1048                                 pd_isp0@RK3399_PD_ISP0 {
1049                                         reg = <RK3399_PD_ISP0>;
1050                                         clocks = <&cru ACLK_ISP0>,
1051                                                  <&cru HCLK_ISP0>;
1052                                         pm_qos = <&qos_isp0_m0>,
1053                                                  <&qos_isp0_m1>;
1054                                 };
1055                                 pd_isp1@RK3399_PD_ISP1 {
1056                                         reg = <RK3399_PD_ISP1>;
1057                                         clocks = <&cru ACLK_ISP1>,
1058                                                  <&cru HCLK_ISP1>;
1059                                         pm_qos = <&qos_isp1_m0>,
1060                                                  <&qos_isp1_m1>;
1061                                 };
1062                                 pd_vo@RK3399_PD_VO {
1063                                         reg = <RK3399_PD_VO>;
1064                                         #address-cells = <1>;
1065                                         #size-cells = <0>;
1066
1067                                         pd_vopb@RK3399_PD_VOPB {
1068                                                 reg = <RK3399_PD_VOPB>;
1069                                                 clocks = <&cru ACLK_VOP0>,
1070                                                          <&cru HCLK_VOP0>;
1071                                                 pm_qos = <&qos_vop_big_r>,
1072                                                          <&qos_vop_big_w>;
1073                                         };
1074                                         pd_vopl@RK3399_PD_VOPL {
1075                                                 reg = <RK3399_PD_VOPL>;
1076                                                 clocks = <&cru ACLK_VOP1>,
1077                                                          <&cru HCLK_VOP1>;
1078                                                 pm_qos = <&qos_vop_little>;
1079                                         };
1080                                 };
1081                         };
1082                 };
1083         };
1084
1085         pmugrf: syscon@ff320000 {
1086                 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
1087                 reg = <0x0 0xff320000 0x0 0x1000>;
1088
1089                 reboot-mode {
1090                         compatible = "syscon-reboot-mode";
1091                         offset = <0x300>;
1092                         mode-bootloader = <BOOT_LOADER>;
1093                         mode-charge = <BOOT_CHARGING>;
1094                         mode-fastboot = <BOOT_FASTBOOT>;
1095                         mode-loader = <BOOT_LOADER>;
1096                         mode-normal = <BOOT_NORMAL>;
1097                         mode-recovery = <BOOT_RECOVERY>;
1098                 };
1099         };
1100
1101         spi3: spi@ff350000 {
1102                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
1103                 reg = <0x0 0xff350000 0x0 0x1000>;
1104                 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
1105                 clock-names = "spiclk", "apb_pclk";
1106                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>;
1107                 pinctrl-names = "default";
1108                 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
1109                 #address-cells = <1>;
1110                 #size-cells = <0>;
1111                 status = "disabled";
1112         };
1113
1114         uart4: serial@ff370000 {
1115                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
1116                 reg = <0x0 0xff370000 0x0 0x100>;
1117                 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
1118                 clock-names = "baudclk", "apb_pclk";
1119                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>;
1120                 reg-shift = <2>;
1121                 reg-io-width = <4>;
1122                 pinctrl-names = "default";
1123                 pinctrl-0 = <&uart4_xfer>;
1124                 status = "disabled";
1125         };
1126
1127         i2c4: i2c@ff3d0000 {
1128                 compatible = "rockchip,rk3399-i2c";
1129                 reg = <0x0 0xff3d0000 0x0 0x1000>;
1130                 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
1131                 clock-names = "i2c", "pclk";
1132                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>;
1133                 pinctrl-names = "default";
1134                 pinctrl-0 = <&i2c4_xfer>;
1135                 #address-cells = <1>;
1136                 #size-cells = <0>;
1137                 status = "disabled";
1138         };
1139
1140         i2c8: i2c@ff3e0000 {
1141                 compatible = "rockchip,rk3399-i2c";
1142                 reg = <0x0 0xff3e0000 0x0 0x1000>;
1143                 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
1144                 clock-names = "i2c", "pclk";
1145                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
1146                 pinctrl-names = "default";
1147                 pinctrl-0 = <&i2c8_xfer>;
1148                 #address-cells = <1>;
1149                 #size-cells = <0>;
1150                 status = "disabled";
1151         };
1152
1153         pcie0: pcie@f8000000 {
1154                 compatible = "rockchip,rk3399-pcie";
1155                 #address-cells = <3>;
1156                 #size-cells = <2>;
1157                 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
1158                          <&cru PCLK_PCIE>, <&cru SCLK_PCIEPHY_REF>;
1159                 clock-names = "aclk_pcie", "aclk_perf_pcie",
1160                               "hclk_pcie", "clk_pciephy_ref";
1161                 bus-range = <0x0 0x1>;
1162                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
1163                              <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
1164                              <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
1165                 interrupt-names = "pcie-sys", "pcie-legacy", "pcie-client";
1166                 ranges = < 0x82000000 0 0xfa000000 0x0 0xfa000000 0 0x600000
1167                            0x81000000 0 0xfa600000 0x0 0xfa600000 0 0x100000 >;
1168                 reg = < 0x0 0xf8000000 0x0 0x2000000 >,
1169                       < 0x0 0xfd000000 0x0 0x1000000 >;
1170                 reg-name = "axi-base", "apb-base";
1171                 resets = <&cru SRST_PCIEPHY>, <&cru SRST_PCIE_CORE>,
1172                          <&cru SRST_PCIE_MGMT>, <&cru SRST_PCIE_MGMT_STICKY>,
1173                          <&cru SRST_PCIE_PIPE>;
1174                 reset-names = "phy-rst", "core-rst", "mgmt-rst",
1175                               "mgmt-sticky-rst", "pipe-rst";
1176                 rockchip,grf = <&grf>;
1177                 pcie-conf = <0xe220>;
1178                 pcie-status = <0xe2a4>;
1179                 pcie-laneoff = <0xe214>;
1180                 power-domains = <&power RK3399_PD_PERIHP>;
1181                 msi-parent = <&its>;
1182                 #interrupt-cells = <1>;
1183                 interrupt-map-mask = <0 0 0 7>;
1184                 interrupt-map = <0 0 0 1 &pcie0 1>,
1185                                 <0 0 0 2 &pcie0 2>,
1186                                 <0 0 0 3 &pcie0 3>,
1187                                 <0 0 0 4 &pcie0 4>;
1188                 status = "disabled";
1189                 pcie_intc: interrupt-controller {
1190                         interrupt-controller;
1191                         #address-cells = <0>;
1192                         #interrupt-cells = <1>;
1193                 };
1194         };
1195
1196         pwm0: pwm@ff420000 {
1197                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1198                 reg = <0x0 0xff420000 0x0 0x10>;
1199                 #pwm-cells = <3>;
1200                 pinctrl-names = "default";
1201                 pinctrl-0 = <&pwm0_pin>;
1202                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1203                 clock-names = "pwm";
1204                 status = "disabled";
1205         };
1206
1207         pwm1: pwm@ff420010 {
1208                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1209                 reg = <0x0 0xff420010 0x0 0x10>;
1210                 #pwm-cells = <3>;
1211                 pinctrl-names = "default";
1212                 pinctrl-0 = <&pwm1_pin>;
1213                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1214                 clock-names = "pwm";
1215                 status = "disabled";
1216         };
1217
1218         pwm2: pwm@ff420020 {
1219                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1220                 reg = <0x0 0xff420020 0x0 0x10>;
1221                 #pwm-cells = <3>;
1222                 pinctrl-names = "default";
1223                 pinctrl-0 = <&pwm2_pin>;
1224                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1225                 clock-names = "pwm";
1226                 status = "disabled";
1227         };
1228
1229         pwm3: pwm@ff420030 {
1230                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1231                 reg = <0x0 0xff420030 0x0 0x10>;
1232                 #pwm-cells = <3>;
1233                 pinctrl-names = "default";
1234                 pinctrl-0 = <&pwm3a_pin>;
1235                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1236                 clock-names = "pwm";
1237                 status = "disabled";
1238         };
1239
1240         rga: rga@ff680000 {
1241                 compatible = "rockchip,rk3399-rga";
1242                 reg = <0x0 0xff680000 0x0 0x10000>;
1243                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
1244                 interrupt-names = "rga";
1245                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
1246                 clock-names = "aclk", "hclk", "sclk";
1247                 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
1248                 reset-names = "core", "axi", "ahb";
1249                 power-domains = <&power RK3399_PD_RGA>;
1250                 status = "disabled";
1251         };
1252
1253         pmucru: pmu-clock-controller@ff750000 {
1254                 compatible = "rockchip,rk3399-pmucru";
1255                 reg = <0x0 0xff750000 0x0 0x1000>;
1256                 #clock-cells = <1>;
1257                 #reset-cells = <1>;
1258                 assigned-clocks = <&pmucru PLL_PPLL>;
1259                 assigned-clock-rates = <676000000>;
1260         };
1261
1262         cru: clock-controller@ff760000 {
1263                 compatible = "rockchip,rk3399-cru";
1264                 reg = <0x0 0xff760000 0x0 0x1000>;
1265                 #clock-cells = <1>;
1266                 #reset-cells = <1>;
1267                 assigned-clocks =
1268                         <&cru ACLK_VOP0>, <&cru HCLK_VOP0>,
1269                         <&cru ACLK_VOP1>, <&cru HCLK_VOP1>,
1270                         <&cru ARMCLKL>, <&cru ARMCLKB>,
1271                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1272                         <&cru PLL_NPLL>,
1273                         <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1274                         <&cru PCLK_PERIHP>,
1275                         <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1276                         <&cru PCLK_PERILP0>,
1277                         <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
1278                 assigned-clock-rates =
1279                          <400000000>,  <200000000>,
1280                          <400000000>,  <200000000>,
1281                          <816000000>, <816000000>,
1282                          <594000000>,  <800000000>,
1283                         <1000000000>,
1284                          <150000000>,   <75000000>,
1285                           <37500000>,
1286                          <100000000>,  <100000000>,
1287                           <50000000>,
1288                          <100000000>,   <50000000>;
1289         };
1290
1291         grf: syscon@ff770000 {
1292                 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
1293                 reg = <0x0 0xff770000 0x0 0x10000>;
1294                 #address-cells = <1>;
1295                 #size-cells = <1>;
1296
1297                 u2phy0: usb2-phy@e450 {
1298                         compatible = "rockchip,rk3399-usb2phy";
1299                         reg = <0xe450 0x10>;
1300                         clocks = <&cru SCLK_USB2PHY0_REF>;
1301                         clock-names = "phyclk";
1302                         #clock-cells = <0>;
1303                         clock-output-names = "clk_usbphy0_480m";
1304                         status = "disabled";
1305
1306                         u2phy0_otg: otg-port {
1307                                 #phy-cells = <0>;
1308                                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
1309                                              <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
1310                                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
1311                                 interrupt-names = "otg-bvalid", "otg-id",
1312                                                   "linestate";
1313                                 status = "disabled";
1314                         };
1315
1316                         u2phy0_host: host-port {
1317                                 #phy-cells = <0>;
1318                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
1319                                 interrupt-names = "linestate";
1320                                 status = "disabled";
1321                         };
1322                 };
1323
1324                 u2phy1: usb2-phy@e460 {
1325                         compatible = "rockchip,rk3399-usb2phy";
1326                         reg = <0xe460 0x10>;
1327                         clocks = <&cru SCLK_USB2PHY1_REF>;
1328                         clock-names = "phyclk";
1329                         #clock-cells = <0>;
1330                         clock-output-names = "clk_usbphy1_480m";
1331                         status = "disabled";
1332
1333                         u2phy1_otg: otg-port {
1334                                 #phy-cells = <0>;
1335                                 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
1336                                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
1337                                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1338                                 interrupt-names = "otg-bvalid", "otg-id",
1339                                                   "linestate";
1340                                 status = "disabled";
1341                         };
1342
1343                         u2phy1_host: host-port {
1344                                 #phy-cells = <0>;
1345                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
1346                                 interrupt-names = "linestate";
1347                                 status = "disabled";
1348                         };
1349                 };
1350         };
1351
1352         tcphy0: phy@ff7c0000 {
1353                 compatible = "rockchip,rk3399-typec-phy";
1354                 reg = <0x0 0xff7c0000 0x0 0x40000>;
1355                 rockchip,grf = <&grf>;
1356                 #phy-cells = <1>;
1357                 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1358                          <&cru SCLK_UPHY0_TCPDPHY_REF>;
1359                 clock-names = "tcpdcore", "tcpdphy-ref";
1360                 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
1361                 assigned-clock-rates = <50000000>;
1362                 resets = <&cru SRST_UPHY0>,
1363                          <&cru SRST_UPHY0_PIPE_L00>,
1364                          <&cru SRST_P_UPHY0_TCPHY>;
1365                 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1366                 rockchip,typec-conn-dir = <0xe580 0 16>;
1367                 rockchip,usb3tousb2-en = <0xe580 3 19>;
1368                 rockchip,external-psm = <0xe588 14 30>;
1369                 rockchip,pipe-status = <0xe5c0 0 0>;
1370                 rockchip,uphy-dp-sel = <0x6268 19 19>;
1371                 status = "disabled";
1372         };
1373
1374         tcphy1: phy@ff800000 {
1375                 compatible = "rockchip,rk3399-typec-phy";
1376                 reg = <0x0 0xff800000 0x0 0x40000>;
1377                 rockchip,grf = <&grf>;
1378                 #phy-cells = <1>;
1379                 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1380                          <&cru SCLK_UPHY1_TCPDPHY_REF>;
1381                 clock-names = "tcpdcore", "tcpdphy-ref";
1382                 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
1383                 assigned-clock-rates = <50000000>;
1384                 resets = <&cru SRST_UPHY1>,
1385                          <&cru SRST_UPHY1_PIPE_L00>,
1386                          <&cru SRST_P_UPHY1_TCPHY>;
1387                 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1388                 rockchip,typec-conn-dir = <0xe58c 0 16>;
1389                 rockchip,usb3tousb2-en = <0xe58c 3 19>;
1390                 rockchip,external-psm = <0xe594 14 30>;
1391                 rockchip,pipe-status = <0xe5c0 16 16>;
1392                 rockchip,uphy-dp-sel = <0x6268 3 19>;
1393                 status = "disabled";
1394         };
1395
1396         watchdog@ff840000 {
1397                 compatible = "snps,dw-wdt";
1398                 reg = <0x0 0xff840000 0x0 0x100>;
1399                 clocks = <&cru PCLK_WDT>;
1400                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
1401         };
1402
1403         rktimer: rktimer@ff850000 {
1404                 compatible = "rockchip,rk3399-timer";
1405                 reg = <0x0 0xff850000 0x0 0x1000>;
1406                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
1407                 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1408                 clock-names = "pclk", "timer";
1409         };
1410
1411         spdif: spdif@ff870000 {
1412                 compatible = "rockchip,rk3399-spdif";
1413                 reg = <0x0 0xff870000 0x0 0x1000>;
1414                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
1415                 dmas = <&dmac_bus 7>;
1416                 dma-names = "tx";
1417                 clock-names = "mclk", "hclk";
1418                 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1419                 pinctrl-names = "default";
1420                 pinctrl-0 = <&spdif_bus>;
1421                 status = "disabled";
1422         };
1423
1424         i2s0: i2s@ff880000 {
1425                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1426                 reg = <0x0 0xff880000 0x0 0x1000>;
1427                 rockchip,grf = <&grf>;
1428                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>;
1429                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1430                 dma-names = "tx", "rx";
1431                 clock-names = "i2s_clk", "i2s_hclk";
1432                 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1433                 pinctrl-names = "default";
1434                 pinctrl-0 = <&i2s0_8ch_bus>;
1435                 status = "disabled";
1436         };
1437
1438         i2s1: i2s@ff890000 {
1439                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1440                 reg = <0x0 0xff890000 0x0 0x1000>;
1441                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>;
1442                 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1443                 dma-names = "tx", "rx";
1444                 clock-names = "i2s_clk", "i2s_hclk";
1445                 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1446                 pinctrl-names = "default";
1447                 pinctrl-0 = <&i2s1_2ch_bus>;
1448                 status = "disabled";
1449         };
1450
1451         i2s2: i2s@ff8a0000 {
1452                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1453                 reg = <0x0 0xff8a0000 0x0 0x1000>;
1454                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>;
1455                 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1456                 dma-names = "tx", "rx";
1457                 clock-names = "i2s_clk", "i2s_hclk";
1458                 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1459                 status = "disabled";
1460         };
1461
1462         gpu: gpu@ff9a0000 {
1463                 compatible = "arm,malit860",
1464                              "arm,malit86x",
1465                              "arm,malit8xx",
1466                              "arm,mali-midgard";
1467
1468                 reg = <0x0 0xff9a0000 0x0 0x10000>;
1469
1470                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>,
1471                              <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
1472                              <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>;
1473                 interrupt-names = "GPU", "JOB", "MMU";
1474
1475                 clocks = <&cru ACLK_GPU>;
1476                 clock-names = "clk_mali";
1477                 #cooling-cells = <2>; /* min followed by max */
1478                 operating-points-v2 = <&gpu_opp_table>;
1479                 power-domains = <&power RK3399_PD_GPU>;
1480                 power-off-delay-ms = <200>;
1481                 status = "disabled";
1482
1483                 gpu_power_model: power_model {
1484                         compatible = "arm,mali-simple-power-model";
1485                         voltage = <900>;
1486                         frequency = <500>;
1487                         static-power = <300>;
1488                         dynamic-power = <396>;
1489                         ts = <32000 4700 (-80) 2>;
1490                         thermal-zone = "gpu-thermal";
1491                 };
1492         };
1493
1494         gpu_opp_table: gpu_opp_table {
1495                 compatible = "operating-points-v2";
1496                 opp-shared;
1497
1498                 opp@200000000 {
1499                         opp-hz = /bits/ 64 <200000000>;
1500                         opp-microvolt = <900000>;
1501                 };
1502                 opp@300000000 {
1503                         opp-hz = /bits/ 64 <300000000>;
1504                         opp-microvolt = <900000>;
1505                 };
1506                 opp@400000000 {
1507                         opp-hz = /bits/ 64 <400000000>;
1508                         opp-microvolt = <900000>;
1509                 };
1510
1511         };
1512
1513         vopl: vop@ff8f0000 {
1514                 compatible = "rockchip,rk3399-vop-lit";
1515                 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1516                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1517                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1518                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1519                 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1520                 reset-names = "axi", "ahb", "dclk";
1521                 power-domains = <&power RK3399_PD_VOPL>;
1522                 iommus = <&vopl_mmu>;
1523                 status = "disabled";
1524
1525                 vopl_out: port {
1526                         #address-cells = <1>;
1527                         #size-cells = <0>;
1528
1529                         vopl_out_mipi: endpoint@0 {
1530                                 reg = <0>;
1531                                 remote-endpoint = <&mipi_in_vopl>;
1532                         };
1533
1534                         vopl_out_edp: endpoint@1 {
1535                                 reg = <1>;
1536                                 remote-endpoint = <&edp_in_vopl>;
1537                         };
1538
1539                         vopl_out_hdmi: endpoint@2 {
1540                                 reg = <2>;
1541                                 remote-endpoint = <&hdmi_in_vopl>;
1542                         };
1543                 };
1544         };
1545
1546         vop1_pwm: voppwm@ff8f01a0 {
1547                 compatible = "rockchip,vop-pwm";
1548                 reg = <0x0 0xff8f01a0 0x0 0x10>;
1549                 #pwm-cells = <3>;
1550                 pinctrl-names = "default";
1551                 pinctrl-0 = <&vop1_pwm_pin>;
1552                 clocks = <&cru SCLK_VOP1_PWM>;
1553                 clock-names = "pwm";
1554                 status = "disabled";
1555         };
1556
1557         vopl_mmu: iommu@ff8f3f00 {
1558                 compatible = "rockchip,iommu";
1559                 reg = <0x0 0xff8f3f00 0x0 0x100>;
1560                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1561                 interrupt-names = "vopl_mmu";
1562                 #iommu-cells = <0>;
1563                 status = "disabled";
1564         };
1565
1566         vopb: vop@ff900000 {
1567                 compatible = "rockchip,rk3399-vop-big";
1568                 reg = <0x0 0xff900000 0x0 0x3efc>;
1569                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1570                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1571                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1572                 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1573                 reset-names = "axi", "ahb", "dclk";
1574                 power-domains = <&power RK3399_PD_VOPB>;
1575                 iommus = <&vopb_mmu>;
1576                 status = "disabled";
1577
1578                 vopb_out: port {
1579                         #address-cells = <1>;
1580                         #size-cells = <0>;
1581
1582                         vopb_out_edp: endpoint@0 {
1583                                 reg = <0>;
1584                                 remote-endpoint = <&edp_in_vopb>;
1585                         };
1586
1587                         vopb_out_mipi: endpoint@1 {
1588                                 reg = <1>;
1589                                 remote-endpoint = <&mipi_in_vopb>;
1590                         };
1591
1592                         vopb_out_hdmi: endpoint@2 {
1593                                 reg = <2>;
1594                                 remote-endpoint = <&hdmi_in_vopb>;
1595                         };
1596                 };
1597         };
1598
1599         vop0_pwm: voppwm@ff9001a0 {
1600                 compatible = "rockchip,vop-pwm";
1601                 reg = <0x0 0xff9001a0 0x0 0x10>;
1602                 #pwm-cells = <3>;
1603                 pinctrl-names = "default";
1604                 pinctrl-0 = <&vop0_pwm_pin>;
1605                 clocks = <&cru SCLK_VOP0_PWM>;
1606                 clock-names = "pwm";
1607                 status = "disabled";
1608         };
1609
1610         vopb_mmu: iommu@ff903f00 {
1611                 compatible = "rockchip,iommu";
1612                 reg = <0x0 0xff903f00 0x0 0x100>;
1613                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1614                 interrupt-names = "vopb_mmu";
1615                 #iommu-cells = <0>;
1616                 status = "disabled";
1617         };
1618
1619         hdmi: hdmi@ff940000 {
1620                 compatible = "rockchip,rk3399-dw-hdmi";
1621                 reg = <0x0 0xff940000 0x0 0x20000>;
1622                 reg-io-width = <4>;
1623                 rockchip,grf = <&grf>;
1624                 power-domains = <&power RK3399_PD_HDCP>;
1625                 pinctrl-names = "default";
1626                 pinctrl-0 = <&hdmi_i2c_xfer>;
1627                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
1628                 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_SFR>, <&cru SCLK_HDMI_SFR>, <&cru PCLK_EDP_CTRL>;
1629                 clock-names = "iahb", "isfr", "vpll", "grf";
1630                 status = "disabled";
1631
1632                 ports {
1633                         hdmi_in: port {
1634                                 #address-cells = <1>;
1635                                 #size-cells = <0>;
1636                                 hdmi_in_vopb: endpoint@0 {
1637                                         reg = <0>;
1638                                         remote-endpoint = <&vopb_out_hdmi>;
1639                                 };
1640                                 hdmi_in_vopl: endpoint@1 {
1641                                         reg = <1>;
1642                                         remote-endpoint = <&vopl_out_hdmi>;
1643                                 };
1644                         };
1645                 };
1646         };
1647
1648         mipi_dsi: mipi@ff960000 {
1649                 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1650                 reg = <0x0 0xff960000 0x0 0x8000>;
1651                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
1652                 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
1653                          <&cru SCLK_DPHY_TX0_CFG>;
1654                 clock-names = "ref", "pclk", "phy_cfg";
1655                 power-domains = <&power RK3399_PD_VIO>;
1656                 rockchip,grf = <&grf>;
1657                 #address-cells = <1>;
1658                 #size-cells = <0>;
1659                 status = "disabled";
1660
1661                 ports {
1662                         #address-cells = <1>;
1663                         #size-cells = <0>;
1664                         reg = <1>;
1665
1666                         mipi_in: port {
1667                                 #address-cells = <1>;
1668                                 #size-cells = <0>;
1669
1670                                 mipi_in_vopb: endpoint@0 {
1671                                         reg = <0>;
1672                                         remote-endpoint = <&vopb_out_mipi>;
1673                                 };
1674                                 mipi_in_vopl: endpoint@1 {
1675                                         reg = <1>;
1676                                         remote-endpoint = <&vopl_out_mipi>;
1677                                 };
1678                         };
1679                 };
1680         };
1681
1682         edp: edp@ff970000 {
1683                 compatible = "rockchip,rk3399-edp";
1684                 reg = <0x0 0xff970000 0x0 0x8000>;
1685                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
1686                 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1687                 clock-names = "dp", "pclk";
1688                 resets = <&cru SRST_P_EDP_CTRL>;
1689                 reset-names = "dp";
1690                 rockchip,grf = <&grf>;
1691                 status = "disabled";
1692                 pinctrl-names = "default";
1693                 pinctrl-0 = <&edp_hpd>;
1694
1695                 ports {
1696                         #address-cells = <1>;
1697                         #size-cells = <0>;
1698
1699                         edp_in: port@0 {
1700                                 reg = <0>;
1701                                 #address-cells = <1>;
1702                                 #size-cells = <0>;
1703
1704                                 edp_in_vopb: endpoint@0 {
1705                                         reg = <0>;
1706                                         remote-endpoint = <&vopb_out_edp>;
1707                                 };
1708
1709                                 edp_in_vopl: endpoint@1 {
1710                                         reg = <1>;
1711                                         remote-endpoint = <&vopl_out_edp>;
1712                                 };
1713                         };
1714                 };
1715         };
1716
1717         display_subsystem: display-subsystem {
1718                 compatible = "rockchip,display-subsystem";
1719                 ports = <&vopl_out>, <&vopb_out>;
1720                 status = "disabled";
1721         };
1722
1723         pinctrl: pinctrl {
1724                 compatible = "rockchip,rk3399-pinctrl";
1725                 rockchip,grf = <&grf>;
1726                 rockchip,pmu = <&pmugrf>;
1727                 #address-cells = <0x2>;
1728                 #size-cells = <0x2>;
1729                 ranges;
1730
1731                 gpio0: gpio0@ff720000 {
1732                         compatible = "rockchip,gpio-bank";
1733                         reg = <0x0 0xff720000 0x0 0x100>;
1734                         clocks = <&pmucru PCLK_GPIO0_PMU>;
1735                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
1736
1737                         gpio-controller;
1738                         #gpio-cells = <0x2>;
1739
1740                         interrupt-controller;
1741                         #interrupt-cells = <0x2>;
1742                 };
1743
1744                 gpio1: gpio1@ff730000 {
1745                         compatible = "rockchip,gpio-bank";
1746                         reg = <0x0 0xff730000 0x0 0x100>;
1747                         clocks = <&pmucru PCLK_GPIO1_PMU>;
1748                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
1749
1750                         gpio-controller;
1751                         #gpio-cells = <0x2>;
1752
1753                         interrupt-controller;
1754                         #interrupt-cells = <0x2>;
1755                 };
1756
1757                 gpio2: gpio2@ff780000 {
1758                         compatible = "rockchip,gpio-bank";
1759                         reg = <0x0 0xff780000 0x0 0x100>;
1760                         clocks = <&cru PCLK_GPIO2>;
1761                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>;
1762
1763                         gpio-controller;
1764                         #gpio-cells = <0x2>;
1765
1766                         interrupt-controller;
1767                         #interrupt-cells = <0x2>;
1768                 };
1769
1770                 gpio3: gpio3@ff788000 {
1771                         compatible = "rockchip,gpio-bank";
1772                         reg = <0x0 0xff788000 0x0 0x100>;
1773                         clocks = <&cru PCLK_GPIO3>;
1774                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
1775
1776                         gpio-controller;
1777                         #gpio-cells = <0x2>;
1778
1779                         interrupt-controller;
1780                         #interrupt-cells = <0x2>;
1781                 };
1782
1783                 gpio4: gpio4@ff790000 {
1784                         compatible = "rockchip,gpio-bank";
1785                         reg = <0x0 0xff790000 0x0 0x100>;
1786                         clocks = <&cru PCLK_GPIO4>;
1787                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
1788
1789                         gpio-controller;
1790                         #gpio-cells = <0x2>;
1791
1792                         interrupt-controller;
1793                         #interrupt-cells = <0x2>;
1794                 };
1795
1796                 pcfg_pull_up: pcfg-pull-up {
1797                         bias-pull-up;
1798                 };
1799
1800                 pcfg_pull_down: pcfg-pull-down {
1801                         bias-pull-down;
1802                 };
1803
1804                 pcfg_pull_none: pcfg-pull-none {
1805                         bias-disable;
1806                 };
1807
1808                 pcfg_pull_up_20ma: pcfg-pull-up-20ma {
1809                         bias-pull-up;
1810                         drive-strength = <20>;
1811                 };
1812
1813                 pcfg_pull_none_20ma: pcfg-pull-none-20ma {
1814                         bias-disable;
1815                         drive-strength = <20>;
1816                 };
1817
1818                 pcfg_pull_none_18ma: pcfg-pull-none-18ma {
1819                         bias-disable;
1820                         drive-strength = <18>;
1821                 };
1822
1823                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1824                         bias-disable;
1825                         drive-strength = <12>;
1826                 };
1827
1828                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1829                         bias-pull-up;
1830                         drive-strength = <8>;
1831                 };
1832
1833                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1834                         bias-pull-down;
1835                         drive-strength = <4>;
1836                 };
1837
1838                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1839                         bias-pull-up;
1840                         drive-strength = <2>;
1841                 };
1842
1843                 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
1844                         bias-pull-down;
1845                         drive-strength = <12>;
1846                 };
1847
1848                 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
1849                         bias-disable;
1850                         drive-strength = <13>;
1851                 };
1852
1853                 emmc {
1854                         emmc_pwr: emmc-pwr {
1855                                 rockchip,pins =
1856                                         <0 5 RK_FUNC_1 &pcfg_pull_up>;
1857                         };
1858                 };
1859
1860                 gmac {
1861                         rgmii_pins: rgmii-pins {
1862                                 rockchip,pins =
1863                                         /* mac_txclk */
1864                                         <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
1865                                         /* mac_rxclk */
1866                                         <3 14 RK_FUNC_1 &pcfg_pull_none>,
1867                                         /* mac_mdio */
1868                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
1869                                         /* mac_txen */
1870                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1871                                         /* mac_clk */
1872                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
1873                                         /* mac_rxdv */
1874                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
1875                                         /* mac_mdc */
1876                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
1877                                         /* mac_rxd1 */
1878                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
1879                                         /* mac_rxd0 */
1880                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
1881                                         /* mac_txd1 */
1882                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1883                                         /* mac_txd0 */
1884                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
1885                                         /* mac_rxd3 */
1886                                         <3 3 RK_FUNC_1 &pcfg_pull_none>,
1887                                         /* mac_rxd2 */
1888                                         <3 2 RK_FUNC_1 &pcfg_pull_none>,
1889                                         /* mac_txd3 */
1890                                         <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
1891                                         /* mac_txd2 */
1892                                         <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
1893                         };
1894
1895                         rmii_pins: rmii-pins {
1896                                 rockchip,pins =
1897                                         /* mac_mdio */
1898                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
1899                                         /* mac_txen */
1900                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1901                                         /* mac_clk */
1902                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
1903                                         /* mac_rxer */
1904                                         <3 10 RK_FUNC_1 &pcfg_pull_none>,
1905                                         /* mac_rxdv */
1906                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
1907                                         /* mac_mdc */
1908                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
1909                                         /* mac_rxd1 */
1910                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
1911                                         /* mac_rxd0 */
1912                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
1913                                         /* mac_txd1 */
1914                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1915                                         /* mac_txd0 */
1916                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
1917                         };
1918                 };
1919
1920                 i2c0 {
1921                         i2c0_xfer: i2c0-xfer {
1922                                 rockchip,pins =
1923                                         <1 15 RK_FUNC_2 &pcfg_pull_none>,
1924                                         <1 16 RK_FUNC_2 &pcfg_pull_none>;
1925                         };
1926                 };
1927
1928                 i2c1 {
1929                         i2c1_xfer: i2c1-xfer {
1930                                 rockchip,pins =
1931                                         <4 2 RK_FUNC_1 &pcfg_pull_none>,
1932                                         <4 1 RK_FUNC_1 &pcfg_pull_none>;
1933                         };
1934                 };
1935
1936                 i2c2 {
1937                         i2c2_xfer: i2c2-xfer {
1938                                 rockchip,pins =
1939                                         <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1940                                         <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
1941                         };
1942                 };
1943
1944                 i2c3 {
1945                         i2c3_xfer: i2c3-xfer {
1946                                 rockchip,pins =
1947                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
1948                                         <4 16 RK_FUNC_1 &pcfg_pull_none>;
1949                         };
1950
1951                         i2c3_gpio: i2c3_gpio {
1952                                 rockchip,pins =
1953                                         <4 17 RK_FUNC_GPIO &pcfg_pull_none>,
1954                                         <4 16 RK_FUNC_GPIO &pcfg_pull_none>;
1955                         };
1956
1957                 };
1958
1959                 i2c4 {
1960                         i2c4_xfer: i2c4-xfer {
1961                                 rockchip,pins =
1962                                         <1 12 RK_FUNC_1 &pcfg_pull_none>,
1963                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
1964                         };
1965                 };
1966
1967                 i2c5 {
1968                         i2c5_xfer: i2c5-xfer {
1969                                 rockchip,pins =
1970                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
1971                                         <3 10 RK_FUNC_2 &pcfg_pull_none>;
1972                         };
1973                 };
1974
1975                 i2c6 {
1976                         i2c6_xfer: i2c6-xfer {
1977                                 rockchip,pins =
1978                                         <2 10 RK_FUNC_2 &pcfg_pull_none>,
1979                                         <2 9 RK_FUNC_2 &pcfg_pull_none>;
1980                         };
1981                 };
1982
1983                 i2c7 {
1984                         i2c7_xfer: i2c7-xfer {
1985                                 rockchip,pins =
1986                                         <2 8 RK_FUNC_2 &pcfg_pull_none>,
1987                                         <2 7 RK_FUNC_2 &pcfg_pull_none>;
1988                         };
1989                 };
1990
1991                 i2c8 {
1992                         i2c8_xfer: i2c8-xfer {
1993                                 rockchip,pins =
1994                                         <1 21 RK_FUNC_1 &pcfg_pull_none>,
1995                                         <1 20 RK_FUNC_1 &pcfg_pull_none>;
1996                         };
1997                 };
1998
1999                 i2s0 {
2000                         i2s0_8ch_bus: i2s0-8ch-bus {
2001                                 rockchip,pins =
2002                                         <3 24 RK_FUNC_1 &pcfg_pull_none>,
2003                                         <3 25 RK_FUNC_1 &pcfg_pull_none>,
2004                                         <3 26 RK_FUNC_1 &pcfg_pull_none>,
2005                                         <3 27 RK_FUNC_1 &pcfg_pull_none>,
2006                                         <3 28 RK_FUNC_1 &pcfg_pull_none>,
2007                                         <3 29 RK_FUNC_1 &pcfg_pull_none>,
2008                                         <3 30 RK_FUNC_1 &pcfg_pull_none>,
2009                                         <3 31 RK_FUNC_1 &pcfg_pull_none>,
2010                                         <4 0 RK_FUNC_1 &pcfg_pull_none>;
2011                         };
2012                 };
2013
2014                 i2s1 {
2015                         i2s1_2ch_bus: i2s1-2ch-bus {
2016                                 rockchip,pins =
2017                                         <4 3 RK_FUNC_1 &pcfg_pull_none>,
2018                                         <4 4 RK_FUNC_1 &pcfg_pull_none>,
2019                                         <4 5 RK_FUNC_1 &pcfg_pull_none>,
2020                                         <4 6 RK_FUNC_1 &pcfg_pull_none>,
2021                                         <4 7 RK_FUNC_1 &pcfg_pull_none>;
2022                         };
2023                 };
2024
2025                 sdio0 {
2026                         sdio0_bus1: sdio0-bus1 {
2027                                 rockchip,pins =
2028                                         <2 20 RK_FUNC_1 &pcfg_pull_up>;
2029                         };
2030
2031                         sdio0_bus4: sdio0-bus4 {
2032                                 rockchip,pins =
2033                                         <2 20 RK_FUNC_1 &pcfg_pull_up>,
2034                                         <2 21 RK_FUNC_1 &pcfg_pull_up>,
2035                                         <2 22 RK_FUNC_1 &pcfg_pull_up>,
2036                                         <2 23 RK_FUNC_1 &pcfg_pull_up>;
2037                         };
2038
2039                         sdio0_cmd: sdio0-cmd {
2040                                 rockchip,pins =
2041                                         <2 24 RK_FUNC_1 &pcfg_pull_up>;
2042                         };
2043
2044                         sdio0_clk: sdio0-clk {
2045                                 rockchip,pins =
2046                                         <2 25 RK_FUNC_1 &pcfg_pull_none>;
2047                         };
2048
2049                         sdio0_cd: sdio0-cd {
2050                                 rockchip,pins =
2051                                         <2 26 RK_FUNC_1 &pcfg_pull_up>;
2052                         };
2053
2054                         sdio0_pwr: sdio0-pwr {
2055                                 rockchip,pins =
2056                                         <2 27 RK_FUNC_1 &pcfg_pull_up>;
2057                         };
2058
2059                         sdio0_bkpwr: sdio0-bkpwr {
2060                                 rockchip,pins =
2061                                         <2 28 RK_FUNC_1 &pcfg_pull_up>;
2062                         };
2063
2064                         sdio0_wp: sdio0-wp {
2065                                 rockchip,pins =
2066                                         <0 3 RK_FUNC_1 &pcfg_pull_up>;
2067                         };
2068
2069                         sdio0_int: sdio0-int {
2070                                 rockchip,pins =
2071                                         <0 4 RK_FUNC_1 &pcfg_pull_up>;
2072                         };
2073                 };
2074
2075                 sdmmc {
2076                         sdmmc_bus1: sdmmc-bus1 {
2077                                 rockchip,pins =
2078                                         <4 8 RK_FUNC_1 &pcfg_pull_up>;
2079                         };
2080
2081                         sdmmc_bus4: sdmmc-bus4 {
2082                                 rockchip,pins =
2083                                         <4 8 RK_FUNC_1 &pcfg_pull_up>,
2084                                         <4 9 RK_FUNC_1 &pcfg_pull_up>,
2085                                         <4 10 RK_FUNC_1 &pcfg_pull_up>,
2086                                         <4 11 RK_FUNC_1 &pcfg_pull_up>;
2087                         };
2088
2089                         sdmmc_clk: sdmmc-clk {
2090                                 rockchip,pins =
2091                                         <4 12 RK_FUNC_1 &pcfg_pull_none>;
2092                         };
2093
2094                         sdmmc_cmd: sdmmc-cmd {
2095                                 rockchip,pins =
2096                                         <4 13 RK_FUNC_1 &pcfg_pull_up>;
2097                         };
2098
2099                         sdmmc_cd: sdmcc-cd {
2100                                 rockchip,pins =
2101                                         <0 7 RK_FUNC_1 &pcfg_pull_up>;
2102                         };
2103
2104                         sdmmc_wp: sdmmc-wp {
2105                                 rockchip,pins =
2106                                         <0 8 RK_FUNC_1 &pcfg_pull_up>;
2107                         };
2108                 };
2109
2110                 spdif {
2111                         spdif_bus: spdif-bus {
2112                                 rockchip,pins =
2113                                         <4 21 RK_FUNC_1 &pcfg_pull_none>;
2114                         };
2115
2116                         spdif_bus_1: spdif-bus-1 {
2117                                 rockchip,pins =
2118                                         <3 16 RK_FUNC_3 &pcfg_pull_none>;
2119                         };
2120                 };
2121
2122                 spi0 {
2123                         spi0_clk: spi0-clk {
2124                                 rockchip,pins =
2125                                         <3 6 RK_FUNC_2 &pcfg_pull_up>;
2126                         };
2127                         spi0_cs0: spi0-cs0 {
2128                                 rockchip,pins =
2129                                         <3 7 RK_FUNC_2 &pcfg_pull_up>;
2130                         };
2131                         spi0_cs1: spi0-cs1 {
2132                                 rockchip,pins =
2133                                         <3 8 RK_FUNC_2 &pcfg_pull_up>;
2134                         };
2135                         spi0_tx: spi0-tx {
2136                                 rockchip,pins =
2137                                         <3 5 RK_FUNC_2 &pcfg_pull_up>;
2138                         };
2139                         spi0_rx: spi0-rx {
2140                                 rockchip,pins =
2141                                         <3 4 RK_FUNC_2 &pcfg_pull_up>;
2142                         };
2143                 };
2144
2145                 spi1 {
2146                         spi1_clk: spi1-clk {
2147                                 rockchip,pins =
2148                                         <1 9 RK_FUNC_2 &pcfg_pull_up>;
2149                         };
2150                         spi1_cs0: spi1-cs0 {
2151                                 rockchip,pins =
2152                                         <1 10 RK_FUNC_2 &pcfg_pull_up>;
2153                         };
2154                         spi1_rx: spi1-rx {
2155                                 rockchip,pins =
2156                                         <1 7 RK_FUNC_2 &pcfg_pull_up>;
2157                         };
2158                         spi1_tx: spi1-tx {
2159                                 rockchip,pins =
2160                                         <1 8 RK_FUNC_2 &pcfg_pull_up>;
2161                         };
2162                 };
2163
2164                 spi2 {
2165                         spi2_clk: spi2-clk {
2166                                 rockchip,pins =
2167                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
2168                         };
2169                         spi2_cs0: spi2-cs0 {
2170                                 rockchip,pins =
2171                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
2172                         };
2173                         spi2_rx: spi2-rx {
2174                                 rockchip,pins =
2175                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
2176                         };
2177                         spi2_tx: spi2-tx {
2178                                 rockchip,pins =
2179                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
2180                         };
2181                 };
2182
2183                 spi3 {
2184                         spi3_clk: spi3-clk {
2185                                 rockchip,pins =
2186                                         <1 17 RK_FUNC_1 &pcfg_pull_up>;
2187                         };
2188                         spi3_cs0: spi3-cs0 {
2189                                 rockchip,pins =
2190                                         <1 18 RK_FUNC_1 &pcfg_pull_up>;
2191                         };
2192                         spi3_rx: spi3-rx {
2193                                 rockchip,pins =
2194                                         <1 15 RK_FUNC_1 &pcfg_pull_up>;
2195                         };
2196                         spi3_tx: spi3-tx {
2197                                 rockchip,pins =
2198                                         <1 16 RK_FUNC_1 &pcfg_pull_up>;
2199                         };
2200                 };
2201
2202                 spi4 {
2203                         spi4_clk: spi4-clk {
2204                                 rockchip,pins =
2205                                         <3 2 RK_FUNC_2 &pcfg_pull_up>;
2206                         };
2207                         spi4_cs0: spi4-cs0 {
2208                                 rockchip,pins =
2209                                         <3 3 RK_FUNC_2 &pcfg_pull_up>;
2210                         };
2211                         spi4_rx: spi4-rx {
2212                                 rockchip,pins =
2213                                         <3 0 RK_FUNC_2 &pcfg_pull_up>;
2214                         };
2215                         spi4_tx: spi4-tx {
2216                                 rockchip,pins =
2217                                         <3 1 RK_FUNC_2 &pcfg_pull_up>;
2218                         };
2219                 };
2220
2221                 spi5 {
2222                         spi5_clk: spi5-clk {
2223                                 rockchip,pins =
2224                                         <2 22 RK_FUNC_2 &pcfg_pull_up>;
2225                         };
2226                         spi5_cs0: spi5-cs0 {
2227                                 rockchip,pins =
2228                                         <2 23 RK_FUNC_2 &pcfg_pull_up>;
2229                         };
2230                         spi5_rx: spi5-rx {
2231                                 rockchip,pins =
2232                                         <2 20 RK_FUNC_2 &pcfg_pull_up>;
2233                         };
2234                         spi5_tx: spi5-tx {
2235                                 rockchip,pins =
2236                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
2237                         };
2238                 };
2239
2240                 tsadc {
2241                         otp_gpio: otp-gpio {
2242                                 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
2243                         };
2244
2245                         otp_out: otp-out {
2246                                 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
2247                         };
2248                 };
2249
2250                 uart0 {
2251                         uart0_xfer: uart0-xfer {
2252                                 rockchip,pins =
2253                                         <2 16 RK_FUNC_1 &pcfg_pull_up>,
2254                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
2255                         };
2256
2257                         uart0_cts: uart0-cts {
2258                                 rockchip,pins =
2259                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
2260                         };
2261
2262                         uart0_rts: uart0-rts {
2263                                 rockchip,pins =
2264                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
2265                         };
2266                 };
2267
2268                 uart1 {
2269                         uart1_xfer: uart1-xfer {
2270                                 rockchip,pins =
2271                                         <3 12 RK_FUNC_2 &pcfg_pull_up>,
2272                                         <3 13 RK_FUNC_2 &pcfg_pull_none>;
2273                         };
2274                 };
2275
2276                 uart2a {
2277                         uart2a_xfer: uart2a-xfer {
2278                                 rockchip,pins =
2279                                         <4 8 RK_FUNC_2 &pcfg_pull_up>,
2280                                         <4 9 RK_FUNC_2 &pcfg_pull_none>;
2281                         };
2282                 };
2283
2284                 uart2b {
2285                         uart2b_xfer: uart2b-xfer {
2286                                 rockchip,pins =
2287                                         <4 16 RK_FUNC_2 &pcfg_pull_up>,
2288                                         <4 17 RK_FUNC_2 &pcfg_pull_none>;
2289                         };
2290                 };
2291
2292                 uart2c {
2293                         uart2c_xfer: uart2c-xfer {
2294                                 rockchip,pins =
2295                                         <4 19 RK_FUNC_1 &pcfg_pull_up>,
2296                                         <4 20 RK_FUNC_1 &pcfg_pull_none>;
2297                         };
2298                 };
2299
2300                 uart3 {
2301                         uart3_xfer: uart3-xfer {
2302                                 rockchip,pins =
2303                                         <3 14 RK_FUNC_2 &pcfg_pull_up>,
2304                                         <3 15 RK_FUNC_2 &pcfg_pull_none>;
2305                         };
2306
2307                         uart3_cts: uart3-cts {
2308                                 rockchip,pins =
2309                                         <3 18 RK_FUNC_2 &pcfg_pull_none>;
2310                         };
2311
2312                         uart3_rts: uart3-rts {
2313                                 rockchip,pins =
2314                                         <3 19 RK_FUNC_2 &pcfg_pull_none>;
2315                         };
2316                 };
2317
2318                 uart4 {
2319                         uart4_xfer: uart4-xfer {
2320                                 rockchip,pins =
2321                                         <1 7 RK_FUNC_1 &pcfg_pull_up>,
2322                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
2323                         };
2324                 };
2325
2326                 uarthdcp {
2327                         uarthdcp_xfer: uarthdcp-xfer {
2328                                 rockchip,pins =
2329                                         <4 21 RK_FUNC_2 &pcfg_pull_up>,
2330                                         <4 22 RK_FUNC_2 &pcfg_pull_none>;
2331                         };
2332                 };
2333
2334                 pwm0 {
2335                         pwm0_pin: pwm0-pin {
2336                                 rockchip,pins =
2337                                         <4 18 RK_FUNC_1 &pcfg_pull_none>;
2338                         };
2339
2340                         vop0_pwm_pin: vop0-pwm-pin {
2341                                 rockchip,pins =
2342                                         <4 18 RK_FUNC_2 &pcfg_pull_none>;
2343                         };
2344                 };
2345
2346                 pwm1 {
2347                         pwm1_pin: pwm1-pin {
2348                                 rockchip,pins =
2349                                         <4 22 RK_FUNC_1 &pcfg_pull_none>;
2350                         };
2351
2352                         vop1_pwm_pin: vop1-pwm-pin {
2353                                 rockchip,pins =
2354                                         <4 18 RK_FUNC_3 &pcfg_pull_none>;
2355                         };
2356                 };
2357
2358                 pwm2 {
2359                         pwm2_pin: pwm2-pin {
2360                                 rockchip,pins =
2361                                         <1 19 RK_FUNC_1 &pcfg_pull_none>;
2362                         };
2363                 };
2364
2365                 pwm3a {
2366                         pwm3a_pin: pwm3a-pin {
2367                                 rockchip,pins =
2368                                         <0 6 RK_FUNC_1 &pcfg_pull_none>;
2369                         };
2370                 };
2371
2372                 pwm3b {
2373                         pwm3b_pin: pwm3b-pin {
2374                                 rockchip,pins =
2375                                         <1 14 RK_FUNC_1 &pcfg_pull_none>;
2376                         };
2377                 };
2378
2379                 edp {
2380                         edp_hpd: edp-hpd {
2381                                 rockchip,pins =
2382                                         <4 23 RK_FUNC_2 &pcfg_pull_none>;
2383                         };
2384                 };
2385
2386                 hdmi {
2387                         hdmi_i2c_xfer: hdmi-i2c-xfer {
2388                                 rockchip,pins =
2389                                         <4 17 RK_FUNC_3 &pcfg_pull_none>,
2390                                         <4 16 RK_FUNC_3 &pcfg_pull_none>;
2391                         };
2392
2393                         hdmi_cec: hdmi-cec {
2394                                 rockchip,pins =
2395                                         <4 23 RK_FUNC_1 &pcfg_pull_none>;
2396                         };
2397                 };
2398
2399                 pcie {
2400                         pcie_clkreqn: pci-clkreqn {
2401                                 rockchip,pins =
2402                                         <2 26 RK_FUNC_2 &pcfg_pull_none>;
2403                         };
2404
2405                         pcie_clkreqnb: pci-clkreqnb {
2406                                 rockchip,pins =
2407                                         <4 24 RK_FUNC_1 &pcfg_pull_none>;
2408                         };
2409                 };
2410         };
2411 };