2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/clock/rk3399-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/interrupt-controller/irq.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/power/rk3399-power.h>
49 #include <dt-bindings/soc/rockchip_boot-mode.h>
50 #include <dt-bindings/thermal/thermal.h>
53 compatible = "rockchip,rk3399";
55 interrupt-parent = <&gic>;
77 compatible = "arm,psci-1.0";
113 compatible = "arm,cortex-a53", "arm,armv8";
115 enable-method = "psci";
116 #cooling-cells = <2>; /* min followed by max */
117 dynamic-power-coefficient = <100>;
118 clocks = <&cru ARMCLKL>;
119 cpu-idle-states = <&cpu_sleep>;
120 operating-points-v2 = <&cluster0_opp>;
121 sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
126 compatible = "arm,cortex-a53", "arm,armv8";
128 enable-method = "psci";
129 clocks = <&cru ARMCLKL>;
130 cpu-idle-states = <&cpu_sleep>;
131 operating-points-v2 = <&cluster0_opp>;
132 sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
137 compatible = "arm,cortex-a53", "arm,armv8";
139 enable-method = "psci";
140 clocks = <&cru ARMCLKL>;
141 cpu-idle-states = <&cpu_sleep>;
142 operating-points-v2 = <&cluster0_opp>;
143 sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
148 compatible = "arm,cortex-a53", "arm,armv8";
150 enable-method = "psci";
151 clocks = <&cru ARMCLKL>;
152 cpu-idle-states = <&cpu_sleep>;
153 operating-points-v2 = <&cluster0_opp>;
154 sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
159 compatible = "arm,cortex-a72", "arm,armv8";
161 enable-method = "psci";
162 #cooling-cells = <2>; /* min followed by max */
163 dynamic-power-coefficient = <436>;
164 clocks = <&cru ARMCLKB>;
165 cpu-idle-states = <&cpu_sleep>;
166 operating-points-v2 = <&cluster1_opp>;
167 sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>;
172 compatible = "arm,cortex-a72", "arm,armv8";
174 enable-method = "psci";
175 clocks = <&cru ARMCLKB>;
176 cpu-idle-states = <&cpu_sleep>;
177 operating-points-v2 = <&cluster1_opp>;
178 sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>;
182 entry-method = "psci";
183 cpu_sleep: cpu-sleep-0 {
184 compatible = "arm,idle-state";
186 arm,psci-suspend-param = <0x0010000>;
187 entry-latency-us = <350>;
188 exit-latency-us = <600>;
189 min-residency-us = <1150>;
193 /include/ "rk3399-sched-energy.dtsi"
197 cluster0_opp: opp_table0 {
198 compatible = "operating-points-v2";
202 opp-hz = /bits/ 64 <408000000>;
203 opp-microvolt = <800000>;
204 clock-latency-ns = <40000>;
207 opp-hz = /bits/ 64 <600000000>;
208 opp-microvolt = <800000>;
211 opp-hz = /bits/ 64 <816000000>;
212 opp-microvolt = <800000>;
215 opp-hz = /bits/ 64 <1008000000>;
216 opp-microvolt = <875000>;
219 opp-hz = /bits/ 64 <1200000000>;
220 opp-microvolt = <925000>;
223 opp-hz = /bits/ 64 <1416000000>;
224 opp-microvolt = <1025000>;
228 cluster1_opp: opp_table1 {
229 compatible = "operating-points-v2";
233 opp-hz = /bits/ 64 <408000000>;
234 opp-microvolt = <800000>;
235 clock-latency-ns = <40000>;
238 opp-hz = /bits/ 64 <600000000>;
239 opp-microvolt = <800000>;
242 opp-hz = /bits/ 64 <816000000>;
243 opp-microvolt = <800000>;
246 opp-hz = /bits/ 64 <1008000000>;
247 opp-microvolt = <850000>;
250 opp-hz = /bits/ 64 <1200000000>;
251 opp-microvolt = <925000>;
256 compatible = "arm,armv8-timer";
257 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
258 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
259 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
260 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
264 compatible = "arm,cortex-a53-pmu";
265 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &part0>;
269 compatible = "arm,cortex-a72-pmu";
270 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &part1>;
274 compatible = "fixed-clock";
276 clock-frequency = <24000000>;
277 clock-output-names = "xin24m";
281 compatible = "arm,amba-bus";
282 #address-cells = <2>;
286 dmac_bus: dma-controller@ff6d0000 {
287 compatible = "arm,pl330", "arm,primecell";
288 reg = <0x0 0xff6d0000 0x0 0x4000>;
289 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
290 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
292 clocks = <&cru ACLK_DMAC0_PERILP>;
293 clock-names = "apb_pclk";
294 peripherals-req-type-burst;
297 dmac_peri: dma-controller@ff6e0000 {
298 compatible = "arm,pl330", "arm,primecell";
299 reg = <0x0 0xff6e0000 0x0 0x4000>;
300 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
301 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>;
303 clocks = <&cru ACLK_DMAC1_PERILP>;
304 clock-names = "apb_pclk";
305 peripherals-req-type-burst;
310 compatible = "rockchip,rk3399-gmac";
311 reg = <0x0 0xfe300000 0x0 0x10000>;
312 rockchip,grf = <&grf>;
313 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
314 interrupt-names = "macirq";
315 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
316 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
317 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
319 clock-names = "stmmaceth", "mac_clk_rx",
320 "mac_clk_tx", "clk_mac_ref",
321 "clk_mac_refout", "aclk_mac",
323 resets = <&cru SRST_A_GMAC>;
324 reset-names = "stmmaceth";
325 power-domains = <&power RK3399_PD_GMAC>;
330 compatible = "rockchip,rk3399-emmc-phy";
331 reg-offset = <0xf780>;
333 rockchip,grf = <&grf>;
334 ctrl-base = <0xfe330000>;
338 sdio0: dwmmc@fe310000 {
339 compatible = "rockchip,rk3399-dw-mshc",
340 "rockchip,rk3288-dw-mshc";
341 reg = <0x0 0xfe310000 0x0 0x4000>;
342 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>;
343 clock-freq-min-max = <400000 150000000>;
344 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
345 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
346 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
347 fifo-depth = <0x100>;
348 power-domains = <&power RK3399_PD_SDIOAUDIO>;
352 sdmmc: dwmmc@fe320000 {
353 compatible = "rockchip,rk3399-dw-mshc",
354 "rockchip,rk3288-dw-mshc";
355 reg = <0x0 0xfe320000 0x0 0x4000>;
356 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
357 clock-freq-min-max = <400000 150000000>;
358 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
359 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
360 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
361 fifo-depth = <0x100>;
362 power-domains = <&power RK3399_PD_SD>;
366 sdhci: sdhci@fe330000 {
367 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
368 reg = <0x0 0xfe330000 0x0 0x10000>;
369 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
370 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
371 clock-names = "clk_xin", "clk_ahb";
372 assigned-clocks = <&cru SCLK_EMMC>;
373 assigned-clock-parents = <&cru PLL_CPLL>;
374 assigned-clock-rates = <200000000>;
376 phy-names = "phy_arasan";
377 power-domains = <&power RK3399_PD_EMMC>;
381 usb_host0_ehci: usb@fe380000 {
382 compatible = "generic-ehci";
383 reg = <0x0 0xfe380000 0x0 0x20000>;
384 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
385 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
386 <&cru SCLK_USBPHY0_480M_SRC>;
387 clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m";
388 phys = <&u2phy0_host>;
390 power-domains = <&power RK3399_PD_PERIHP>;
394 usb_host0_ohci: usb@fe3a0000 {
395 compatible = "generic-ohci";
396 reg = <0x0 0xfe3a0000 0x0 0x20000>;
397 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
398 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
399 <&cru SCLK_USBPHY0_480M_SRC>;
400 clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m";
401 phys = <&u2phy0_host>;
403 power-domains = <&power RK3399_PD_PERIHP>;
407 usb_host1_ehci: usb@fe3c0000 {
408 compatible = "generic-ehci";
409 reg = <0x0 0xfe3c0000 0x0 0x20000>;
410 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
411 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
412 <&cru SCLK_USBPHY1_480M_SRC>;
413 clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m";
414 phys = <&u2phy1_host>;
416 power-domains = <&power RK3399_PD_PERIHP>;
420 usb_host1_ohci: usb@fe3e0000 {
421 compatible = "generic-ohci";
422 reg = <0x0 0xfe3e0000 0x0 0x20000>;
423 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
424 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
425 <&cru SCLK_USBPHY1_480M_SRC>;
426 clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m";
427 phys = <&u2phy1_host>;
429 power-domains = <&power RK3399_PD_PERIHP>;
433 usbdrd3_0: usb@fe800000 {
434 compatible = "rockchip,rk3399-dwc3";
435 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
436 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
437 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
438 clock-names = "clk_usb3otg0_ref", "clk_usb3otg0_suspend",
439 "aclk_usb3otg0", "aclk_usb3_rksoc_axi_perf",
440 "aclk_usb3", "aclk_usb3_grf";
441 power-domains = <&power RK3399_PD_USB3>;
442 resets = <&cru SRST_A_USB3_OTG0>;
443 reset-names = "usb3-otg";
444 #address-cells = <2>;
448 usbdrd_dwc3_0: dwc3@fe800000 {
449 compatible = "snps,dwc3";
450 reg = <0x0 0xfe800000 0x0 0x100000>;
451 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
453 phys = <&u2phy0_otg>;
454 phy-names = "usb2-phy";
455 phy_type = "utmi_wide";
456 snps,dis_enblslpm_quirk;
457 snps,dis-u2-freeclk-exists-quirk;
458 snps,dis-del-phy-power-chg-quirk;
459 snps,xhci-slow-suspend-quirk;
464 usbdrd3_1: usb@fe900000 {
465 compatible = "rockchip,rk3399-dwc3";
466 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
467 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
468 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
469 clock-names = "clk_usb3otg1_ref", "clk_usb3otg1_suspend",
470 "aclk_usb3otg1", "aclk_usb3_rksoc_axi_perf",
471 "aclk_usb3", "aclk_usb3_grf";
472 power-domains = <&power RK3399_PD_USB3>;
473 resets = <&cru SRST_A_USB3_OTG1>;
474 reset-names = "usb3-otg";
475 #address-cells = <2>;
479 usbdrd_dwc3_1: dwc3@fe900000 {
480 compatible = "snps,dwc3";
481 reg = <0x0 0xfe900000 0x0 0x100000>;
482 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
484 phys = <&u2phy1_otg>;
485 phy-names = "usb2-phy";
486 phy_type = "utmi_wide";
487 snps,dis_enblslpm_quirk;
488 snps,dis-u2-freeclk-exists-quirk;
489 snps,dis-del-phy-power-chg-quirk;
490 snps,xhci-slow-suspend-quirk;
495 gic: interrupt-controller@fee00000 {
496 compatible = "arm,gic-v3";
497 #interrupt-cells = <4>;
498 #address-cells = <2>;
501 interrupt-controller;
503 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
504 <0x0 0xfef00000 0 0xc0000>, /* GICR */
505 <0x0 0xfff00000 0 0x10000>, /* GICC */
506 <0x0 0xfff10000 0 0x10000>, /* GICH */
507 <0x0 0xfff20000 0 0x10000>; /* GICV */
508 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
509 its: interrupt-controller@fee20000 {
510 compatible = "arm,gic-v3-its";
512 reg = <0x0 0xfee20000 0x0 0x20000>;
516 part0: interrupt-partition-0 {
517 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
520 part1: interrupt-partition-1 {
521 affinity = <&cpu_b0 &cpu_b1>;
526 saradc: saradc@ff100000 {
527 compatible = "rockchip,rk3399-saradc";
528 reg = <0x0 0xff100000 0x0 0x100>;
529 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>;
530 #io-channel-cells = <1>;
531 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
532 clock-names = "saradc", "apb_pclk";
537 compatible = "rockchip,rk3399-i2c";
538 reg = <0x0 0xff3c0000 0x0 0x1000>;
539 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
540 clock-names = "i2c", "pclk";
541 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
542 pinctrl-names = "default";
543 pinctrl-0 = <&i2c0_xfer>;
544 #address-cells = <1>;
550 compatible = "rockchip,rk3399-i2c";
551 reg = <0x0 0xff110000 0x0 0x1000>;
552 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
553 clock-names = "i2c", "pclk";
554 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>;
555 pinctrl-names = "default";
556 pinctrl-0 = <&i2c1_xfer>;
557 #address-cells = <1>;
563 compatible = "rockchip,rk3399-i2c";
564 reg = <0x0 0xff120000 0x0 0x1000>;
565 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
566 clock-names = "i2c", "pclk";
567 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>;
568 pinctrl-names = "default";
569 pinctrl-0 = <&i2c2_xfer>;
570 #address-cells = <1>;
576 compatible = "rockchip,rk3399-i2c";
577 reg = <0x0 0xff130000 0x0 0x1000>;
578 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
579 clock-names = "i2c", "pclk";
580 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>;
581 pinctrl-names = "default";
582 pinctrl-0 = <&i2c3_xfer>;
583 #address-cells = <1>;
589 compatible = "rockchip,rk3399-i2c";
590 reg = <0x0 0xff140000 0x0 0x1000>;
591 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
592 clock-names = "i2c", "pclk";
593 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>;
594 pinctrl-names = "default";
595 pinctrl-0 = <&i2c5_xfer>;
596 #address-cells = <1>;
602 compatible = "rockchip,rk3399-i2c";
603 reg = <0x0 0xff150000 0x0 0x1000>;
604 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
605 clock-names = "i2c", "pclk";
606 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>;
607 pinctrl-names = "default";
608 pinctrl-0 = <&i2c6_xfer>;
609 #address-cells = <1>;
615 compatible = "rockchip,rk3399-i2c";
616 reg = <0x0 0xff160000 0x0 0x1000>;
617 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
618 clock-names = "i2c", "pclk";
619 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>;
620 pinctrl-names = "default";
621 pinctrl-0 = <&i2c7_xfer>;
622 #address-cells = <1>;
627 uart0: serial@ff180000 {
628 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
629 reg = <0x0 0xff180000 0x0 0x100>;
630 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
631 clock-names = "baudclk", "apb_pclk";
632 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
635 pinctrl-names = "default";
636 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
640 uart1: serial@ff190000 {
641 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
642 reg = <0x0 0xff190000 0x0 0x100>;
643 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
644 clock-names = "baudclk", "apb_pclk";
645 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>;
648 pinctrl-names = "default";
649 pinctrl-0 = <&uart1_xfer>;
653 uart2: serial@ff1a0000 {
654 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
655 reg = <0x0 0xff1a0000 0x0 0x100>;
656 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
657 clock-names = "baudclk", "apb_pclk";
658 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
661 pinctrl-names = "default";
662 pinctrl-0 = <&uart2c_xfer>;
666 uart3: serial@ff1b0000 {
667 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
668 reg = <0x0 0xff1b0000 0x0 0x100>;
669 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
670 clock-names = "baudclk", "apb_pclk";
671 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
674 pinctrl-names = "default";
675 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
680 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
681 reg = <0x0 0xff1c0000 0x0 0x1000>;
682 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
683 clock-names = "spiclk", "apb_pclk";
684 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>;
685 pinctrl-names = "default";
686 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
687 #address-cells = <1>;
693 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
694 reg = <0x0 0xff1d0000 0x0 0x1000>;
695 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
696 clock-names = "spiclk", "apb_pclk";
697 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>;
698 pinctrl-names = "default";
699 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
700 #address-cells = <1>;
706 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
707 reg = <0x0 0xff1e0000 0x0 0x1000>;
708 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
709 clock-names = "spiclk", "apb_pclk";
710 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>;
711 pinctrl-names = "default";
712 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
713 #address-cells = <1>;
719 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
720 reg = <0x0 0xff1f0000 0x0 0x1000>;
721 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
722 clock-names = "spiclk", "apb_pclk";
723 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>;
724 pinctrl-names = "default";
725 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
726 #address-cells = <1>;
732 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
733 reg = <0x0 0xff200000 0x0 0x1000>;
734 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
735 clock-names = "spiclk", "apb_pclk";
736 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
737 pinctrl-names = "default";
738 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
739 #address-cells = <1>;
745 soc_thermal: soc-thermal {
746 polling-delay-passive = <20>; /* milliseconds */
747 polling-delay = <1000>; /* milliseconds */
748 sustainable-power = <1000>; /* milliwatts */
750 thermal-sensors = <&tsadc 0>;
753 threshold: trip-point@0 {
754 temperature = <70000>; /* millicelsius */
755 hysteresis = <2000>; /* millicelsius */
758 target: trip-point@1 {
759 temperature = <85000>; /* millicelsius */
760 hysteresis = <2000>; /* millicelsius */
764 temperature = <95000>; /* millicelsius */
765 hysteresis = <2000>; /* millicelsius */
774 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
775 contribution = <4096>;
780 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
781 contribution = <1024>;
786 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
787 contribution = <4096>;
792 gpu_thermal: gpu-thermal {
793 polling-delay-passive = <100>; /* milliseconds */
794 polling-delay = <1000>; /* milliseconds */
796 thermal-sensors = <&tsadc 1>;
800 tsadc: tsadc@ff260000 {
801 compatible = "rockchip,rk3399-tsadc";
802 reg = <0x0 0xff260000 0x0 0x100>;
803 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
804 rockchip,grf = <&grf>;
805 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
806 clock-names = "tsadc", "apb_pclk";
807 assigned-clocks = <&cru SCLK_TSADC>;
808 assigned-clock-rates = <750000>;
809 resets = <&cru SRST_TSADC>;
810 reset-names = "tsadc-apb";
811 pinctrl-names = "init", "default", "sleep";
812 pinctrl-0 = <&otp_gpio>;
813 pinctrl-1 = <&otp_out>;
814 pinctrl-2 = <&otp_gpio>;
815 #thermal-sensor-cells = <1>;
816 rockchip,hw-tshut-temp = <95000>;
820 qos_emmc: qos@ffa58000 {
821 compatible = "syscon";
822 reg = <0x0 0xffa58000 0x0 0x20>;
825 qos_gmac: qos@ffa5c000 {
826 compatible = "syscon";
827 reg = <0x0 0xffa5c000 0x0 0x20>;
830 qos_pcie: qos@ffa60080 {
831 compatible = "syscon";
832 reg = <0x0 0xffa60080 0x0 0x20>;
835 qos_usb_host0: qos@ffa60100 {
836 compatible = "syscon";
837 reg = <0x0 0xffa60100 0x0 0x20>;
840 qos_usb_host1: qos@ffa60180 {
841 compatible = "syscon";
842 reg = <0x0 0xffa60180 0x0 0x20>;
845 qos_usb_otg0: qos@ffa70000 {
846 compatible = "syscon";
847 reg = <0x0 0xffa70000 0x0 0x20>;
850 qos_usb_otg1: qos@ffa70080 {
851 compatible = "syscon";
852 reg = <0x0 0xffa70080 0x0 0x20>;
855 qos_sd: qos@ffa74000 {
856 compatible = "syscon";
857 reg = <0x0 0xffa74000 0x0 0x20>;
860 qos_sdioaudio: qos@ffa76000 {
861 compatible = "syscon";
862 reg = <0x0 0xffa76000 0x0 0x20>;
865 qos_hdcp: qos@ffa90000 {
866 compatible = "syscon";
867 reg = <0x0 0xffa90000 0x0 0x20>;
870 qos_iep: qos@ffa98000 {
871 compatible = "syscon";
872 reg = <0x0 0xffa98000 0x0 0x20>;
875 qos_isp0_m0: qos@ffaa0000 {
876 compatible = "syscon";
877 reg = <0x0 0xffaa0000 0x0 0x20>;
880 qos_isp0_m1: qos@ffaa0080 {
881 compatible = "syscon";
882 reg = <0x0 0xffaa0080 0x0 0x20>;
885 qos_isp1_m0: qos@ffaa8000 {
886 compatible = "syscon";
887 reg = <0x0 0xffaa8000 0x0 0x20>;
890 qos_isp1_m1: qos@ffaa8080 {
891 compatible = "syscon";
892 reg = <0x0 0xffaa8080 0x0 0x20>;
895 qos_rga_r: qos@ffab0000 {
896 compatible = "syscon";
897 reg = <0x0 0xffab0000 0x0 0x20>;
900 qos_rga_w: qos@ffab0080 {
901 compatible = "syscon";
902 reg = <0x0 0xffab0080 0x0 0x20>;
905 qos_video_m0: qos@ffab8000 {
906 compatible = "syscon";
907 reg = <0x0 0xffab8000 0x0 0x20>;
910 qos_video_m1_r: qos@ffac0000 {
911 compatible = "syscon";
912 reg = <0x0 0xffac0000 0x0 0x20>;
915 qos_video_m1_w: qos@ffac0080 {
916 compatible = "syscon";
917 reg = <0x0 0xffac0080 0x0 0x20>;
920 qos_vop_big_r: qos@ffac8000 {
921 compatible = "syscon";
922 reg = <0x0 0xffac8000 0x0 0x20>;
925 qos_vop_big_w: qos@ffac8080 {
926 compatible = "syscon";
927 reg = <0x0 0xffac8080 0x0 0x20>;
930 qos_vop_little: qos@ffad0000 {
931 compatible = "syscon";
932 reg = <0x0 0xffad0000 0x0 0x20>;
935 qos_perihp: qos@ffad8080 {
936 compatible = "syscon";
937 reg = <0x0 0xffad8080 0x0 0x20>;
940 qos_gpu: qos@ffae0000 {
941 compatible = "syscon";
942 reg = <0x0 0xffae0000 0x0 0x20>;
945 pmu: power-management@ff310000 {
946 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
947 reg = <0x0 0xff310000 0x0 0x1000>;
950 * Note: RK3399 supports 6 voltage domains including VD_CORE_L,
951 * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
952 * Some of the power domains are grouped together for every
954 * The detail contents as below.
956 power: power-controller {
957 compatible = "rockchip,rk3399-power-controller";
958 #power-domain-cells = <1>;
959 #address-cells = <1>;
962 /* These power domains are grouped by VD_CENTER */
963 pd_iep@RK3399_PD_IEP {
964 reg = <RK3399_PD_IEP>;
965 clocks = <&cru ACLK_IEP>,
969 pd_rga@RK3399_PD_RGA {
970 reg = <RK3399_PD_RGA>;
971 clocks = <&cru ACLK_RGA>,
973 pm_qos = <&qos_rga_r>,
976 pd_vcodec@RK3399_PD_VCODEC {
977 reg = <RK3399_PD_VCODEC>;
978 clocks = <&cru ACLK_VCODEC>,
980 pm_qos = <&qos_video_m0>;
982 pd_vdu@RK3399_PD_VDU {
983 reg = <RK3399_PD_VDU>;
984 clocks = <&cru ACLK_VDU>,
986 pm_qos = <&qos_video_m1_r>,
990 /* These power domains are grouped by VD_GPU */
991 pd_gpu@RK3399_PD_GPU {
992 reg = <RK3399_PD_GPU>;
993 clocks = <&cru ACLK_GPU>;
997 /* These power domains are grouped by VD_LOGIC */
998 pd_emmc@RK3399_PD_EMMC {
999 reg = <RK3399_PD_EMMC>;
1000 clocks = <&cru ACLK_EMMC>;
1001 pm_qos = <&qos_emmc>;
1003 pd_gmac@RK3399_PD_GMAC {
1004 reg = <RK3399_PD_GMAC>;
1005 clocks = <&cru ACLK_GMAC>;
1006 pm_qos = <&qos_gmac>;
1008 pd_perihp@RK3399_PD_PERIHP {
1009 reg = <RK3399_PD_PERIHP>;
1010 #address-cells = <1>;
1012 clocks = <&cru ACLK_PERIHP>;
1013 pm_qos = <&qos_perihp>,
1018 pd_sd@RK3399_PD_SD {
1019 reg = <RK3399_PD_SD>;
1020 clocks = <&cru HCLK_SDMMC>,
1025 pd_sdioaudio@RK3399_PD_SDIOAUDIO {
1026 reg = <RK3399_PD_SDIOAUDIO>;
1027 clocks = <&cru HCLK_SDIO>;
1028 pm_qos = <&qos_sdioaudio>;
1030 pd_usb3@RK3399_PD_USB3 {
1031 reg = <RK3399_PD_USB3>;
1032 clocks = <&cru ACLK_USB3>;
1033 pm_qos = <&qos_usb_otg0>,
1036 pd_vio@RK3399_PD_VIO {
1037 reg = <RK3399_PD_VIO>;
1038 #address-cells = <1>;
1041 pd_hdcp@RK3399_PD_HDCP {
1042 reg = <RK3399_PD_HDCP>;
1043 clocks = <&cru ACLK_HDCP>,
1046 pm_qos = <&qos_hdcp>;
1048 pd_isp0@RK3399_PD_ISP0 {
1049 reg = <RK3399_PD_ISP0>;
1050 clocks = <&cru ACLK_ISP0>,
1052 pm_qos = <&qos_isp0_m0>,
1055 pd_isp1@RK3399_PD_ISP1 {
1056 reg = <RK3399_PD_ISP1>;
1057 clocks = <&cru ACLK_ISP1>,
1059 pm_qos = <&qos_isp1_m0>,
1062 pd_vo@RK3399_PD_VO {
1063 reg = <RK3399_PD_VO>;
1064 #address-cells = <1>;
1067 pd_vopb@RK3399_PD_VOPB {
1068 reg = <RK3399_PD_VOPB>;
1069 clocks = <&cru ACLK_VOP0>,
1071 pm_qos = <&qos_vop_big_r>,
1074 pd_vopl@RK3399_PD_VOPL {
1075 reg = <RK3399_PD_VOPL>;
1076 clocks = <&cru ACLK_VOP1>,
1078 pm_qos = <&qos_vop_little>;
1085 pmugrf: syscon@ff320000 {
1086 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
1087 reg = <0x0 0xff320000 0x0 0x1000>;
1090 compatible = "syscon-reboot-mode";
1092 mode-bootloader = <BOOT_LOADER>;
1093 mode-charge = <BOOT_CHARGING>;
1094 mode-fastboot = <BOOT_FASTBOOT>;
1095 mode-loader = <BOOT_LOADER>;
1096 mode-normal = <BOOT_NORMAL>;
1097 mode-recovery = <BOOT_RECOVERY>;
1101 spi3: spi@ff350000 {
1102 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
1103 reg = <0x0 0xff350000 0x0 0x1000>;
1104 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
1105 clock-names = "spiclk", "apb_pclk";
1106 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>;
1107 pinctrl-names = "default";
1108 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
1109 #address-cells = <1>;
1111 status = "disabled";
1114 uart4: serial@ff370000 {
1115 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
1116 reg = <0x0 0xff370000 0x0 0x100>;
1117 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
1118 clock-names = "baudclk", "apb_pclk";
1119 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>;
1122 pinctrl-names = "default";
1123 pinctrl-0 = <&uart4_xfer>;
1124 status = "disabled";
1127 i2c4: i2c@ff3d0000 {
1128 compatible = "rockchip,rk3399-i2c";
1129 reg = <0x0 0xff3d0000 0x0 0x1000>;
1130 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
1131 clock-names = "i2c", "pclk";
1132 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>;
1133 pinctrl-names = "default";
1134 pinctrl-0 = <&i2c4_xfer>;
1135 #address-cells = <1>;
1137 status = "disabled";
1140 i2c8: i2c@ff3e0000 {
1141 compatible = "rockchip,rk3399-i2c";
1142 reg = <0x0 0xff3e0000 0x0 0x1000>;
1143 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
1144 clock-names = "i2c", "pclk";
1145 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
1146 pinctrl-names = "default";
1147 pinctrl-0 = <&i2c8_xfer>;
1148 #address-cells = <1>;
1150 status = "disabled";
1153 pcie0: pcie@f8000000 {
1154 compatible = "rockchip,rk3399-pcie";
1155 #address-cells = <3>;
1157 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
1158 <&cru PCLK_PCIE>, <&cru SCLK_PCIEPHY_REF>;
1159 clock-names = "aclk_pcie", "aclk_perf_pcie",
1160 "hclk_pcie", "clk_pciephy_ref";
1161 bus-range = <0x0 0x1>;
1162 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
1163 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
1164 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
1165 interrupt-names = "pcie-sys", "pcie-legacy", "pcie-client";
1166 ranges = < 0x82000000 0 0xfa000000 0x0 0xfa000000 0 0x600000
1167 0x81000000 0 0xfa600000 0x0 0xfa600000 0 0x100000 >;
1168 reg = < 0x0 0xf8000000 0x0 0x2000000 >,
1169 < 0x0 0xfd000000 0x0 0x1000000 >;
1170 reg-name = "axi-base", "apb-base";
1171 resets = <&cru SRST_PCIEPHY>, <&cru SRST_PCIE_CORE>,
1172 <&cru SRST_PCIE_MGMT>, <&cru SRST_PCIE_MGMT_STICKY>,
1173 <&cru SRST_PCIE_PIPE>;
1174 reset-names = "phy-rst", "core-rst", "mgmt-rst",
1175 "mgmt-sticky-rst", "pipe-rst";
1176 rockchip,grf = <&grf>;
1177 pcie-conf = <0xe220>;
1178 pcie-status = <0xe2a4>;
1179 pcie-laneoff = <0xe214>;
1180 power-domains = <&power RK3399_PD_PERIHP>;
1181 msi-parent = <&its>;
1182 #interrupt-cells = <1>;
1183 interrupt-map-mask = <0 0 0 7>;
1184 interrupt-map = <0 0 0 1 &pcie0 1>,
1188 status = "disabled";
1189 pcie_intc: interrupt-controller {
1190 interrupt-controller;
1191 #address-cells = <0>;
1192 #interrupt-cells = <1>;
1196 pwm0: pwm@ff420000 {
1197 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1198 reg = <0x0 0xff420000 0x0 0x10>;
1200 pinctrl-names = "default";
1201 pinctrl-0 = <&pwm0_pin>;
1202 clocks = <&pmucru PCLK_RKPWM_PMU>;
1203 clock-names = "pwm";
1204 status = "disabled";
1207 pwm1: pwm@ff420010 {
1208 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1209 reg = <0x0 0xff420010 0x0 0x10>;
1211 pinctrl-names = "default";
1212 pinctrl-0 = <&pwm1_pin>;
1213 clocks = <&pmucru PCLK_RKPWM_PMU>;
1214 clock-names = "pwm";
1215 status = "disabled";
1218 pwm2: pwm@ff420020 {
1219 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1220 reg = <0x0 0xff420020 0x0 0x10>;
1222 pinctrl-names = "default";
1223 pinctrl-0 = <&pwm2_pin>;
1224 clocks = <&pmucru PCLK_RKPWM_PMU>;
1225 clock-names = "pwm";
1226 status = "disabled";
1229 pwm3: pwm@ff420030 {
1230 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1231 reg = <0x0 0xff420030 0x0 0x10>;
1233 pinctrl-names = "default";
1234 pinctrl-0 = <&pwm3a_pin>;
1235 clocks = <&pmucru PCLK_RKPWM_PMU>;
1236 clock-names = "pwm";
1237 status = "disabled";
1241 compatible = "rockchip,rk3399-rga";
1242 reg = <0x0 0xff680000 0x0 0x10000>;
1243 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
1244 interrupt-names = "rga";
1245 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
1246 clock-names = "aclk", "hclk", "sclk";
1247 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
1248 reset-names = "core", "axi", "ahb";
1249 power-domains = <&power RK3399_PD_RGA>;
1250 status = "disabled";
1253 pmucru: pmu-clock-controller@ff750000 {
1254 compatible = "rockchip,rk3399-pmucru";
1255 reg = <0x0 0xff750000 0x0 0x1000>;
1258 assigned-clocks = <&pmucru PLL_PPLL>;
1259 assigned-clock-rates = <676000000>;
1262 cru: clock-controller@ff760000 {
1263 compatible = "rockchip,rk3399-cru";
1264 reg = <0x0 0xff760000 0x0 0x1000>;
1268 <&cru ACLK_VOP0>, <&cru HCLK_VOP0>,
1269 <&cru ACLK_VOP1>, <&cru HCLK_VOP1>,
1270 <&cru ARMCLKL>, <&cru ARMCLKB>,
1271 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1273 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1275 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1276 <&cru PCLK_PERILP0>,
1277 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
1278 assigned-clock-rates =
1279 <400000000>, <200000000>,
1280 <400000000>, <200000000>,
1281 <816000000>, <816000000>,
1282 <594000000>, <800000000>,
1284 <150000000>, <75000000>,
1286 <100000000>, <100000000>,
1288 <100000000>, <50000000>;
1291 grf: syscon@ff770000 {
1292 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
1293 reg = <0x0 0xff770000 0x0 0x10000>;
1294 #address-cells = <1>;
1297 u2phy0: usb2-phy@e450 {
1298 compatible = "rockchip,rk3399-usb2phy";
1299 reg = <0xe450 0x10>;
1300 clocks = <&cru SCLK_USB2PHY0_REF>;
1301 clock-names = "phyclk";
1303 clock-output-names = "clk_usbphy0_480m";
1304 status = "disabled";
1306 u2phy0_otg: otg-port {
1308 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
1309 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
1310 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
1311 interrupt-names = "otg-bvalid", "otg-id",
1313 status = "disabled";
1316 u2phy0_host: host-port {
1318 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
1319 interrupt-names = "linestate";
1320 status = "disabled";
1324 u2phy1: usb2-phy@e460 {
1325 compatible = "rockchip,rk3399-usb2phy";
1326 reg = <0xe460 0x10>;
1327 clocks = <&cru SCLK_USB2PHY1_REF>;
1328 clock-names = "phyclk";
1330 clock-output-names = "clk_usbphy1_480m";
1331 status = "disabled";
1333 u2phy1_otg: otg-port {
1335 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
1336 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
1337 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1338 interrupt-names = "otg-bvalid", "otg-id",
1340 status = "disabled";
1343 u2phy1_host: host-port {
1345 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
1346 interrupt-names = "linestate";
1347 status = "disabled";
1352 tcphy0: phy@ff7c0000 {
1353 compatible = "rockchip,rk3399-typec-phy";
1354 reg = <0x0 0xff7c0000 0x0 0x40000>;
1355 rockchip,grf = <&grf>;
1357 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1358 <&cru SCLK_UPHY0_TCPDPHY_REF>;
1359 clock-names = "tcpdcore", "tcpdphy-ref";
1360 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
1361 assigned-clock-rates = <50000000>;
1362 resets = <&cru SRST_UPHY0>,
1363 <&cru SRST_UPHY0_PIPE_L00>,
1364 <&cru SRST_P_UPHY0_TCPHY>;
1365 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1366 rockchip,typec-conn-dir = <0xe580 0 16>;
1367 rockchip,usb3tousb2-en = <0xe580 3 19>;
1368 rockchip,external-psm = <0xe588 14 30>;
1369 rockchip,pipe-status = <0xe5c0 0 0>;
1370 rockchip,uphy-dp-sel = <0x6268 19 19>;
1371 status = "disabled";
1374 tcphy1: phy@ff800000 {
1375 compatible = "rockchip,rk3399-typec-phy";
1376 reg = <0x0 0xff800000 0x0 0x40000>;
1377 rockchip,grf = <&grf>;
1379 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1380 <&cru SCLK_UPHY1_TCPDPHY_REF>;
1381 clock-names = "tcpdcore", "tcpdphy-ref";
1382 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
1383 assigned-clock-rates = <50000000>;
1384 resets = <&cru SRST_UPHY1>,
1385 <&cru SRST_UPHY1_PIPE_L00>,
1386 <&cru SRST_P_UPHY1_TCPHY>;
1387 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1388 rockchip,typec-conn-dir = <0xe58c 0 16>;
1389 rockchip,usb3tousb2-en = <0xe58c 3 19>;
1390 rockchip,external-psm = <0xe594 14 30>;
1391 rockchip,pipe-status = <0xe5c0 16 16>;
1392 rockchip,uphy-dp-sel = <0x6268 3 19>;
1393 status = "disabled";
1397 compatible = "snps,dw-wdt";
1398 reg = <0x0 0xff840000 0x0 0x100>;
1399 clocks = <&cru PCLK_WDT>;
1400 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
1403 rktimer: rktimer@ff850000 {
1404 compatible = "rockchip,rk3399-timer";
1405 reg = <0x0 0xff850000 0x0 0x1000>;
1406 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
1407 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1408 clock-names = "pclk", "timer";
1411 spdif: spdif@ff870000 {
1412 compatible = "rockchip,rk3399-spdif";
1413 reg = <0x0 0xff870000 0x0 0x1000>;
1414 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
1415 dmas = <&dmac_bus 7>;
1417 clock-names = "mclk", "hclk";
1418 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1419 pinctrl-names = "default";
1420 pinctrl-0 = <&spdif_bus>;
1421 status = "disabled";
1424 i2s0: i2s@ff880000 {
1425 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1426 reg = <0x0 0xff880000 0x0 0x1000>;
1427 rockchip,grf = <&grf>;
1428 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>;
1429 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1430 dma-names = "tx", "rx";
1431 clock-names = "i2s_clk", "i2s_hclk";
1432 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1433 pinctrl-names = "default";
1434 pinctrl-0 = <&i2s0_8ch_bus>;
1435 status = "disabled";
1438 i2s1: i2s@ff890000 {
1439 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1440 reg = <0x0 0xff890000 0x0 0x1000>;
1441 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>;
1442 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1443 dma-names = "tx", "rx";
1444 clock-names = "i2s_clk", "i2s_hclk";
1445 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1446 pinctrl-names = "default";
1447 pinctrl-0 = <&i2s1_2ch_bus>;
1448 status = "disabled";
1451 i2s2: i2s@ff8a0000 {
1452 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1453 reg = <0x0 0xff8a0000 0x0 0x1000>;
1454 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>;
1455 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1456 dma-names = "tx", "rx";
1457 clock-names = "i2s_clk", "i2s_hclk";
1458 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1459 status = "disabled";
1463 compatible = "arm,malit860",
1468 reg = <0x0 0xff9a0000 0x0 0x10000>;
1470 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>,
1471 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
1472 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>;
1473 interrupt-names = "GPU", "JOB", "MMU";
1475 clocks = <&cru ACLK_GPU>;
1476 clock-names = "clk_mali";
1477 #cooling-cells = <2>; /* min followed by max */
1478 operating-points-v2 = <&gpu_opp_table>;
1479 power-domains = <&power RK3399_PD_GPU>;
1480 power-off-delay-ms = <200>;
1481 status = "disabled";
1483 gpu_power_model: power_model {
1484 compatible = "arm,mali-simple-power-model";
1487 static-power = <300>;
1488 dynamic-power = <396>;
1489 ts = <32000 4700 (-80) 2>;
1490 thermal-zone = "gpu-thermal";
1494 gpu_opp_table: gpu_opp_table {
1495 compatible = "operating-points-v2";
1499 opp-hz = /bits/ 64 <200000000>;
1500 opp-microvolt = <900000>;
1503 opp-hz = /bits/ 64 <300000000>;
1504 opp-microvolt = <900000>;
1507 opp-hz = /bits/ 64 <400000000>;
1508 opp-microvolt = <900000>;
1513 vopl: vop@ff8f0000 {
1514 compatible = "rockchip,rk3399-vop-lit";
1515 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1516 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1517 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1518 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1519 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1520 reset-names = "axi", "ahb", "dclk";
1521 power-domains = <&power RK3399_PD_VOPL>;
1522 iommus = <&vopl_mmu>;
1523 status = "disabled";
1526 #address-cells = <1>;
1529 vopl_out_mipi: endpoint@0 {
1531 remote-endpoint = <&mipi_in_vopl>;
1534 vopl_out_edp: endpoint@1 {
1536 remote-endpoint = <&edp_in_vopl>;
1539 vopl_out_hdmi: endpoint@2 {
1541 remote-endpoint = <&hdmi_in_vopl>;
1546 vop1_pwm: voppwm@ff8f01a0 {
1547 compatible = "rockchip,vop-pwm";
1548 reg = <0x0 0xff8f01a0 0x0 0x10>;
1550 pinctrl-names = "default";
1551 pinctrl-0 = <&vop1_pwm_pin>;
1552 clocks = <&cru SCLK_VOP1_PWM>;
1553 clock-names = "pwm";
1554 status = "disabled";
1557 vopl_mmu: iommu@ff8f3f00 {
1558 compatible = "rockchip,iommu";
1559 reg = <0x0 0xff8f3f00 0x0 0x100>;
1560 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1561 interrupt-names = "vopl_mmu";
1563 status = "disabled";
1566 vopb: vop@ff900000 {
1567 compatible = "rockchip,rk3399-vop-big";
1568 reg = <0x0 0xff900000 0x0 0x3efc>;
1569 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1570 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1571 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1572 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1573 reset-names = "axi", "ahb", "dclk";
1574 power-domains = <&power RK3399_PD_VOPB>;
1575 iommus = <&vopb_mmu>;
1576 status = "disabled";
1579 #address-cells = <1>;
1582 vopb_out_edp: endpoint@0 {
1584 remote-endpoint = <&edp_in_vopb>;
1587 vopb_out_mipi: endpoint@1 {
1589 remote-endpoint = <&mipi_in_vopb>;
1592 vopb_out_hdmi: endpoint@2 {
1594 remote-endpoint = <&hdmi_in_vopb>;
1599 vop0_pwm: voppwm@ff9001a0 {
1600 compatible = "rockchip,vop-pwm";
1601 reg = <0x0 0xff9001a0 0x0 0x10>;
1603 pinctrl-names = "default";
1604 pinctrl-0 = <&vop0_pwm_pin>;
1605 clocks = <&cru SCLK_VOP0_PWM>;
1606 clock-names = "pwm";
1607 status = "disabled";
1610 vopb_mmu: iommu@ff903f00 {
1611 compatible = "rockchip,iommu";
1612 reg = <0x0 0xff903f00 0x0 0x100>;
1613 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1614 interrupt-names = "vopb_mmu";
1616 status = "disabled";
1619 hdmi: hdmi@ff940000 {
1620 compatible = "rockchip,rk3399-dw-hdmi";
1621 reg = <0x0 0xff940000 0x0 0x20000>;
1623 rockchip,grf = <&grf>;
1624 power-domains = <&power RK3399_PD_HDCP>;
1625 pinctrl-names = "default";
1626 pinctrl-0 = <&hdmi_i2c_xfer>;
1627 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
1628 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_SFR>, <&cru SCLK_HDMI_SFR>, <&cru PCLK_EDP_CTRL>;
1629 clock-names = "iahb", "isfr", "vpll", "grf";
1630 status = "disabled";
1634 #address-cells = <1>;
1636 hdmi_in_vopb: endpoint@0 {
1638 remote-endpoint = <&vopb_out_hdmi>;
1640 hdmi_in_vopl: endpoint@1 {
1642 remote-endpoint = <&vopl_out_hdmi>;
1648 mipi_dsi: mipi@ff960000 {
1649 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1650 reg = <0x0 0xff960000 0x0 0x8000>;
1651 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
1652 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
1653 <&cru SCLK_DPHY_TX0_CFG>;
1654 clock-names = "ref", "pclk", "phy_cfg";
1655 power-domains = <&power RK3399_PD_VIO>;
1656 rockchip,grf = <&grf>;
1657 #address-cells = <1>;
1659 status = "disabled";
1662 #address-cells = <1>;
1667 #address-cells = <1>;
1670 mipi_in_vopb: endpoint@0 {
1672 remote-endpoint = <&vopb_out_mipi>;
1674 mipi_in_vopl: endpoint@1 {
1676 remote-endpoint = <&vopl_out_mipi>;
1683 compatible = "rockchip,rk3399-edp";
1684 reg = <0x0 0xff970000 0x0 0x8000>;
1685 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
1686 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1687 clock-names = "dp", "pclk";
1688 resets = <&cru SRST_P_EDP_CTRL>;
1690 rockchip,grf = <&grf>;
1691 status = "disabled";
1692 pinctrl-names = "default";
1693 pinctrl-0 = <&edp_hpd>;
1696 #address-cells = <1>;
1701 #address-cells = <1>;
1704 edp_in_vopb: endpoint@0 {
1706 remote-endpoint = <&vopb_out_edp>;
1709 edp_in_vopl: endpoint@1 {
1711 remote-endpoint = <&vopl_out_edp>;
1717 display_subsystem: display-subsystem {
1718 compatible = "rockchip,display-subsystem";
1719 ports = <&vopl_out>, <&vopb_out>;
1720 status = "disabled";
1724 compatible = "rockchip,rk3399-pinctrl";
1725 rockchip,grf = <&grf>;
1726 rockchip,pmu = <&pmugrf>;
1727 #address-cells = <0x2>;
1728 #size-cells = <0x2>;
1731 gpio0: gpio0@ff720000 {
1732 compatible = "rockchip,gpio-bank";
1733 reg = <0x0 0xff720000 0x0 0x100>;
1734 clocks = <&pmucru PCLK_GPIO0_PMU>;
1735 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
1738 #gpio-cells = <0x2>;
1740 interrupt-controller;
1741 #interrupt-cells = <0x2>;
1744 gpio1: gpio1@ff730000 {
1745 compatible = "rockchip,gpio-bank";
1746 reg = <0x0 0xff730000 0x0 0x100>;
1747 clocks = <&pmucru PCLK_GPIO1_PMU>;
1748 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
1751 #gpio-cells = <0x2>;
1753 interrupt-controller;
1754 #interrupt-cells = <0x2>;
1757 gpio2: gpio2@ff780000 {
1758 compatible = "rockchip,gpio-bank";
1759 reg = <0x0 0xff780000 0x0 0x100>;
1760 clocks = <&cru PCLK_GPIO2>;
1761 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>;
1764 #gpio-cells = <0x2>;
1766 interrupt-controller;
1767 #interrupt-cells = <0x2>;
1770 gpio3: gpio3@ff788000 {
1771 compatible = "rockchip,gpio-bank";
1772 reg = <0x0 0xff788000 0x0 0x100>;
1773 clocks = <&cru PCLK_GPIO3>;
1774 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
1777 #gpio-cells = <0x2>;
1779 interrupt-controller;
1780 #interrupt-cells = <0x2>;
1783 gpio4: gpio4@ff790000 {
1784 compatible = "rockchip,gpio-bank";
1785 reg = <0x0 0xff790000 0x0 0x100>;
1786 clocks = <&cru PCLK_GPIO4>;
1787 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
1790 #gpio-cells = <0x2>;
1792 interrupt-controller;
1793 #interrupt-cells = <0x2>;
1796 pcfg_pull_up: pcfg-pull-up {
1800 pcfg_pull_down: pcfg-pull-down {
1804 pcfg_pull_none: pcfg-pull-none {
1808 pcfg_pull_up_20ma: pcfg-pull-up-20ma {
1810 drive-strength = <20>;
1813 pcfg_pull_none_20ma: pcfg-pull-none-20ma {
1815 drive-strength = <20>;
1818 pcfg_pull_none_18ma: pcfg-pull-none-18ma {
1820 drive-strength = <18>;
1823 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1825 drive-strength = <12>;
1828 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1830 drive-strength = <8>;
1833 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1835 drive-strength = <4>;
1838 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1840 drive-strength = <2>;
1843 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
1845 drive-strength = <12>;
1848 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
1850 drive-strength = <13>;
1854 emmc_pwr: emmc-pwr {
1856 <0 5 RK_FUNC_1 &pcfg_pull_up>;
1861 rgmii_pins: rgmii-pins {
1864 <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
1866 <3 14 RK_FUNC_1 &pcfg_pull_none>,
1868 <3 13 RK_FUNC_1 &pcfg_pull_none>,
1870 <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1872 <3 11 RK_FUNC_1 &pcfg_pull_none>,
1874 <3 9 RK_FUNC_1 &pcfg_pull_none>,
1876 <3 8 RK_FUNC_1 &pcfg_pull_none>,
1878 <3 7 RK_FUNC_1 &pcfg_pull_none>,
1880 <3 6 RK_FUNC_1 &pcfg_pull_none>,
1882 <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1884 <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
1886 <3 3 RK_FUNC_1 &pcfg_pull_none>,
1888 <3 2 RK_FUNC_1 &pcfg_pull_none>,
1890 <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
1892 <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
1895 rmii_pins: rmii-pins {
1898 <3 13 RK_FUNC_1 &pcfg_pull_none>,
1900 <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1902 <3 11 RK_FUNC_1 &pcfg_pull_none>,
1904 <3 10 RK_FUNC_1 &pcfg_pull_none>,
1906 <3 9 RK_FUNC_1 &pcfg_pull_none>,
1908 <3 8 RK_FUNC_1 &pcfg_pull_none>,
1910 <3 7 RK_FUNC_1 &pcfg_pull_none>,
1912 <3 6 RK_FUNC_1 &pcfg_pull_none>,
1914 <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1916 <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
1921 i2c0_xfer: i2c0-xfer {
1923 <1 15 RK_FUNC_2 &pcfg_pull_none>,
1924 <1 16 RK_FUNC_2 &pcfg_pull_none>;
1929 i2c1_xfer: i2c1-xfer {
1931 <4 2 RK_FUNC_1 &pcfg_pull_none>,
1932 <4 1 RK_FUNC_1 &pcfg_pull_none>;
1937 i2c2_xfer: i2c2-xfer {
1939 <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1940 <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
1945 i2c3_xfer: i2c3-xfer {
1947 <4 17 RK_FUNC_1 &pcfg_pull_none>,
1948 <4 16 RK_FUNC_1 &pcfg_pull_none>;
1951 i2c3_gpio: i2c3_gpio {
1953 <4 17 RK_FUNC_GPIO &pcfg_pull_none>,
1954 <4 16 RK_FUNC_GPIO &pcfg_pull_none>;
1960 i2c4_xfer: i2c4-xfer {
1962 <1 12 RK_FUNC_1 &pcfg_pull_none>,
1963 <1 11 RK_FUNC_1 &pcfg_pull_none>;
1968 i2c5_xfer: i2c5-xfer {
1970 <3 11 RK_FUNC_2 &pcfg_pull_none>,
1971 <3 10 RK_FUNC_2 &pcfg_pull_none>;
1976 i2c6_xfer: i2c6-xfer {
1978 <2 10 RK_FUNC_2 &pcfg_pull_none>,
1979 <2 9 RK_FUNC_2 &pcfg_pull_none>;
1984 i2c7_xfer: i2c7-xfer {
1986 <2 8 RK_FUNC_2 &pcfg_pull_none>,
1987 <2 7 RK_FUNC_2 &pcfg_pull_none>;
1992 i2c8_xfer: i2c8-xfer {
1994 <1 21 RK_FUNC_1 &pcfg_pull_none>,
1995 <1 20 RK_FUNC_1 &pcfg_pull_none>;
2000 i2s0_8ch_bus: i2s0-8ch-bus {
2002 <3 24 RK_FUNC_1 &pcfg_pull_none>,
2003 <3 25 RK_FUNC_1 &pcfg_pull_none>,
2004 <3 26 RK_FUNC_1 &pcfg_pull_none>,
2005 <3 27 RK_FUNC_1 &pcfg_pull_none>,
2006 <3 28 RK_FUNC_1 &pcfg_pull_none>,
2007 <3 29 RK_FUNC_1 &pcfg_pull_none>,
2008 <3 30 RK_FUNC_1 &pcfg_pull_none>,
2009 <3 31 RK_FUNC_1 &pcfg_pull_none>,
2010 <4 0 RK_FUNC_1 &pcfg_pull_none>;
2015 i2s1_2ch_bus: i2s1-2ch-bus {
2017 <4 3 RK_FUNC_1 &pcfg_pull_none>,
2018 <4 4 RK_FUNC_1 &pcfg_pull_none>,
2019 <4 5 RK_FUNC_1 &pcfg_pull_none>,
2020 <4 6 RK_FUNC_1 &pcfg_pull_none>,
2021 <4 7 RK_FUNC_1 &pcfg_pull_none>;
2026 sdio0_bus1: sdio0-bus1 {
2028 <2 20 RK_FUNC_1 &pcfg_pull_up>;
2031 sdio0_bus4: sdio0-bus4 {
2033 <2 20 RK_FUNC_1 &pcfg_pull_up>,
2034 <2 21 RK_FUNC_1 &pcfg_pull_up>,
2035 <2 22 RK_FUNC_1 &pcfg_pull_up>,
2036 <2 23 RK_FUNC_1 &pcfg_pull_up>;
2039 sdio0_cmd: sdio0-cmd {
2041 <2 24 RK_FUNC_1 &pcfg_pull_up>;
2044 sdio0_clk: sdio0-clk {
2046 <2 25 RK_FUNC_1 &pcfg_pull_none>;
2049 sdio0_cd: sdio0-cd {
2051 <2 26 RK_FUNC_1 &pcfg_pull_up>;
2054 sdio0_pwr: sdio0-pwr {
2056 <2 27 RK_FUNC_1 &pcfg_pull_up>;
2059 sdio0_bkpwr: sdio0-bkpwr {
2061 <2 28 RK_FUNC_1 &pcfg_pull_up>;
2064 sdio0_wp: sdio0-wp {
2066 <0 3 RK_FUNC_1 &pcfg_pull_up>;
2069 sdio0_int: sdio0-int {
2071 <0 4 RK_FUNC_1 &pcfg_pull_up>;
2076 sdmmc_bus1: sdmmc-bus1 {
2078 <4 8 RK_FUNC_1 &pcfg_pull_up>;
2081 sdmmc_bus4: sdmmc-bus4 {
2083 <4 8 RK_FUNC_1 &pcfg_pull_up>,
2084 <4 9 RK_FUNC_1 &pcfg_pull_up>,
2085 <4 10 RK_FUNC_1 &pcfg_pull_up>,
2086 <4 11 RK_FUNC_1 &pcfg_pull_up>;
2089 sdmmc_clk: sdmmc-clk {
2091 <4 12 RK_FUNC_1 &pcfg_pull_none>;
2094 sdmmc_cmd: sdmmc-cmd {
2096 <4 13 RK_FUNC_1 &pcfg_pull_up>;
2099 sdmmc_cd: sdmcc-cd {
2101 <0 7 RK_FUNC_1 &pcfg_pull_up>;
2104 sdmmc_wp: sdmmc-wp {
2106 <0 8 RK_FUNC_1 &pcfg_pull_up>;
2111 spdif_bus: spdif-bus {
2113 <4 21 RK_FUNC_1 &pcfg_pull_none>;
2116 spdif_bus_1: spdif-bus-1 {
2118 <3 16 RK_FUNC_3 &pcfg_pull_none>;
2123 spi0_clk: spi0-clk {
2125 <3 6 RK_FUNC_2 &pcfg_pull_up>;
2127 spi0_cs0: spi0-cs0 {
2129 <3 7 RK_FUNC_2 &pcfg_pull_up>;
2131 spi0_cs1: spi0-cs1 {
2133 <3 8 RK_FUNC_2 &pcfg_pull_up>;
2137 <3 5 RK_FUNC_2 &pcfg_pull_up>;
2141 <3 4 RK_FUNC_2 &pcfg_pull_up>;
2146 spi1_clk: spi1-clk {
2148 <1 9 RK_FUNC_2 &pcfg_pull_up>;
2150 spi1_cs0: spi1-cs0 {
2152 <1 10 RK_FUNC_2 &pcfg_pull_up>;
2156 <1 7 RK_FUNC_2 &pcfg_pull_up>;
2160 <1 8 RK_FUNC_2 &pcfg_pull_up>;
2165 spi2_clk: spi2-clk {
2167 <2 11 RK_FUNC_1 &pcfg_pull_up>;
2169 spi2_cs0: spi2-cs0 {
2171 <2 12 RK_FUNC_1 &pcfg_pull_up>;
2175 <2 9 RK_FUNC_1 &pcfg_pull_up>;
2179 <2 10 RK_FUNC_1 &pcfg_pull_up>;
2184 spi3_clk: spi3-clk {
2186 <1 17 RK_FUNC_1 &pcfg_pull_up>;
2188 spi3_cs0: spi3-cs0 {
2190 <1 18 RK_FUNC_1 &pcfg_pull_up>;
2194 <1 15 RK_FUNC_1 &pcfg_pull_up>;
2198 <1 16 RK_FUNC_1 &pcfg_pull_up>;
2203 spi4_clk: spi4-clk {
2205 <3 2 RK_FUNC_2 &pcfg_pull_up>;
2207 spi4_cs0: spi4-cs0 {
2209 <3 3 RK_FUNC_2 &pcfg_pull_up>;
2213 <3 0 RK_FUNC_2 &pcfg_pull_up>;
2217 <3 1 RK_FUNC_2 &pcfg_pull_up>;
2222 spi5_clk: spi5-clk {
2224 <2 22 RK_FUNC_2 &pcfg_pull_up>;
2226 spi5_cs0: spi5-cs0 {
2228 <2 23 RK_FUNC_2 &pcfg_pull_up>;
2232 <2 20 RK_FUNC_2 &pcfg_pull_up>;
2236 <2 21 RK_FUNC_2 &pcfg_pull_up>;
2241 otp_gpio: otp-gpio {
2242 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
2246 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
2251 uart0_xfer: uart0-xfer {
2253 <2 16 RK_FUNC_1 &pcfg_pull_up>,
2254 <2 17 RK_FUNC_1 &pcfg_pull_none>;
2257 uart0_cts: uart0-cts {
2259 <2 18 RK_FUNC_1 &pcfg_pull_none>;
2262 uart0_rts: uart0-rts {
2264 <2 19 RK_FUNC_1 &pcfg_pull_none>;
2269 uart1_xfer: uart1-xfer {
2271 <3 12 RK_FUNC_2 &pcfg_pull_up>,
2272 <3 13 RK_FUNC_2 &pcfg_pull_none>;
2277 uart2a_xfer: uart2a-xfer {
2279 <4 8 RK_FUNC_2 &pcfg_pull_up>,
2280 <4 9 RK_FUNC_2 &pcfg_pull_none>;
2285 uart2b_xfer: uart2b-xfer {
2287 <4 16 RK_FUNC_2 &pcfg_pull_up>,
2288 <4 17 RK_FUNC_2 &pcfg_pull_none>;
2293 uart2c_xfer: uart2c-xfer {
2295 <4 19 RK_FUNC_1 &pcfg_pull_up>,
2296 <4 20 RK_FUNC_1 &pcfg_pull_none>;
2301 uart3_xfer: uart3-xfer {
2303 <3 14 RK_FUNC_2 &pcfg_pull_up>,
2304 <3 15 RK_FUNC_2 &pcfg_pull_none>;
2307 uart3_cts: uart3-cts {
2309 <3 18 RK_FUNC_2 &pcfg_pull_none>;
2312 uart3_rts: uart3-rts {
2314 <3 19 RK_FUNC_2 &pcfg_pull_none>;
2319 uart4_xfer: uart4-xfer {
2321 <1 7 RK_FUNC_1 &pcfg_pull_up>,
2322 <1 8 RK_FUNC_1 &pcfg_pull_none>;
2327 uarthdcp_xfer: uarthdcp-xfer {
2329 <4 21 RK_FUNC_2 &pcfg_pull_up>,
2330 <4 22 RK_FUNC_2 &pcfg_pull_none>;
2335 pwm0_pin: pwm0-pin {
2337 <4 18 RK_FUNC_1 &pcfg_pull_none>;
2340 vop0_pwm_pin: vop0-pwm-pin {
2342 <4 18 RK_FUNC_2 &pcfg_pull_none>;
2347 pwm1_pin: pwm1-pin {
2349 <4 22 RK_FUNC_1 &pcfg_pull_none>;
2352 vop1_pwm_pin: vop1-pwm-pin {
2354 <4 18 RK_FUNC_3 &pcfg_pull_none>;
2359 pwm2_pin: pwm2-pin {
2361 <1 19 RK_FUNC_1 &pcfg_pull_none>;
2366 pwm3a_pin: pwm3a-pin {
2368 <0 6 RK_FUNC_1 &pcfg_pull_none>;
2373 pwm3b_pin: pwm3b-pin {
2375 <1 14 RK_FUNC_1 &pcfg_pull_none>;
2382 <4 23 RK_FUNC_2 &pcfg_pull_none>;
2387 hdmi_i2c_xfer: hdmi-i2c-xfer {
2389 <4 17 RK_FUNC_3 &pcfg_pull_none>,
2390 <4 16 RK_FUNC_3 &pcfg_pull_none>;
2393 hdmi_cec: hdmi-cec {
2395 <4 23 RK_FUNC_1 &pcfg_pull_none>;
2400 pcie_clkreqn: pci-clkreqn {
2402 <2 26 RK_FUNC_2 &pcfg_pull_none>;
2405 pcie_clkreqnb: pci-clkreqnb {
2407 <4 24 RK_FUNC_1 &pcfg_pull_none>;