2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/clock/rk3399-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/interrupt-controller/irq.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/power/rk3399-power.h>
49 #include <dt-bindings/soc/rockchip_boot-mode.h>
50 #include <dt-bindings/thermal/thermal.h>
53 compatible = "rockchip,rk3399";
55 interrupt-parent = <&gic>;
77 compatible = "arm,psci-1.0";
113 compatible = "arm,cortex-a53", "arm,armv8";
115 enable-method = "psci";
116 #cooling-cells = <2>; /* min followed by max */
117 dynamic-power-coefficient = <121>;
118 clocks = <&cru ARMCLKL>;
119 cpu-idle-states = <&cpu_sleep>;
120 operating-points-v2 = <&cluster0_opp>;
121 sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
126 compatible = "arm,cortex-a53", "arm,armv8";
128 enable-method = "psci";
129 clocks = <&cru ARMCLKL>;
130 cpu-idle-states = <&cpu_sleep>;
131 operating-points-v2 = <&cluster0_opp>;
132 sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
137 compatible = "arm,cortex-a53", "arm,armv8";
139 enable-method = "psci";
140 clocks = <&cru ARMCLKL>;
141 cpu-idle-states = <&cpu_sleep>;
142 operating-points-v2 = <&cluster0_opp>;
143 sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
148 compatible = "arm,cortex-a53", "arm,armv8";
150 enable-method = "psci";
151 clocks = <&cru ARMCLKL>;
152 cpu-idle-states = <&cpu_sleep>;
153 operating-points-v2 = <&cluster0_opp>;
154 sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
159 compatible = "arm,cortex-a72", "arm,armv8";
161 enable-method = "psci";
162 #cooling-cells = <2>; /* min followed by max */
163 dynamic-power-coefficient = <1068>;
164 clocks = <&cru ARMCLKB>;
165 cpu-idle-states = <&cpu_sleep>;
166 operating-points-v2 = <&cluster1_opp>;
167 sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>;
172 compatible = "arm,cortex-a72", "arm,armv8";
174 enable-method = "psci";
175 clocks = <&cru ARMCLKB>;
176 cpu-idle-states = <&cpu_sleep>;
177 operating-points-v2 = <&cluster1_opp>;
178 sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>;
182 entry-method = "psci";
183 cpu_sleep: cpu-sleep-0 {
184 compatible = "arm,idle-state";
186 arm,psci-suspend-param = <0x0010000>;
187 entry-latency-us = <350>;
188 exit-latency-us = <600>;
189 min-residency-us = <1150>;
193 /include/ "rk3399-sched-energy.dtsi"
197 cluster0_opp: opp_table0 {
198 compatible = "operating-points-v2";
202 opp-hz = /bits/ 64 <408000000>;
203 opp-microvolt = <800000>;
204 clock-latency-ns = <40000>;
207 opp-hz = /bits/ 64 <600000000>;
208 opp-microvolt = <800000>;
211 opp-hz = /bits/ 64 <816000000>;
212 opp-microvolt = <800000>;
215 opp-hz = /bits/ 64 <1008000000>;
216 opp-microvolt = <875000>;
219 opp-hz = /bits/ 64 <1200000000>;
220 opp-microvolt = <925000>;
223 opp-hz = /bits/ 64 <1416000000>;
224 opp-microvolt = <1025000>;
228 cluster1_opp: opp_table1 {
229 compatible = "operating-points-v2";
233 opp-hz = /bits/ 64 <408000000>;
234 opp-microvolt = <800000>;
235 clock-latency-ns = <40000>;
238 opp-hz = /bits/ 64 <600000000>;
239 opp-microvolt = <800000>;
242 opp-hz = /bits/ 64 <816000000>;
243 opp-microvolt = <800000>;
246 opp-hz = /bits/ 64 <1008000000>;
247 opp-microvolt = <850000>;
250 opp-hz = /bits/ 64 <1200000000>;
251 opp-microvolt = <925000>;
256 compatible = "arm,armv8-timer";
257 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
258 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
259 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
260 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
264 compatible = "arm,armv8-pmuv3";
265 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
269 compatible = "fixed-clock";
271 clock-frequency = <24000000>;
272 clock-output-names = "xin24m";
276 compatible = "arm,amba-bus";
277 #address-cells = <2>;
281 dmac_bus: dma-controller@ff6d0000 {
282 compatible = "arm,pl330", "arm,primecell";
283 reg = <0x0 0xff6d0000 0x0 0x4000>;
284 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
285 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
287 clocks = <&cru ACLK_DMAC0_PERILP>;
288 clock-names = "apb_pclk";
291 dmac_peri: dma-controller@ff6e0000 {
292 compatible = "arm,pl330", "arm,primecell";
293 reg = <0x0 0xff6e0000 0x0 0x4000>;
294 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
295 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
297 clocks = <&cru ACLK_DMAC1_PERILP>;
298 clock-names = "apb_pclk";
303 compatible = "rockchip,rk3399-gmac";
304 reg = <0x0 0xfe300000 0x0 0x10000>;
305 rockchip,grf = <&grf>;
306 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
307 interrupt-names = "macirq";
308 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
309 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
310 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
312 clock-names = "stmmaceth", "mac_clk_rx",
313 "mac_clk_tx", "clk_mac_ref",
314 "clk_mac_refout", "aclk_mac",
316 resets = <&cru SRST_A_GMAC>;
317 reset-names = "stmmaceth";
322 compatible = "rockchip,rk3399-emmc-phy";
323 reg-offset = <0xf780>;
325 rockchip,grf = <&grf>;
326 ctrl-base = <0xfe330000>;
330 sdio0: dwmmc@fe310000 {
331 compatible = "rockchip,rk3399-dw-mshc",
332 "rockchip,rk3288-dw-mshc";
333 reg = <0x0 0xfe310000 0x0 0x4000>;
334 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
335 clock-freq-min-max = <400000 150000000>;
336 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
337 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
338 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
339 fifo-depth = <0x100>;
343 sdmmc: dwmmc@fe320000 {
344 compatible = "rockchip,rk3399-dw-mshc",
345 "rockchip,rk3288-dw-mshc";
346 reg = <0x0 0xfe320000 0x0 0x4000>;
347 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
348 clock-freq-min-max = <400000 150000000>;
349 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
350 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
351 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
352 fifo-depth = <0x100>;
356 sdhci: sdhci@fe330000 {
357 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
358 reg = <0x0 0xfe330000 0x0 0x10000>;
359 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
360 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
361 clock-names = "clk_xin", "clk_ahb";
362 assigned-clocks = <&cru SCLK_EMMC>;
363 assigned-clock-parents = <&cru PLL_CPLL>;
364 assigned-clock-rates = <200000000>;
366 phy-names = "phy_arasan";
371 compatible = "rockchip,rk3399-usb-phy";
372 rockchip,grf = <&grf>;
373 #address-cells = <1>;
376 usb2phy0: usb2-phy0 {
382 usb2phy1: usb2-phy1 {
389 usb_host0_ehci: usb@fe380000 {
390 compatible = "generic-ehci";
391 reg = <0x0 0xfe380000 0x0 0x20000>;
392 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
393 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
394 clock-names = "hclk_host0", "hclk_host0_arb";
396 phy-names = "usb2_phy0";
400 usb_host0_ohci: usb@fe3a0000 {
401 compatible = "generic-ohci";
402 reg = <0x0 0xfe3a0000 0x0 0x20000>;
403 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
404 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
405 clock-names = "hclk_host0", "hclk_host0_arb";
409 usb_host1_ehci: usb@fe3c0000 {
410 compatible = "generic-ehci";
411 reg = <0x0 0xfe3c0000 0x0 0x20000>;
412 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
413 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
414 clock-names = "hclk_host1", "hclk_host1_arb";
416 phy-names = "usb2_phy1";
420 usb_host1_ohci: usb@fe3e0000 {
421 compatible = "generic-ohci";
422 reg = <0x0 0xfe3e0000 0x0 0x20000>;
423 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
424 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
425 clock-names = "hclk_host1", "hclk_host1_arb";
429 usbdrd3_0: usb@fe800000 {
430 compatible = "rockchip,dwc3";
431 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
432 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
433 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
434 clock-names = "clk_usb3otg0_ref", "clk_usb3otg0_suspend",
435 "aclk_usb3otg0", "aclk_usb3_rksoc_axi_perf",
436 "aclk_usb3", "aclk_usb3_grf";
437 #address-cells = <2>;
441 usbdrd_dwc3_0: dwc3@fe800000 {
442 compatible = "snps,dwc3";
443 reg = <0x0 0xfe800000 0x0 0x100000>;
444 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
446 snps,dis_enblslpm_quirk;
447 snps,phyif_utmi_16_bits;
448 snps,dis_u2_freeclk_exists_quirk;
449 snps,dis_del_phy_power_chg_quirk;
450 snps,xhci_slow_suspend_quirk;
455 usbdrd3_1: usb@fe900000 {
456 compatible = "rockchip,dwc3";
457 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
458 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
459 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
460 clock-names = "clk_usb3otg1_ref", "clk_usb3otg1_suspend",
461 "aclk_usb3otg1", "aclk_usb3_rksoc_axi_perf",
462 "aclk_usb3", "aclk_usb3_grf";
463 #address-cells = <2>;
467 usbdrd_dwc3_1: dwc3@fe900000 {
468 compatible = "snps,dwc3";
469 reg = <0x0 0xfe900000 0x0 0x100000>;
470 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
472 snps,dis_enblslpm_quirk;
473 snps,phyif_utmi_16_bits;
474 snps,dis_u2_freeclk_exists_quirk;
475 snps,dis_del_phy_power_chg_quirk;
476 snps,xhci_slow_suspend_quirk;
481 gic: interrupt-controller@fee00000 {
482 compatible = "arm,gic-v3";
483 #interrupt-cells = <3>;
484 #address-cells = <2>;
487 interrupt-controller;
489 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
490 <0x0 0xfef00000 0 0xc0000>, /* GICR */
491 <0x0 0xfff00000 0 0x10000>, /* GICC */
492 <0x0 0xfff10000 0 0x10000>, /* GICH */
493 <0x0 0xfff20000 0 0x10000>; /* GICV */
494 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
495 its: interrupt-controller@fee20000 {
496 compatible = "arm,gic-v3-its";
498 reg = <0x0 0xfee20000 0x0 0x20000>;
502 saradc: saradc@ff100000 {
503 compatible = "rockchip,rk3399-saradc";
504 reg = <0x0 0xff100000 0x0 0x100>;
505 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
506 #io-channel-cells = <1>;
507 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
508 clock-names = "saradc", "apb_pclk";
513 compatible = "rockchip,rk3399-i2c";
514 reg = <0x0 0xff3c0000 0x0 0x1000>;
515 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
516 clock-names = "i2c", "pclk";
517 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
518 pinctrl-names = "default";
519 pinctrl-0 = <&i2c0_xfer>;
520 #address-cells = <1>;
526 compatible = "rockchip,rk3399-i2c";
527 reg = <0x0 0xff110000 0x0 0x1000>;
528 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
529 clock-names = "i2c", "pclk";
530 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
531 pinctrl-names = "default";
532 pinctrl-0 = <&i2c1_xfer>;
533 #address-cells = <1>;
539 compatible = "rockchip,rk3399-i2c";
540 reg = <0x0 0xff120000 0x0 0x1000>;
541 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
542 clock-names = "i2c", "pclk";
543 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
544 pinctrl-names = "default";
545 pinctrl-0 = <&i2c2_xfer>;
546 #address-cells = <1>;
552 compatible = "rockchip,rk3399-i2c";
553 reg = <0x0 0xff130000 0x0 0x1000>;
554 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
555 clock-names = "i2c", "pclk";
556 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
557 pinctrl-names = "default";
558 pinctrl-0 = <&i2c3_xfer>;
559 #address-cells = <1>;
565 compatible = "rockchip,rk3399-i2c";
566 reg = <0x0 0xff140000 0x0 0x1000>;
567 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
568 clock-names = "i2c", "pclk";
569 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
570 pinctrl-names = "default";
571 pinctrl-0 = <&i2c5_xfer>;
572 #address-cells = <1>;
578 compatible = "rockchip,rk3399-i2c";
579 reg = <0x0 0xff150000 0x0 0x1000>;
580 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
581 clock-names = "i2c", "pclk";
582 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
583 pinctrl-names = "default";
584 pinctrl-0 = <&i2c6_xfer>;
585 #address-cells = <1>;
591 compatible = "rockchip,rk3399-i2c";
592 reg = <0x0 0xff160000 0x0 0x1000>;
593 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
594 clock-names = "i2c", "pclk";
595 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
596 pinctrl-names = "default";
597 pinctrl-0 = <&i2c7_xfer>;
598 #address-cells = <1>;
603 uart0: serial@ff180000 {
604 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
605 reg = <0x0 0xff180000 0x0 0x100>;
606 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
607 clock-names = "baudclk", "apb_pclk";
608 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
611 pinctrl-names = "default";
612 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
616 uart1: serial@ff190000 {
617 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
618 reg = <0x0 0xff190000 0x0 0x100>;
619 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
620 clock-names = "baudclk", "apb_pclk";
621 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
624 pinctrl-names = "default";
625 pinctrl-0 = <&uart1_xfer>;
629 uart2: serial@ff1a0000 {
630 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
631 reg = <0x0 0xff1a0000 0x0 0x100>;
632 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
633 clock-names = "baudclk", "apb_pclk";
634 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
637 pinctrl-names = "default";
638 pinctrl-0 = <&uart2c_xfer>;
642 uart3: serial@ff1b0000 {
643 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
644 reg = <0x0 0xff1b0000 0x0 0x100>;
645 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
646 clock-names = "baudclk", "apb_pclk";
647 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
650 pinctrl-names = "default";
651 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
656 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
657 reg = <0x0 0xff1c0000 0x0 0x1000>;
658 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
659 clock-names = "spiclk", "apb_pclk";
660 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
661 pinctrl-names = "default";
662 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
663 #address-cells = <1>;
669 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
670 reg = <0x0 0xff1d0000 0x0 0x1000>;
671 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
672 clock-names = "spiclk", "apb_pclk";
673 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
674 pinctrl-names = "default";
675 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
676 #address-cells = <1>;
682 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
683 reg = <0x0 0xff1e0000 0x0 0x1000>;
684 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
685 clock-names = "spiclk", "apb_pclk";
686 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
687 pinctrl-names = "default";
688 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
689 #address-cells = <1>;
695 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
696 reg = <0x0 0xff1f0000 0x0 0x1000>;
697 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
698 clock-names = "spiclk", "apb_pclk";
699 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
700 pinctrl-names = "default";
701 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
702 #address-cells = <1>;
708 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
709 reg = <0x0 0xff200000 0x0 0x1000>;
710 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
711 clock-names = "spiclk", "apb_pclk";
712 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
713 pinctrl-names = "default";
714 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
715 #address-cells = <1>;
721 soc_thermal: soc-thermal {
722 polling-delay-passive = <100>; /* milliseconds */
723 polling-delay = <1000>; /* milliseconds */
724 sustainable-power = <2600>; /* milliwatts */
726 thermal-sensors = <&tsadc 0>;
729 threshold: trip-point@0 {
730 temperature = <70000>; /* millicelsius */
731 hysteresis = <2000>; /* millicelsius */
734 target: trip-point@1 {
735 temperature = <85000>; /* millicelsius */
736 hysteresis = <2000>; /* millicelsius */
740 temperature = <95000>; /* millicelsius */
741 hysteresis = <2000>; /* millicelsius */
750 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
755 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
760 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
765 gpu_thermal: gpu-thermal {
766 polling-delay-passive = <100>; /* milliseconds */
767 polling-delay = <1000>; /* milliseconds */
769 thermal-sensors = <&tsadc 1>;
773 tsadc: tsadc@ff260000 {
774 compatible = "rockchip,rk3399-tsadc";
775 reg = <0x0 0xff260000 0x0 0x100>;
776 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
777 rockchip,grf = <&grf>;
778 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
779 clock-names = "tsadc", "apb_pclk";
780 assigned-clocks = <&cru SCLK_TSADC>;
781 assigned-clock-rates = <750000>;
782 resets = <&cru SRST_TSADC>;
783 reset-names = "tsadc-apb";
784 pinctrl-names = "init", "default", "sleep";
785 pinctrl-0 = <&otp_gpio>;
786 pinctrl-1 = <&otp_out>;
787 pinctrl-2 = <&otp_gpio>;
788 #thermal-sensor-cells = <1>;
789 rockchip,hw-tshut-temp = <95000>;
793 qos_gpu: qos_gpu@0xffae0000 {
794 compatible ="syscon";
795 reg = <0x0 0xffae0000 0x0 0x20>;
797 qos_video_m0: qos_video_m0@0xffab8000 {
798 compatible ="syscon";
799 reg = <0x0 0xffab8000 0x0 0x20>;
801 qos_video_m1_r: qos_video_m1_r@0xffac0000 {
802 compatible ="syscon";
803 reg = <0x0 0xffac0000 0x0 0x20>;
805 qos_video_m1_w: qos_video_m1_w@0xffac0080 {
806 compatible ="syscon";
807 reg = <0x0 0xffac0080 0x0 0x20>;
809 qos_rga_r: qos_rga_r@0xffab0000 {
810 compatible ="syscon";
811 reg = <0x0 0xffab0000 0x0 0x20>;
813 qos_rga_w: qos_rga_w@0xffab0080 {
814 compatible ="syscon";
815 reg = <0x0 0xffab0000 0x0 0x20>;
817 qos_iep: qos_iep@0xffa98000 {
818 compatible ="syscon";
819 reg = <0x0 0xffa98000 0x0 0x20>;
821 qos_vop_big_r: qos_vop_big_r@0xffac8000 {
822 compatible ="syscon";
823 reg = <0x0 0xffac8000 0x0 0x20>;
825 qos_vop_big_w: qos_vop_big_w@0xffac8080 {
826 compatible ="syscon";
827 reg = <0x0 0xffac8080 0x0 0x20>;
829 qos_vop_little: qos_vop_little@0xffad0000 {
830 compatible ="syscon";
831 reg = <0x0 0xffad0000 0x0 0x20>;
833 qos_isp0_m0: qos_isp0_m0@0xffaa0000 {
834 compatible ="syscon";
835 reg = <0x0 0xffaa0000 0x0 0x20>;
837 qos_isp0_m1: qos_isp0_m1@0xffaa0080 {
838 compatible ="syscon";
839 reg = <0x0 0xffaa0080 0x0 0x20>;
841 qos_isp1_m0: qos_isp1_m0@0xffaa8000 {
842 compatible ="syscon";
843 reg = <0x0 0xffaa8000 0x0 0x20>;
845 qos_isp1_m1: qos_isp1_m1@0xffaa8080 {
846 compatible ="syscon";
847 reg = <0x0 0xffaa8080 0x0 0x20>;
849 qos_hdcp: qos_hdcp@0xffa90000 {
850 compatible ="syscon";
851 reg = <0x0 0xffa90000 0x0 0x20>;
854 pmu: power-management@ff310000 {
855 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
856 reg = <0x0 0xff310000 0x0 0x1000>;
858 power: power-controller {
860 compatible = "rockchip,rk3399-power-controller";
861 #power-domain-cells = <1>;
862 #address-cells = <1>;
867 reg = <RK3399_PD_VDU>;
868 pm_qos = <&qos_video_m1_r>,
872 reg = <RK3399_PD_VCODEC>;
873 pm_qos = <&qos_video_m0>;
876 reg = <RK3399_PD_IEP>;
880 reg = <RK3399_PD_RGA>;
881 pm_qos = <&qos_rga_r>,
885 reg = <RK3399_PD_VIO>;
886 #address-cells = <1>;
890 reg = <RK3399_PD_ISP0>;
891 pm_qos = <&qos_isp0_m0>,
895 reg = <RK3399_PD_ISP1>;
896 pm_qos = <&qos_isp1_m0>,
900 reg = <RK3399_PD_HDCP>;
901 pm_qos = <&qos_hdcp>;
904 reg = <RK3399_PD_VO>;
905 #address-cells = <1>;
909 reg = <RK3399_PD_VOPB>;
910 pm_qos = <&qos_vop_big_r>,
914 reg = <RK3399_PD_VOPL>;
915 pm_qos = <&qos_vop_little>;
920 reg = <RK3399_PD_GPU>;
926 pmugrf: syscon@ff320000 {
927 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
928 reg = <0x0 0xff320000 0x0 0x1000>;
931 compatible = "syscon-reboot-mode";
933 mode-normal = <BOOT_NORMAL>;
934 mode-recovery = <BOOT_RECOVERY>;
935 mode-bootloader = <BOOT_FASTBOOT>;
936 mode-loader = <BOOT_LOADER>;
941 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
942 reg = <0x0 0xff350000 0x0 0x1000>;
943 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
944 clock-names = "spiclk", "apb_pclk";
945 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
946 pinctrl-names = "default";
947 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
948 #address-cells = <1>;
953 uart4: serial@ff370000 {
954 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
955 reg = <0x0 0xff370000 0x0 0x100>;
956 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
957 clock-names = "baudclk", "apb_pclk";
958 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
961 pinctrl-names = "default";
962 pinctrl-0 = <&uart4_xfer>;
967 compatible = "rockchip,rk3399-i2c";
968 reg = <0x0 0xff3d0000 0x0 0x1000>;
969 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
970 clock-names = "i2c", "pclk";
971 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
972 pinctrl-names = "default";
973 pinctrl-0 = <&i2c4_xfer>;
974 #address-cells = <1>;
980 compatible = "rockchip,rk3399-i2c";
981 reg = <0x0 0xff3e0000 0x0 0x1000>;
982 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
983 clock-names = "i2c", "pclk";
984 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
985 pinctrl-names = "default";
986 pinctrl-0 = <&i2c8_xfer>;
987 #address-cells = <1>;
992 pcie0: pcie@f8000000 {
993 compatible = "rockchip,rk3399-pcie";
994 #address-cells = <3>;
996 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
997 <&cru PCLK_PCIE>, <&cru SCLK_PCIEPHY_REF>;
998 clock-names = "aclk_pcie", "aclk_perf_pcie",
999 "hclk_pcie", "clk_pciephy_ref";
1000 bus-range = <0x0 0x1>;
1001 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
1002 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
1003 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
1004 interrupt-names = "pcie-sys", "pcie-legacy", "pcie-client";
1005 ranges = < 0x82000000 0 0xfa000000 0x0 0xfa000000 0 0x600000
1006 0x81000000 0 0xfa600000 0x0 0xfa600000 0 0x100000 >;
1007 reg = < 0x0 0xf8000000 0x0 0x2000000 >,
1008 < 0x0 0xfd000000 0x0 0x1000000 >;
1009 reg-name = "axi-base", "apb-base";
1010 resets = <&cru SRST_PCIEPHY>, <&cru SRST_PCIE_CORE>,
1011 <&cru SRST_PCIE_MGMT>, <&cru SRST_PCIE_MGMT_STICKY>,
1012 <&cru SRST_PCIE_PIPE>;
1013 reset-names = "phy-rst", "core-rst", "mgmt-rst",
1014 "mgmt-sticky-rst", "pipe-rst";
1015 rockchip,grf = <&grf>;
1016 pcie-conf = <0xe220>;
1017 pcie-status = <0xe2a4>;
1018 pcie-laneoff = <0xe214>;
1019 msi-parent = <&its>;
1020 #interrupt-cells = <1>;
1021 interrupt-map-mask = <0 0 0 7>;
1022 interrupt-map = <0 0 0 1 &pcie0 1>,
1026 status = "disabled";
1027 pcie_intc: interrupt-controller {
1028 interrupt-controller;
1029 #address-cells = <0>;
1030 #interrupt-cells = <1>;
1034 pwm0: pwm@ff420000 {
1035 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1036 reg = <0x0 0xff420000 0x0 0x10>;
1038 pinctrl-names = "default";
1039 pinctrl-0 = <&pwm0_pin>;
1040 clocks = <&pmucru PCLK_RKPWM_PMU>;
1041 clock-names = "pwm";
1042 status = "disabled";
1045 pwm1: pwm@ff420010 {
1046 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1047 reg = <0x0 0xff420010 0x0 0x10>;
1049 pinctrl-names = "default";
1050 pinctrl-0 = <&pwm1_pin>;
1051 clocks = <&pmucru PCLK_RKPWM_PMU>;
1052 clock-names = "pwm";
1053 status = "disabled";
1056 pwm2: pwm@ff420020 {
1057 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1058 reg = <0x0 0xff420020 0x0 0x10>;
1060 pinctrl-names = "default";
1061 pinctrl-0 = <&pwm2_pin>;
1062 clocks = <&pmucru PCLK_RKPWM_PMU>;
1063 clock-names = "pwm";
1064 status = "disabled";
1067 pwm3: pwm@ff420030 {
1068 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1069 reg = <0x0 0xff420030 0x0 0x10>;
1071 pinctrl-names = "default";
1072 pinctrl-0 = <&pwm3a_pin>;
1073 clocks = <&pmucru PCLK_RKPWM_PMU>;
1074 clock-names = "pwm";
1075 status = "disabled";
1079 compatible = "rockchip,rk3399-rga";
1080 reg = <0x0 0xff680000 0x0 0x10000>;
1081 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
1082 interrupt-names = "rga";
1083 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
1084 clock-names = "aclk", "hclk", "sclk";
1085 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
1086 reset-names = "core", "axi", "ahb";
1087 status = "disabled";
1090 pmucru: pmu-clock-controller@ff750000 {
1091 compatible = "rockchip,rk3399-pmucru";
1092 reg = <0x0 0xff750000 0x0 0x1000>;
1095 assigned-clocks = <&pmucru PLL_PPLL>;
1096 assigned-clock-rates = <676000000>;
1099 cru: clock-controller@ff760000 {
1100 compatible = "rockchip,rk3399-cru";
1101 reg = <0x0 0xff760000 0x0 0x1000>;
1105 <&cru ACLK_VOP0>, <&cru HCLK_VOP0>,
1106 <&cru ACLK_VOP1>, <&cru HCLK_VOP1>,
1107 <&cru ARMCLKL>, <&cru ARMCLKB>,
1108 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1110 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1112 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1113 <&cru PCLK_PERILP0>,
1114 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
1115 assigned-clock-rates =
1116 <400000000>, <200000000>,
1117 <400000000>, <200000000>,
1118 <816000000>, <816000000>,
1119 <594000000>, <800000000>,
1121 <150000000>, <75000000>,
1123 <100000000>, <100000000>,
1125 <100000000>, <50000000>;
1128 grf: syscon@ff770000 {
1129 compatible = "rockchip,rk3399-grf", "syscon";
1130 reg = <0x0 0xff770000 0x0 0x10000>;
1134 compatible = "snps,dw-wdt";
1135 reg = <0x0 0xff840000 0x0 0x100>;
1136 clocks = <&cru PCLK_WDT>;
1137 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1140 rktimer: rktimer@ff850000 {
1141 compatible = "rockchip,rk3399-timer";
1142 reg = <0x0 0xff850000 0x0 0x1000>;
1143 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1144 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1145 clock-names = "pclk", "timer";
1148 spdif: spdif@ff870000 {
1149 compatible = "rockchip,rk3399-spdif";
1150 reg = <0x0 0xff870000 0x0 0x1000>;
1151 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
1152 dmas = <&dmac_bus 7>;
1154 clock-names = "mclk", "hclk";
1155 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1156 pinctrl-names = "default";
1157 pinctrl-0 = <&spdif_bus>;
1158 status = "disabled";
1161 i2s0: i2s@ff880000 {
1162 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1163 reg = <0x0 0xff880000 0x0 0x1000>;
1164 rockchip,grf = <&grf>;
1165 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1166 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1167 dma-names = "tx", "rx";
1168 clock-names = "i2s_clk", "i2s_hclk";
1169 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1170 pinctrl-names = "default";
1171 pinctrl-0 = <&i2s0_8ch_bus>;
1172 status = "disabled";
1175 i2s1: i2s@ff890000 {
1176 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1177 reg = <0x0 0xff890000 0x0 0x1000>;
1178 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1179 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1180 dma-names = "tx", "rx";
1181 clock-names = "i2s_clk", "i2s_hclk";
1182 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1183 pinctrl-names = "default";
1184 pinctrl-0 = <&i2s1_2ch_bus>;
1185 status = "disabled";
1188 i2s2: i2s@ff8a0000 {
1189 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1190 reg = <0x0 0xff8a0000 0x0 0x1000>;
1191 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1192 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1193 dma-names = "tx", "rx";
1194 clock-names = "i2s_clk", "i2s_hclk";
1195 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1196 status = "disabled";
1200 compatible = "arm,malit860",
1205 reg = <0x0 0xff9a0000 0x0 0x10000>;
1207 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
1208 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
1209 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1210 interrupt-names = "GPU", "JOB", "MMU";
1212 clocks = <&cru ACLK_GPU>;
1213 clock-names = "clk_mali";
1214 #cooling-cells = <2>; /* min followed by max */
1215 operating-points-v2 = <&gpu_opp_table>;
1216 power-domains = <&power RK3399_PD_GPU>;
1217 status = "disabled";
1220 compatible = "arm,mali-simple-power-model";
1223 static-power = <300>;
1224 dynamic-power = <1780>;
1225 ts = <32000 4700 (-80) 2>;
1226 thermal-zone = "gpu-thermal";
1230 gpu_opp_table: gpu_opp_table {
1231 compatible = "operating-points-v2";
1235 opp-hz = /bits/ 64 <200000000>;
1236 opp-microvolt = <900000>;
1239 opp-hz = /bits/ 64 <300000000>;
1240 opp-microvolt = <900000>;
1243 opp-hz = /bits/ 64 <400000000>;
1244 opp-microvolt = <900000>;
1249 vopl: vop@ff8f0000 {
1250 compatible = "rockchip,rk3399-vop-lit";
1251 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1252 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
1253 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1254 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1255 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1256 reset-names = "axi", "ahb", "dclk";
1257 iommus = <&vopl_mmu>;
1258 status = "disabled";
1261 #address-cells = <1>;
1264 vopl_out_mipi: endpoint@0 {
1266 remote-endpoint = <&mipi_in_vopl>;
1269 vopl_out_edp: endpoint@1 {
1271 remote-endpoint = <&edp_in_vopl>;
1276 vopl_mmu: iommu@ff8f3f00 {
1277 compatible = "rockchip,iommu";
1278 reg = <0x0 0xff8f3f00 0x0 0x100>;
1279 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
1280 interrupt-names = "vopl_mmu";
1282 status = "disabled";
1285 vopb: vop@ff900000 {
1286 compatible = "rockchip,rk3399-vop-big";
1287 reg = <0x0 0xff900000 0x0 0x3efc>;
1288 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1289 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1290 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1291 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1292 reset-names = "axi", "ahb", "dclk";
1293 iommus = <&vopb_mmu>;
1294 status = "disabled";
1297 #address-cells = <1>;
1300 vopb_out_edp: endpoint@0 {
1302 remote-endpoint = <&edp_in_vopb>;
1305 vopb_out_mipi: endpoint@1 {
1307 remote-endpoint = <&mipi_in_vopb>;
1312 vopb_mmu: iommu@ff903f00 {
1313 compatible = "rockchip,iommu";
1314 reg = <0x0 0xff903f00 0x0 0x100>;
1315 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1316 interrupt-names = "vopb_mmu";
1318 status = "disabled";
1321 mipi_dsi: mipi@ff960000 {
1322 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1323 reg = <0x0 0xff960000 0x0 0x8000>;
1324 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1325 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
1326 <&cru SCLK_DPHY_TX0_CFG>;
1327 clock-names = "ref", "pclk", "phy_cfg";
1328 rockchip,grf = <&grf>;
1329 #address-cells = <1>;
1331 status = "disabled";
1334 #address-cells = <1>;
1339 #address-cells = <1>;
1342 mipi_in_vopb: endpoint@0 {
1344 remote-endpoint = <&vopb_out_mipi>;
1346 mipi_in_vopl: endpoint@1 {
1348 remote-endpoint = <&vopl_out_mipi>;
1355 compatible = "rockchip,rk3399-edp";
1356 reg = <0x0 0xff970000 0x0 0x8000>;
1357 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1358 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1359 clock-names = "dp", "pclk";
1360 resets = <&cru SRST_P_EDP_CTRL>;
1362 rockchip,grf = <&grf>;
1363 status = "disabled";
1364 pinctrl-names = "default";
1365 pinctrl-0 = <&edp_hpd>;
1368 #address-cells = <1>;
1373 #address-cells = <1>;
1376 edp_in_vopb: endpoint@0 {
1378 remote-endpoint = <&vopb_out_edp>;
1381 edp_in_vopl: endpoint@1 {
1383 remote-endpoint = <&vopl_out_edp>;
1389 display_subsystem: display-subsystem {
1390 compatible = "rockchip,display-subsystem";
1391 ports = <&vopl_out>, <&vopb_out>;
1392 status = "disabled";
1396 compatible = "rockchip,rk3399-pinctrl";
1397 rockchip,grf = <&grf>;
1398 rockchip,pmu = <&pmugrf>;
1399 #address-cells = <0x2>;
1400 #size-cells = <0x2>;
1403 gpio0: gpio0@ff720000 {
1404 compatible = "rockchip,gpio-bank";
1405 reg = <0x0 0xff720000 0x0 0x100>;
1406 clocks = <&pmucru PCLK_GPIO0_PMU>;
1407 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1410 #gpio-cells = <0x2>;
1412 interrupt-controller;
1413 #interrupt-cells = <0x2>;
1416 gpio1: gpio1@ff730000 {
1417 compatible = "rockchip,gpio-bank";
1418 reg = <0x0 0xff730000 0x0 0x100>;
1419 clocks = <&pmucru PCLK_GPIO1_PMU>;
1420 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1423 #gpio-cells = <0x2>;
1425 interrupt-controller;
1426 #interrupt-cells = <0x2>;
1429 gpio2: gpio2@ff780000 {
1430 compatible = "rockchip,gpio-bank";
1431 reg = <0x0 0xff780000 0x0 0x100>;
1432 clocks = <&cru PCLK_GPIO2>;
1433 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1436 #gpio-cells = <0x2>;
1438 interrupt-controller;
1439 #interrupt-cells = <0x2>;
1442 gpio3: gpio3@ff788000 {
1443 compatible = "rockchip,gpio-bank";
1444 reg = <0x0 0xff788000 0x0 0x100>;
1445 clocks = <&cru PCLK_GPIO3>;
1446 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1449 #gpio-cells = <0x2>;
1451 interrupt-controller;
1452 #interrupt-cells = <0x2>;
1455 gpio4: gpio4@ff790000 {
1456 compatible = "rockchip,gpio-bank";
1457 reg = <0x0 0xff790000 0x0 0x100>;
1458 clocks = <&cru PCLK_GPIO4>;
1459 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1462 #gpio-cells = <0x2>;
1464 interrupt-controller;
1465 #interrupt-cells = <0x2>;
1468 pcfg_pull_up: pcfg-pull-up {
1472 pcfg_pull_down: pcfg-pull-down {
1476 pcfg_pull_none: pcfg-pull-none {
1480 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1482 drive-strength = <12>;
1485 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1487 drive-strength = <8>;
1490 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1492 drive-strength = <4>;
1495 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1497 drive-strength = <2>;
1500 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
1502 drive-strength = <12>;
1505 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
1507 drive-strength = <13>;
1511 emmc_pwr: emmc-pwr {
1513 <0 5 RK_FUNC_1 &pcfg_pull_up>;
1518 rgmii_pins: rgmii-pins {
1521 <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
1523 <3 14 RK_FUNC_1 &pcfg_pull_none>,
1525 <3 13 RK_FUNC_1 &pcfg_pull_none>,
1527 <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1529 <3 11 RK_FUNC_1 &pcfg_pull_none>,
1531 <3 9 RK_FUNC_1 &pcfg_pull_none>,
1533 <3 8 RK_FUNC_1 &pcfg_pull_none>,
1535 <3 7 RK_FUNC_1 &pcfg_pull_none>,
1537 <3 6 RK_FUNC_1 &pcfg_pull_none>,
1539 <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1541 <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
1543 <3 3 RK_FUNC_1 &pcfg_pull_none>,
1545 <3 2 RK_FUNC_1 &pcfg_pull_none>,
1547 <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
1549 <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
1552 rmii_pins: rmii-pins {
1555 <3 13 RK_FUNC_1 &pcfg_pull_none>,
1557 <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1559 <3 11 RK_FUNC_1 &pcfg_pull_none>,
1561 <3 10 RK_FUNC_1 &pcfg_pull_none>,
1563 <3 9 RK_FUNC_1 &pcfg_pull_none>,
1565 <3 8 RK_FUNC_1 &pcfg_pull_none>,
1567 <3 7 RK_FUNC_1 &pcfg_pull_none>,
1569 <3 6 RK_FUNC_1 &pcfg_pull_none>,
1571 <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1573 <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
1578 i2c0_xfer: i2c0-xfer {
1580 <1 15 RK_FUNC_2 &pcfg_pull_none>,
1581 <1 16 RK_FUNC_2 &pcfg_pull_none>;
1586 i2c1_xfer: i2c1-xfer {
1588 <4 2 RK_FUNC_1 &pcfg_pull_none>,
1589 <4 1 RK_FUNC_1 &pcfg_pull_none>;
1594 i2c2_xfer: i2c2-xfer {
1596 <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1597 <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
1602 i2c3_xfer: i2c3-xfer {
1604 <4 17 RK_FUNC_1 &pcfg_pull_none>,
1605 <4 16 RK_FUNC_1 &pcfg_pull_none>;
1608 i2c3_gpio: i2c3_gpio {
1610 <4 17 RK_FUNC_GPIO &pcfg_pull_none>,
1611 <4 16 RK_FUNC_GPIO &pcfg_pull_none>;
1617 i2c4_xfer: i2c4-xfer {
1619 <1 12 RK_FUNC_1 &pcfg_pull_none>,
1620 <1 11 RK_FUNC_1 &pcfg_pull_none>;
1625 i2c5_xfer: i2c5-xfer {
1627 <3 11 RK_FUNC_2 &pcfg_pull_none>,
1628 <3 10 RK_FUNC_2 &pcfg_pull_none>;
1633 i2c6_xfer: i2c6-xfer {
1635 <2 10 RK_FUNC_2 &pcfg_pull_none>,
1636 <2 9 RK_FUNC_2 &pcfg_pull_none>;
1641 i2c7_xfer: i2c7-xfer {
1643 <2 8 RK_FUNC_2 &pcfg_pull_none>,
1644 <2 7 RK_FUNC_2 &pcfg_pull_none>;
1649 i2c8_xfer: i2c8-xfer {
1651 <1 21 RK_FUNC_1 &pcfg_pull_none>,
1652 <1 20 RK_FUNC_1 &pcfg_pull_none>;
1657 i2s0_8ch_bus: i2s0-8ch-bus {
1659 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1660 <3 25 RK_FUNC_1 &pcfg_pull_none>,
1661 <3 26 RK_FUNC_1 &pcfg_pull_none>,
1662 <3 27 RK_FUNC_1 &pcfg_pull_none>,
1663 <3 28 RK_FUNC_1 &pcfg_pull_none>,
1664 <3 29 RK_FUNC_1 &pcfg_pull_none>,
1665 <3 30 RK_FUNC_1 &pcfg_pull_none>,
1666 <3 31 RK_FUNC_1 &pcfg_pull_none>,
1667 <4 0 RK_FUNC_1 &pcfg_pull_none>;
1672 i2s1_2ch_bus: i2s1-2ch-bus {
1674 <4 3 RK_FUNC_1 &pcfg_pull_none>,
1675 <4 4 RK_FUNC_1 &pcfg_pull_none>,
1676 <4 5 RK_FUNC_1 &pcfg_pull_none>,
1677 <4 6 RK_FUNC_1 &pcfg_pull_none>,
1678 <4 7 RK_FUNC_1 &pcfg_pull_none>;
1683 sdio0_bus1: sdio0-bus1 {
1685 <2 20 RK_FUNC_1 &pcfg_pull_up>;
1688 sdio0_bus4: sdio0-bus4 {
1690 <2 20 RK_FUNC_1 &pcfg_pull_up>,
1691 <2 21 RK_FUNC_1 &pcfg_pull_up>,
1692 <2 22 RK_FUNC_1 &pcfg_pull_up>,
1693 <2 23 RK_FUNC_1 &pcfg_pull_up>;
1696 sdio0_cmd: sdio0-cmd {
1698 <2 24 RK_FUNC_1 &pcfg_pull_up>;
1701 sdio0_clk: sdio0-clk {
1703 <2 25 RK_FUNC_1 &pcfg_pull_none>;
1706 sdio0_cd: sdio0-cd {
1708 <2 26 RK_FUNC_1 &pcfg_pull_up>;
1711 sdio0_pwr: sdio0-pwr {
1713 <2 27 RK_FUNC_1 &pcfg_pull_up>;
1716 sdio0_bkpwr: sdio0-bkpwr {
1718 <2 28 RK_FUNC_1 &pcfg_pull_up>;
1721 sdio0_wp: sdio0-wp {
1723 <0 3 RK_FUNC_1 &pcfg_pull_up>;
1726 sdio0_int: sdio0-int {
1728 <0 4 RK_FUNC_1 &pcfg_pull_up>;
1733 sdmmc_bus1: sdmmc-bus1 {
1735 <4 8 RK_FUNC_1 &pcfg_pull_up>;
1738 sdmmc_bus4: sdmmc-bus4 {
1740 <4 8 RK_FUNC_1 &pcfg_pull_up>,
1741 <4 9 RK_FUNC_1 &pcfg_pull_up>,
1742 <4 10 RK_FUNC_1 &pcfg_pull_up>,
1743 <4 11 RK_FUNC_1 &pcfg_pull_up>;
1746 sdmmc_clk: sdmmc-clk {
1748 <4 12 RK_FUNC_1 &pcfg_pull_none>;
1751 sdmmc_cmd: sdmmc-cmd {
1753 <4 13 RK_FUNC_1 &pcfg_pull_up>;
1756 sdmmc_cd: sdmcc-cd {
1758 <0 7 RK_FUNC_1 &pcfg_pull_up>;
1761 sdmmc_wp: sdmmc-wp {
1763 <0 8 RK_FUNC_1 &pcfg_pull_up>;
1768 spdif_bus: spdif-bus {
1770 <4 21 RK_FUNC_1 &pcfg_pull_none>;
1775 spi0_clk: spi0-clk {
1777 <3 6 RK_FUNC_2 &pcfg_pull_up>;
1779 spi0_cs0: spi0-cs0 {
1781 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1783 spi0_cs1: spi0-cs1 {
1785 <3 8 RK_FUNC_2 &pcfg_pull_up>;
1789 <3 5 RK_FUNC_2 &pcfg_pull_up>;
1793 <3 4 RK_FUNC_2 &pcfg_pull_up>;
1798 spi1_clk: spi1-clk {
1800 <1 9 RK_FUNC_2 &pcfg_pull_up>;
1802 spi1_cs0: spi1-cs0 {
1804 <1 10 RK_FUNC_2 &pcfg_pull_up>;
1808 <1 7 RK_FUNC_2 &pcfg_pull_up>;
1812 <1 8 RK_FUNC_2 &pcfg_pull_up>;
1817 spi2_clk: spi2-clk {
1819 <2 11 RK_FUNC_1 &pcfg_pull_up>;
1821 spi2_cs0: spi2-cs0 {
1823 <2 12 RK_FUNC_1 &pcfg_pull_up>;
1827 <2 9 RK_FUNC_1 &pcfg_pull_up>;
1831 <2 10 RK_FUNC_1 &pcfg_pull_up>;
1836 spi3_clk: spi3-clk {
1838 <1 17 RK_FUNC_1 &pcfg_pull_up>;
1840 spi3_cs0: spi3-cs0 {
1842 <1 18 RK_FUNC_1 &pcfg_pull_up>;
1846 <1 15 RK_FUNC_1 &pcfg_pull_up>;
1850 <1 16 RK_FUNC_1 &pcfg_pull_up>;
1855 spi4_clk: spi4-clk {
1857 <3 2 RK_FUNC_2 &pcfg_pull_up>;
1859 spi4_cs0: spi4-cs0 {
1861 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1865 <3 0 RK_FUNC_2 &pcfg_pull_up>;
1869 <3 1 RK_FUNC_2 &pcfg_pull_up>;
1874 spi5_clk: spi5-clk {
1876 <2 22 RK_FUNC_2 &pcfg_pull_up>;
1878 spi5_cs0: spi5-cs0 {
1880 <2 23 RK_FUNC_2 &pcfg_pull_up>;
1884 <2 20 RK_FUNC_2 &pcfg_pull_up>;
1888 <2 21 RK_FUNC_2 &pcfg_pull_up>;
1893 otp_gpio: otp-gpio {
1894 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
1898 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
1903 uart0_xfer: uart0-xfer {
1905 <2 16 RK_FUNC_1 &pcfg_pull_up>,
1906 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1909 uart0_cts: uart0-cts {
1911 <2 18 RK_FUNC_1 &pcfg_pull_none>;
1914 uart0_rts: uart0-rts {
1916 <2 19 RK_FUNC_1 &pcfg_pull_none>;
1921 uart1_xfer: uart1-xfer {
1923 <3 12 RK_FUNC_2 &pcfg_pull_up>,
1924 <3 13 RK_FUNC_2 &pcfg_pull_none>;
1929 uart2a_xfer: uart2a-xfer {
1931 <4 8 RK_FUNC_2 &pcfg_pull_up>,
1932 <4 9 RK_FUNC_2 &pcfg_pull_none>;
1937 uart2b_xfer: uart2b-xfer {
1939 <4 16 RK_FUNC_2 &pcfg_pull_up>,
1940 <4 17 RK_FUNC_2 &pcfg_pull_none>;
1945 uart2c_xfer: uart2c-xfer {
1947 <4 19 RK_FUNC_1 &pcfg_pull_up>,
1948 <4 20 RK_FUNC_1 &pcfg_pull_none>;
1953 uart3_xfer: uart3-xfer {
1955 <3 14 RK_FUNC_2 &pcfg_pull_up>,
1956 <3 15 RK_FUNC_2 &pcfg_pull_none>;
1959 uart3_cts: uart3-cts {
1961 <3 18 RK_FUNC_2 &pcfg_pull_none>;
1964 uart3_rts: uart3-rts {
1966 <3 19 RK_FUNC_2 &pcfg_pull_none>;
1971 uart4_xfer: uart4-xfer {
1973 <1 7 RK_FUNC_1 &pcfg_pull_up>,
1974 <1 8 RK_FUNC_1 &pcfg_pull_none>;
1979 uarthdcp_xfer: uarthdcp-xfer {
1981 <4 21 RK_FUNC_2 &pcfg_pull_up>,
1982 <4 22 RK_FUNC_2 &pcfg_pull_none>;
1987 pwm0_pin: pwm0-pin {
1989 <4 18 RK_FUNC_1 &pcfg_pull_none>;
1992 vop0_pwm_pin: vop0-pwm-pin {
1994 <4 18 RK_FUNC_2 &pcfg_pull_none>;
1999 pwm1_pin: pwm1-pin {
2001 <4 22 RK_FUNC_1 &pcfg_pull_none>;
2004 vop1_pwm_pin: vop1-pwm-pin {
2006 <4 18 RK_FUNC_3 &pcfg_pull_none>;
2011 pwm2_pin: pwm2-pin {
2013 <1 19 RK_FUNC_1 &pcfg_pull_none>;
2018 pwm3a_pin: pwm3a-pin {
2020 <0 6 RK_FUNC_1 &pcfg_pull_none>;
2025 pwm3b_pin: pwm3b-pin {
2027 <1 14 RK_FUNC_1 &pcfg_pull_none>;
2034 <4 23 RK_FUNC_2 &pcfg_pull_none>;
2039 hdmi_i2c_xfer: hdmi-i2c-xfer {
2041 <4 17 RK_FUNC_3 &pcfg_pull_none>,
2042 <4 16 RK_FUNC_3 &pcfg_pull_none>;
2045 hdmi_cec: hdmi-cec {
2047 <4 23 RK_FUNC_1 &pcfg_pull_none>;
2052 pcie_clkreqn: pci-clkreqn {
2054 <2 26 RK_FUNC_2 &pcfg_pull_none>;
2057 pcie_clkreqnb: pci-clkreqnb {
2059 <4 24 RK_FUNC_1 &pcfg_pull_none>;