2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/clock/rk3399-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/interrupt-controller/irq.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/power/rk3399-power.h>
49 #include <dt-bindings/thermal/thermal.h>
52 compatible = "rockchip,rk3399";
53 interrupt-parent = <&gic>;
75 compatible = "arm,psci-1.0";
111 compatible = "arm,cortex-a53", "arm,armv8";
113 enable-method = "psci";
114 #cooling-cells = <2>; /* min followed by max */
115 clocks = <&cru ARMCLKL>;
116 cpu-idle-states = <&cpu_sleep>;
117 operating-points-v2 = <&cluster0_opp>;
122 compatible = "arm,cortex-a53", "arm,armv8";
124 enable-method = "psci";
125 clocks = <&cru ARMCLKL>;
126 cpu-idle-states = <&cpu_sleep>;
127 operating-points-v2 = <&cluster0_opp>;
132 compatible = "arm,cortex-a53", "arm,armv8";
134 enable-method = "psci";
135 clocks = <&cru ARMCLKL>;
136 cpu-idle-states = <&cpu_sleep>;
137 operating-points-v2 = <&cluster0_opp>;
142 compatible = "arm,cortex-a53", "arm,armv8";
144 enable-method = "psci";
145 clocks = <&cru ARMCLKL>;
146 cpu-idle-states = <&cpu_sleep>;
147 operating-points-v2 = <&cluster0_opp>;
152 compatible = "arm,cortex-a72", "arm,armv8";
154 enable-method = "psci";
155 #cooling-cells = <2>; /* min followed by max */
156 clocks = <&cru ARMCLKB>;
157 cpu-idle-states = <&cpu_sleep>;
158 operating-points-v2 = <&cluster1_opp>;
163 compatible = "arm,cortex-a72", "arm,armv8";
165 enable-method = "psci";
166 clocks = <&cru ARMCLKB>;
167 cpu-idle-states = <&cpu_sleep>;
168 operating-points-v2 = <&cluster1_opp>;
172 entry-method = "psci";
173 cpu_sleep: cpu-sleep-0 {
174 compatible = "arm,idle-state";
176 arm,psci-suspend-param = <0x0010000>;
177 entry-latency-us = <350>;
178 exit-latency-us = <600>;
179 min-residency-us = <1150>;
184 cluster0_opp: opp_table0 {
185 compatible = "operating-points-v2";
189 opp-hz = /bits/ 64 <408000000>;
190 opp-microvolt = <800000>;
191 clock-latency-ns = <40000>;
194 opp-hz = /bits/ 64 <600000000>;
195 opp-microvolt = <800000>;
198 opp-hz = /bits/ 64 <816000000>;
199 opp-microvolt = <800000>;
202 opp-hz = /bits/ 64 <1008000000>;
203 opp-microvolt = <875000>;
206 opp-hz = /bits/ 64 <1200000000>;
207 opp-microvolt = <925000>;
210 opp-hz = /bits/ 64 <1416000000>;
211 opp-microvolt = <1025000>;
215 cluster1_opp: opp_table1 {
216 compatible = "operating-points-v2";
220 opp-hz = /bits/ 64 <408000000>;
221 opp-microvolt = <800000>;
222 clock-latency-ns = <40000>;
225 opp-hz = /bits/ 64 <600000000>;
226 opp-microvolt = <800000>;
229 opp-hz = /bits/ 64 <816000000>;
230 opp-microvolt = <800000>;
233 opp-hz = /bits/ 64 <1008000000>;
234 opp-microvolt = <850000>;
237 opp-hz = /bits/ 64 <1200000000>;
238 opp-microvolt = <925000>;
243 compatible = "arm,armv8-timer";
244 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
245 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
246 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
247 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
251 compatible = "arm,armv8-pmuv3";
252 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
256 compatible = "fixed-clock";
258 clock-frequency = <24000000>;
259 clock-output-names = "xin24m";
263 compatible = "arm,amba-bus";
264 #address-cells = <2>;
268 dmac_bus: dma-controller@ff6d0000 {
269 compatible = "arm,pl330", "arm,primecell";
270 reg = <0x0 0xff6d0000 0x0 0x4000>;
271 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
272 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
274 clocks = <&cru ACLK_DMAC0_PERILP>;
275 clock-names = "apb_pclk";
278 dmac_peri: dma-controller@ff6e0000 {
279 compatible = "arm,pl330", "arm,primecell";
280 reg = <0x0 0xff6e0000 0x0 0x4000>;
281 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
282 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
284 clocks = <&cru ACLK_DMAC1_PERILP>;
285 clock-names = "apb_pclk";
290 compatible = "rockchip,rk3399-gmac";
291 reg = <0x0 0xfe300000 0x0 0x10000>;
292 rockchip,grf = <&grf>;
293 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
294 interrupt-names = "macirq";
295 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
296 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
297 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
299 clock-names = "stmmaceth", "mac_clk_rx",
300 "mac_clk_tx", "clk_mac_ref",
301 "clk_mac_refout", "aclk_mac",
303 resets = <&cru SRST_A_GMAC>;
304 reset-names = "stmmaceth";
309 compatible = "rockchip,rk3399-emmc-phy";
310 reg-offset = <0xf780>;
312 rockchip,grf = <&grf>;
316 sdio0: dwmmc@fe310000 {
317 compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc";
318 reg = <0x0 0xfe310000 0x0 0x4000>;
319 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
320 clock-freq-min-max = <400000 150000000>;
321 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
322 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
323 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
324 fifo-depth = <0x100>;
328 sdmmc: dwmmc@fe320000 {
329 compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc";
330 reg = <0x0 0xfe320000 0x0 0x4000>;
331 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
332 clock-freq-min-max = <400000 150000000>;
333 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
334 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
335 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
336 fifo-depth = <0x100>;
340 sdhci: sdhci@fe330000 {
341 compatible = "arasan,sdhci-5.1";
342 reg = <0x0 0xfe330000 0x0 0x10000>;
343 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
344 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
345 clock-names = "clk_xin", "clk_ahb";
346 assigned-clocks = <&cru SCLK_EMMC>;
347 assigned-clock-parents = <&cru PLL_CPLL>;
348 assigned-clock-rates = <200000000>;
350 phy-names = "phy_arasan";
355 compatible = "rockchip,rk3399-usb-phy";
356 rockchip,grf = <&grf>;
357 #address-cells = <1>;
360 usb2phy0: usb2-phy0 {
366 usb2phy1: usb2-phy1 {
373 usb_host0_echi: usb@fe380000 {
374 compatible = "generic-ehci";
375 reg = <0x0 0xfe380000 0x0 0x20000>;
376 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
377 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
378 clock-names = "hclk_host0", "hclk_host0_arb";
380 phy-names = "usb2_phy0";
384 usb_host0_ohci: usb@fe3a0000 {
385 compatible = "generic-ohci";
386 reg = <0x0 0xfe3a0000 0x0 0x20000>;
387 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
388 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
389 clock-names = "hclk_host0", "hclk_host0_arb";
393 usb_host1_echi: usb@fe3c0000 {
394 compatible = "generic-ehci";
395 reg = <0x0 0xfe3c0000 0x0 0x20000>;
396 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
397 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
398 clock-names = "hclk_host1", "hclk_host1_arb";
400 phy-names = "usb2_phy1";
404 usb_host1_ohci: usb@fe3e0000 {
405 compatible = "generic-ohci";
406 reg = <0x0 0xfe3e0000 0x0 0x20000>;
407 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
408 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
409 clock-names = "hclk_host1", "hclk_host1_arb";
413 usbdrd3_0: usb@fe800000 {
414 compatible = "rockchip,dwc3";
415 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
416 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
417 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
418 clock-names = "clk_usb3otg0_ref", "clk_usb3otg0_suspend",
419 "aclk_usb3otg0", "aclk_usb3_rksoc_axi_perf",
420 "aclk_usb3", "aclk_usb3_grf";
421 #address-cells = <2>;
425 usbdrd_dwc3_0: dwc3 {
426 compatible = "snps,dwc3";
427 reg = <0x0 0xfe800000 0x0 0x100000>;
428 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
431 snps,dis_enblslpm_quirk;
432 snps,phyif_utmi_16_bits;
433 snps,dis_u2_freeclk_exists_quirk;
434 snps,dis_del_phy_power_chg_quirk;
439 usbdrd3_1: usb@fe900000 {
440 compatible = "rockchip,dwc3";
441 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
442 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
443 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
444 clock-names = "clk_usb3otg1_ref", "clk_usb3otg1_suspend",
445 "aclk_usb3otg1", "aclk_usb3_rksoc_axi_perf",
446 "aclk_usb3", "aclk_usb3_grf";
447 #address-cells = <2>;
451 usbdrd_dwc3_1: dwc3 {
452 compatible = "snps,dwc3";
453 reg = <0x0 0xfe900000 0x0 0x100000>;
454 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
457 snps,dis_enblslpm_quirk;
458 snps,phyif_utmi_16_bits;
459 snps,dis_u2_freeclk_exists_quirk;
460 snps,dis_del_phy_power_chg_quirk;
465 gic: interrupt-controller@fee00000 {
466 compatible = "arm,gic-v3";
467 #interrupt-cells = <3>;
468 #address-cells = <2>;
471 interrupt-controller;
473 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
474 <0x0 0xfef00000 0 0xc0000>, /* GICR */
475 <0x0 0xfff00000 0 0x10000>, /* GICC */
476 <0x0 0xfff10000 0 0x10000>, /* GICH */
477 <0x0 0xfff20000 0 0x10000>; /* GICV */
478 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
479 its: interrupt-controller@fee20000 {
480 compatible = "arm,gic-v3-its";
482 reg = <0x0 0xfee20000 0x0 0x20000>;
486 saradc: saradc@ff100000 {
487 compatible = "rockchip,rk3399-saradc";
488 reg = <0x0 0xff100000 0x0 0x100>;
489 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
490 #io-channel-cells = <1>;
491 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
492 clock-names = "saradc", "apb_pclk";
497 compatible = "rockchip,rk3399-i2c";
498 reg = <0x0 0xff3c0000 0x0 0x1000>;
499 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
500 clock-names = "i2c", "pclk";
501 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
502 pinctrl-names = "default";
503 pinctrl-0 = <&i2c0_xfer>;
504 #address-cells = <1>;
510 compatible = "rockchip,rk3399-i2c";
511 reg = <0x0 0xff110000 0x0 0x1000>;
512 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
513 clock-names = "i2c", "pclk";
514 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
515 pinctrl-names = "default";
516 pinctrl-0 = <&i2c1_xfer>;
517 #address-cells = <1>;
523 compatible = "rockchip,rk3399-i2c";
524 reg = <0x0 0xff120000 0x0 0x1000>;
525 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
526 clock-names = "i2c", "pclk";
527 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
528 pinctrl-names = "default";
529 pinctrl-0 = <&i2c2_xfer>;
530 #address-cells = <1>;
536 compatible = "rockchip,rk3399-i2c";
537 reg = <0x0 0xff130000 0x0 0x1000>;
538 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
539 clock-names = "i2c", "pclk";
540 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
541 pinctrl-names = "default";
542 pinctrl-0 = <&i2c3_xfer>;
543 #address-cells = <1>;
549 compatible = "rockchip,rk3399-i2c";
550 reg = <0x0 0xff140000 0x0 0x1000>;
551 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
552 clock-names = "i2c", "pclk";
553 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
554 pinctrl-names = "default";
555 pinctrl-0 = <&i2c5_xfer>;
556 #address-cells = <1>;
562 compatible = "rockchip,rk3399-i2c";
563 reg = <0x0 0xff150000 0x0 0x1000>;
564 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
565 clock-names = "i2c", "pclk";
566 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
567 pinctrl-names = "default";
568 pinctrl-0 = <&i2c6_xfer>;
569 #address-cells = <1>;
575 compatible = "rockchip,rk3399-i2c";
576 reg = <0x0 0xff160000 0x0 0x1000>;
577 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
578 clock-names = "i2c", "pclk";
579 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
580 pinctrl-names = "default";
581 pinctrl-0 = <&i2c7_xfer>;
582 #address-cells = <1>;
587 uart0: serial@ff180000 {
588 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
589 reg = <0x0 0xff180000 0x0 0x100>;
590 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
591 clock-names = "baudclk", "apb_pclk";
592 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
595 pinctrl-names = "default";
596 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
600 uart1: serial@ff190000 {
601 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
602 reg = <0x0 0xff190000 0x0 0x100>;
603 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
604 clock-names = "baudclk", "apb_pclk";
605 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
608 pinctrl-names = "default";
609 pinctrl-0 = <&uart1_xfer>;
613 uart2: serial@ff1a0000 {
614 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
615 reg = <0x0 0xff1a0000 0x0 0x100>;
616 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
617 clock-names = "baudclk", "apb_pclk";
618 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
621 pinctrl-names = "default";
622 pinctrl-0 = <&uart2c_xfer>;
626 uart3: serial@ff1b0000 {
627 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
628 reg = <0x0 0xff1b0000 0x0 0x100>;
629 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
630 clock-names = "baudclk", "apb_pclk";
631 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
634 pinctrl-names = "default";
635 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
640 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
641 reg = <0x0 0xff1c0000 0x0 0x1000>;
642 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
643 clock-names = "spiclk", "apb_pclk";
644 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
645 pinctrl-names = "default";
646 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
647 #address-cells = <1>;
653 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
654 reg = <0x0 0xff1d0000 0x0 0x1000>;
655 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
656 clock-names = "spiclk", "apb_pclk";
657 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
658 pinctrl-names = "default";
659 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
660 #address-cells = <1>;
666 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
667 reg = <0x0 0xff1e0000 0x0 0x1000>;
668 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
669 clock-names = "spiclk", "apb_pclk";
670 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
671 pinctrl-names = "default";
672 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
673 #address-cells = <1>;
679 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
680 reg = <0x0 0xff1f0000 0x0 0x1000>;
681 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
682 clock-names = "spiclk", "apb_pclk";
683 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
684 pinctrl-names = "default";
685 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
686 #address-cells = <1>;
692 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
693 reg = <0x0 0xff200000 0x0 0x1000>;
694 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
695 clock-names = "spiclk", "apb_pclk";
696 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
697 pinctrl-names = "default";
698 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
699 #address-cells = <1>;
706 polling-delay-passive = <100>; /* milliseconds */
707 polling-delay = <1000>; /* milliseconds */
709 thermal-sensors = <&tsadc 0>;
712 cpu_alert0: cpu_alert0 {
713 temperature = <70000>; /* millicelsius */
714 hysteresis = <2000>; /* millicelsius */
717 cpu_alert1: cpu_alert1 {
718 temperature = <75000>; /* millicelsius */
719 hysteresis = <2000>; /* millicelsius */
723 temperature = <95000>; /* millicelsius */
724 hysteresis = <2000>; /* millicelsius */
731 trip = <&cpu_alert0>;
733 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
736 trip = <&cpu_alert1>;
738 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
739 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
745 polling-delay-passive = <100>; /* milliseconds */
746 polling-delay = <1000>; /* milliseconds */
748 thermal-sensors = <&tsadc 1>;
751 gpu_alert0: gpu_alert0 {
752 temperature = <75000>; /* millicelsius */
753 hysteresis = <2000>; /* millicelsius */
757 temperature = <950000>; /* millicelsius */
758 hysteresis = <2000>; /* millicelsius */
765 trip = <&gpu_alert0>;
767 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
773 tsadc: tsadc@ff260000 {
774 compatible = "rockchip,rk3399-tsadc";
775 reg = <0x0 0xff260000 0x0 0x100>;
776 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
777 rockchip,grf = <&grf>;
778 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
779 clock-names = "tsadc", "apb_pclk";
780 assigned-clocks = <&cru SCLK_TSADC>;
781 assigned-clock-rates = <750000>;
782 resets = <&cru SRST_TSADC>;
783 reset-names = "tsadc-apb";
784 pinctrl-names = "init", "default", "sleep";
785 pinctrl-0 = <&otp_gpio>;
786 pinctrl-1 = <&otp_out>;
787 pinctrl-2 = <&otp_gpio>;
788 #thermal-sensor-cells = <1>;
789 rockchip,hw-tshut-temp = <95000>;
793 pmu: power-management@ff31000 {
794 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
795 reg = <0x0 0xff310000 0x0 0x1000>;
797 power: power-controller {
799 compatible = "rockchip,rk3399-power-controller";
800 #power-domain-cells = <1>;
801 #address-cells = <1>;
805 reg = <RK3399_PD_CENTER>;
806 #address-cells = <1>;
810 reg = <RK3399_PD_VDU>;
813 reg = <RK3399_PD_VCODEC>;
816 reg = <RK3399_PD_IEP>;
819 reg = <RK3399_PD_RGA>;
823 reg = <RK3399_PD_VIO>;
824 #address-cells = <1>;
828 reg = <RK3399_PD_ISP0>;
831 reg = <RK3399_PD_ISP1>;
834 reg = <RK3399_PD_HDCP>;
837 reg = <RK3399_PD_VO>;
838 #address-cells = <1>;
842 reg = <RK3399_PD_VOPB>;
845 reg = <RK3399_PD_VOPL>;
850 reg = <RK3399_PD_GPU>;
855 pmugrf: syscon@ff320000 {
856 compatible = "rockchip,rk3399-pmugrf", "syscon";
857 reg = <0x0 0xff320000 0x0 0x1000>;
861 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
862 reg = <0x0 0xff350000 0x0 0x1000>;
863 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
864 clock-names = "spiclk", "apb_pclk";
865 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
866 pinctrl-names = "default";
867 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
868 #address-cells = <1>;
873 uart4: serial@ff370000 {
874 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
875 reg = <0x0 0xff370000 0x0 0x100>;
876 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
877 clock-names = "baudclk", "apb_pclk";
878 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
881 pinctrl-names = "default";
882 pinctrl-0 = <&uart4_xfer>;
887 compatible = "rockchip,rk3399-i2c";
888 reg = <0x0 0xff3d0000 0x0 0x1000>;
889 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
890 clock-names = "i2c", "pclk";
891 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
892 pinctrl-names = "default";
893 pinctrl-0 = <&i2c4_xfer>;
894 #address-cells = <1>;
900 compatible = "rockchip,rk3399-i2c";
901 reg = <0x0 0xff3e0000 0x0 0x1000>;
902 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
903 clock-names = "i2c", "pclk";
904 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
905 pinctrl-names = "default";
906 pinctrl-0 = <&i2c8_xfer>;
907 #address-cells = <1>;
913 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
914 reg = <0x0 0xff420000 0x0 0x10>;
916 pinctrl-names = "default";
917 pinctrl-0 = <&pwm0_pin>;
918 clocks = <&pmucru PCLK_RKPWM_PMU>;
924 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
925 reg = <0x0 0xff420010 0x0 0x10>;
927 pinctrl-names = "default";
928 pinctrl-0 = <&pwm1_pin>;
929 clocks = <&pmucru PCLK_RKPWM_PMU>;
935 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
936 reg = <0x0 0xff420020 0x0 0x10>;
938 pinctrl-names = "default";
939 pinctrl-0 = <&pwm2_pin>;
940 clocks = <&pmucru PCLK_RKPWM_PMU>;
946 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
947 reg = <0x0 0xff420030 0x0 0x10>;
949 pinctrl-names = "default";
950 pinctrl-0 = <&pwm3a_pin>;
951 clocks = <&pmucru PCLK_RKPWM_PMU>;
957 compatible = "rockchip,rk3399-rga";
958 reg = <0x0 0xff680000 0x0 0x10000>;
959 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
960 interrupt-names = "rga";
961 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
962 clock-names = "aclk", "hclk", "sclk";
963 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
964 reset-names = "core", "axi", "ahb";
968 pmucru: pmu-clock-controller@ff750000 {
969 compatible = "rockchip,rk3399-pmucru";
970 reg = <0x0 0xff750000 0x0 0x1000>;
973 assigned-clocks = <&pmucru PLL_PPLL>;
974 assigned-clock-rates = <676000000>;
977 cru: clock-controller@ff760000 {
978 compatible = "rockchip,rk3399-cru";
979 reg = <0x0 0xff760000 0x0 0x1000>;
983 <&cru ACLK_VOP0>, <&cru HCLK_VOP0>,
984 <&cru ACLK_VOP1>, <&cru HCLK_VOP1>,
985 <&cru ARMCLKL>, <&cru ARMCLKB>,
986 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
988 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
990 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
992 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
993 assigned-clock-rates =
994 <400000000>, <200000000>,
995 <400000000>, <200000000>,
996 <816000000>, <1008000000>,
997 <594000000>, <800000000>,
999 <150000000>, <75000000>,
1001 <100000000>, <100000000>,
1003 <100000000>, <50000000>;
1006 grf: syscon@ff770000 {
1007 compatible = "rockchip,rk3399-grf", "syscon";
1008 reg = <0x0 0xff770000 0x0 0x10000>;
1011 wdt0: watchdog@ff840000 {
1012 compatible = "snps,dw-wdt";
1013 reg = <0x0 0xff840000 0x0 0x100>;
1014 clocks = <&cru PCLK_WDT>;
1015 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1016 status = "disabled";
1019 spdif: spdif@ff870000 {
1020 compatible = "rockchip,rk3399-spdif";
1021 reg = <0x0 0xff870000 0x0 0x1000>;
1022 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
1023 dmas = <&dmac_bus 7>;
1025 clock-names = "mclk", "hclk";
1026 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1027 pinctrl-names = "default";
1028 pinctrl-0 = <&spdif_bus>;
1029 status = "disabled";
1032 i2s0: i2s@ff880000 {
1033 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1034 reg = <0x0 0xff880000 0x0 0x1000>;
1035 rockchip,grf = <&grf>;
1036 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1037 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1038 dma-names = "tx", "rx";
1039 clock-names = "i2s_clk", "i2s_hclk";
1040 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1041 pinctrl-names = "default";
1042 pinctrl-0 = <&i2s0_8ch_bus>;
1043 status = "disabled";
1046 i2s1: i2s@ff890000 {
1047 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1048 reg = <0x0 0xff890000 0x0 0x1000>;
1049 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1050 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1051 dma-names = "tx", "rx";
1052 clock-names = "i2s_clk", "i2s_hclk";
1053 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1054 pinctrl-names = "default";
1055 pinctrl-0 = <&i2s1_2ch_bus>;
1056 status = "disabled";
1059 i2s2: i2s@ff8a0000 {
1060 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1061 reg = <0x0 0xff8a0000 0x0 0x1000>;
1062 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1063 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1064 dma-names = "tx", "rx";
1065 clock-names = "i2s_clk", "i2s_hclk";
1066 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1067 status = "disabled";
1071 compatible = "arm,malit860",
1076 reg = <0x0 0xff9a0000 0x0 0x10000>;
1078 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
1079 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
1080 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1081 interrupt-names = "GPU", "JOB", "MMU";
1083 clocks = <&cru ACLK_GPU>;
1084 clock-names = "clk_mali";
1085 #cooling-cells = <2>; /* min followed by max */
1086 operating-points-v2 = <&gpu_opp_table>;
1088 status = "disabled";
1091 compatible = "arm,mali-simple-power-model";
1094 static-power = <500>;
1095 dynamic-power = <1500>;
1096 ts = <20000 2000 (-20) 2>;
1097 thermal-zone = "gpu";
1101 gpu_opp_table: gpu_opp_table {
1102 compatible = "operating-points-v2";
1106 opp-hz = /bits/ 64 <200000000>;
1107 opp-microvolt = <900000>;
1110 opp-hz = /bits/ 64 <300000000>;
1111 opp-microvolt = <900000>;
1114 opp-hz = /bits/ 64 <400000000>;
1115 opp-microvolt = <900000>;
1120 vopl: vop@ff8f0000 {
1121 compatible = "rockchip,rk3399-vop-lit";
1122 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1123 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
1124 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1125 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1126 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1127 reset-names = "axi", "ahb", "dclk";
1128 iommus = <&vopl_mmu>;
1129 status = "disabled";
1132 #address-cells = <1>;
1135 vopl_out_mipi: endpoint@0 {
1137 remote-endpoint = <&mipi_in_vopl>;
1140 vopl_out_edp: endpoint@1 {
1142 remote-endpoint = <&edp_in_vopl>;
1147 vopl_mmu: iommu@ff8f3f00 {
1148 compatible = "rockchip,iommu";
1149 reg = <0x0 0xff8f3f00 0x0 0x100>;
1150 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
1151 interrupt-names = "vopl_mmu";
1153 status = "disabled";
1156 vopb: vop@ff900000 {
1157 compatible = "rockchip,rk3399-vop-big";
1158 reg = <0x0 0xff900000 0x0 0x3efc>;
1159 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1160 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1161 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1162 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1163 reset-names = "axi", "ahb", "dclk";
1164 iommus = <&vopb_mmu>;
1165 status = "disabled";
1168 #address-cells = <1>;
1171 vopb_out_edp: endpoint@0 {
1173 remote-endpoint = <&edp_in_vopb>;
1176 vopb_out_mipi: endpoint@1 {
1178 remote-endpoint = <&mipi_in_vopb>;
1183 vopb_mmu: iommu@ff903f00 {
1184 compatible = "rockchip,iommu";
1185 reg = <0x0 0xff903f00 0x0 0x100>;
1186 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1187 interrupt-names = "vopb_mmu";
1189 status = "disabled";
1192 mipi_dsi: mipi@ff960000 {
1193 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1194 reg = <0x0 0xff960000 0x0 0x8000>;
1195 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1196 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
1197 <&cru SCLK_DPHY_TX0_CFG>;
1198 clock-names = "ref", "pclk", "phy_cfg";
1199 rockchip,grf = <&grf>;
1200 #address-cells = <1>;
1202 status = "disabled";
1205 #address-cells = <1>;
1210 #address-cells = <1>;
1213 mipi_in_vopb: endpoint@0 {
1215 remote-endpoint = <&vopb_out_mipi>;
1217 mipi_in_vopl: endpoint@1 {
1219 remote-endpoint = <&vopl_out_mipi>;
1226 compatible = "rockchip,rk3399-edp";
1227 reg = <0x0 0xff970000 0x0 0x8000>;
1228 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1229 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1230 clock-names = "dp", "pclk";
1231 resets = <&cru SRST_P_EDP_CTRL>;
1233 rockchip,grf = <&grf>;
1234 status = "disabled";
1235 pinctrl-names = "default";
1236 pinctrl-0 = <&edp_hpd>;
1239 #address-cells = <1>;
1244 #address-cells = <1>;
1247 edp_in_vopb: endpoint@0 {
1249 remote-endpoint = <&vopb_out_edp>;
1252 edp_in_vopl: endpoint@1 {
1254 remote-endpoint = <&vopl_out_edp>;
1260 display_subsystem: display-subsystem {
1261 compatible = "rockchip,display-subsystem";
1262 ports = <&vopl_out>, <&vopb_out>;
1263 status = "disabled";
1267 compatible = "rockchip,rk3399-pinctrl";
1268 rockchip,grf = <&grf>;
1269 rockchip,pmu = <&pmugrf>;
1270 #address-cells = <0x2>;
1271 #size-cells = <0x2>;
1274 gpio0: gpio0@ff720000 {
1275 compatible = "rockchip,gpio-bank";
1276 reg = <0x0 0xff720000 0x0 0x100>;
1277 clocks = <&pmucru PCLK_GPIO0_PMU>;
1278 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1281 #gpio-cells = <0x2>;
1283 interrupt-controller;
1284 #interrupt-cells = <0x2>;
1287 gpio1: gpio1@ff730000 {
1288 compatible = "rockchip,gpio-bank";
1289 reg = <0x0 0xff730000 0x0 0x100>;
1290 clocks = <&pmucru PCLK_GPIO1_PMU>;
1291 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1294 #gpio-cells = <0x2>;
1296 interrupt-controller;
1297 #interrupt-cells = <0x2>;
1300 gpio2: gpio2@ff780000 {
1301 compatible = "rockchip,gpio-bank";
1302 reg = <0x0 0xff780000 0x0 0x100>;
1303 clocks = <&cru PCLK_GPIO2>;
1304 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1307 #gpio-cells = <0x2>;
1309 interrupt-controller;
1310 #interrupt-cells = <0x2>;
1313 gpio3: gpio3@ff788000 {
1314 compatible = "rockchip,gpio-bank";
1315 reg = <0x0 0xff788000 0x0 0x100>;
1316 clocks = <&cru PCLK_GPIO3>;
1317 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1320 #gpio-cells = <0x2>;
1322 interrupt-controller;
1323 #interrupt-cells = <0x2>;
1326 gpio4: gpio4@ff790000 {
1327 compatible = "rockchip,gpio-bank";
1328 reg = <0x0 0xff790000 0x0 0x100>;
1329 clocks = <&cru PCLK_GPIO4>;
1330 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1333 #gpio-cells = <0x2>;
1335 interrupt-controller;
1336 #interrupt-cells = <0x2>;
1339 pcfg_pull_up: pcfg-pull-up {
1343 pcfg_pull_down: pcfg-pull-down {
1347 pcfg_pull_none: pcfg-pull-none {
1351 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1353 drive-strength = <12>;
1356 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1358 drive-strength = <8>;
1361 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1363 drive-strength = <4>;
1366 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1368 drive-strength = <2>;
1371 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
1373 drive-strength = <12>;
1376 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
1378 drive-strength = <13>;
1382 emmc_pwr: emmc-pwr {
1384 <0 5 RK_FUNC_1 &pcfg_pull_up>;
1389 rgmii_pins: rgmii-pins {
1392 <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
1394 <3 14 RK_FUNC_1 &pcfg_pull_none>,
1396 <3 13 RK_FUNC_1 &pcfg_pull_none>,
1398 <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1400 <3 11 RK_FUNC_1 &pcfg_pull_none>,
1402 <3 9 RK_FUNC_1 &pcfg_pull_none>,
1404 <3 8 RK_FUNC_1 &pcfg_pull_none>,
1406 <3 7 RK_FUNC_1 &pcfg_pull_none>,
1408 <3 6 RK_FUNC_1 &pcfg_pull_none>,
1410 <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1412 <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
1414 <3 3 RK_FUNC_1 &pcfg_pull_none>,
1416 <3 2 RK_FUNC_1 &pcfg_pull_none>,
1418 <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
1420 <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
1423 rmii_pins: rmii-pins {
1426 <3 13 RK_FUNC_1 &pcfg_pull_none>,
1428 <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1430 <3 11 RK_FUNC_1 &pcfg_pull_none>,
1432 <3 10 RK_FUNC_1 &pcfg_pull_none>,
1434 <3 9 RK_FUNC_1 &pcfg_pull_none>,
1436 <3 8 RK_FUNC_1 &pcfg_pull_none>,
1438 <3 7 RK_FUNC_1 &pcfg_pull_none>,
1440 <3 6 RK_FUNC_1 &pcfg_pull_none>,
1442 <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1444 <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
1449 i2c0_xfer: i2c0-xfer {
1451 <1 15 RK_FUNC_2 &pcfg_pull_none>,
1452 <1 16 RK_FUNC_2 &pcfg_pull_none>;
1457 i2c1_xfer: i2c1-xfer {
1459 <4 2 RK_FUNC_1 &pcfg_pull_none>,
1460 <4 1 RK_FUNC_1 &pcfg_pull_none>;
1465 i2c2_xfer: i2c2-xfer {
1467 <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1468 <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
1473 i2c3_xfer: i2c3-xfer {
1475 <4 17 RK_FUNC_1 &pcfg_pull_none>,
1476 <4 16 RK_FUNC_1 &pcfg_pull_none>;
1481 i2c4_xfer: i2c4-xfer {
1483 <1 12 RK_FUNC_1 &pcfg_pull_none>,
1484 <1 11 RK_FUNC_1 &pcfg_pull_none>;
1489 i2c5_xfer: i2c5-xfer {
1491 <3 11 RK_FUNC_2 &pcfg_pull_none>,
1492 <3 10 RK_FUNC_2 &pcfg_pull_none>;
1497 i2c6_xfer: i2c6-xfer {
1499 <2 10 RK_FUNC_2 &pcfg_pull_none>,
1500 <2 9 RK_FUNC_2 &pcfg_pull_none>;
1505 i2c7_xfer: i2c7-xfer {
1507 <2 8 RK_FUNC_2 &pcfg_pull_none>,
1508 <2 7 RK_FUNC_2 &pcfg_pull_none>;
1513 i2c8_xfer: i2c8-xfer {
1515 <1 21 RK_FUNC_1 &pcfg_pull_none>,
1516 <1 20 RK_FUNC_1 &pcfg_pull_none>;
1521 i2s0_8ch_bus: i2s0-8ch-bus {
1523 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1524 <3 25 RK_FUNC_1 &pcfg_pull_none>,
1525 <3 26 RK_FUNC_1 &pcfg_pull_none>,
1526 <3 27 RK_FUNC_1 &pcfg_pull_none>,
1527 <3 28 RK_FUNC_1 &pcfg_pull_none>,
1528 <3 29 RK_FUNC_1 &pcfg_pull_none>,
1529 <3 30 RK_FUNC_1 &pcfg_pull_none>,
1530 <3 31 RK_FUNC_1 &pcfg_pull_none>,
1531 <4 0 RK_FUNC_1 &pcfg_pull_none>;
1536 i2s1_2ch_bus: i2s1-2ch-bus {
1538 <4 3 RK_FUNC_1 &pcfg_pull_none>,
1539 <4 4 RK_FUNC_1 &pcfg_pull_none>,
1540 <4 5 RK_FUNC_1 &pcfg_pull_none>,
1541 <4 6 RK_FUNC_1 &pcfg_pull_none>,
1542 <4 7 RK_FUNC_1 &pcfg_pull_none>;
1547 sdio0_bus1: sdio0-bus1 {
1549 <2 20 RK_FUNC_1 &pcfg_pull_up>;
1552 sdio0_bus4: sdio0-bus4 {
1554 <2 20 RK_FUNC_1 &pcfg_pull_up>,
1555 <2 21 RK_FUNC_1 &pcfg_pull_up>,
1556 <2 22 RK_FUNC_1 &pcfg_pull_up>,
1557 <2 23 RK_FUNC_1 &pcfg_pull_up>;
1560 sdio0_cmd: sdio0-cmd {
1562 <2 24 RK_FUNC_1 &pcfg_pull_up>;
1565 sdio0_clk: sdio0-clk {
1567 <2 25 RK_FUNC_1 &pcfg_pull_none>;
1570 sdio0_cd: sdio0-cd {
1572 <2 26 RK_FUNC_1 &pcfg_pull_up>;
1575 sdio0_pwr: sdio0-pwr {
1577 <2 27 RK_FUNC_1 &pcfg_pull_up>;
1580 sdio0_bkpwr: sdio0-bkpwr {
1582 <2 28 RK_FUNC_1 &pcfg_pull_up>;
1585 sdio0_wp: sdio0-wp {
1587 <0 3 RK_FUNC_1 &pcfg_pull_up>;
1590 sdio0_int: sdio0-int {
1592 <0 4 RK_FUNC_1 &pcfg_pull_up>;
1597 sdmmc_bus1: sdmmc-bus1 {
1599 <4 8 RK_FUNC_1 &pcfg_pull_up>;
1602 sdmmc_bus4: sdmmc-bus4 {
1604 <4 8 RK_FUNC_1 &pcfg_pull_up>,
1605 <4 9 RK_FUNC_1 &pcfg_pull_up>,
1606 <4 10 RK_FUNC_1 &pcfg_pull_up>,
1607 <4 11 RK_FUNC_1 &pcfg_pull_up>;
1610 sdmmc_clk: sdmmc-clk {
1612 <4 12 RK_FUNC_1 &pcfg_pull_none>;
1615 sdmmc_cmd: sdmmc-cmd {
1617 <4 13 RK_FUNC_1 &pcfg_pull_up>;
1620 sdmmc_cd: sdmcc-cd {
1622 <0 7 RK_FUNC_1 &pcfg_pull_up>;
1625 sdmmc_wp: sdmmc-wp {
1627 <0 8 RK_FUNC_1 &pcfg_pull_up>;
1632 spdif_bus: spdif-bus {
1634 <4 21 RK_FUNC_1 &pcfg_pull_none>;
1639 spi0_clk: spi0-clk {
1641 <3 6 RK_FUNC_2 &pcfg_pull_up>;
1643 spi0_cs0: spi0-cs0 {
1645 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1647 spi0_cs1: spi0-cs1 {
1649 <3 8 RK_FUNC_2 &pcfg_pull_up>;
1653 <3 5 RK_FUNC_2 &pcfg_pull_up>;
1657 <3 4 RK_FUNC_2 &pcfg_pull_up>;
1662 spi1_clk: spi1-clk {
1664 <1 9 RK_FUNC_2 &pcfg_pull_up>;
1666 spi1_cs0: spi1-cs0 {
1668 <1 10 RK_FUNC_2 &pcfg_pull_up>;
1672 <1 7 RK_FUNC_2 &pcfg_pull_up>;
1676 <1 8 RK_FUNC_2 &pcfg_pull_up>;
1681 spi2_clk: spi2-clk {
1683 <2 11 RK_FUNC_1 &pcfg_pull_up>;
1685 spi2_cs0: spi2-cs0 {
1687 <2 12 RK_FUNC_1 &pcfg_pull_up>;
1691 <2 9 RK_FUNC_1 &pcfg_pull_up>;
1695 <2 10 RK_FUNC_1 &pcfg_pull_up>;
1700 spi3_clk: spi3-clk {
1702 <1 17 RK_FUNC_1 &pcfg_pull_up>;
1704 spi3_cs0: spi3-cs0 {
1706 <1 18 RK_FUNC_1 &pcfg_pull_up>;
1710 <1 15 RK_FUNC_1 &pcfg_pull_up>;
1714 <1 16 RK_FUNC_1 &pcfg_pull_up>;
1719 spi4_clk: spi4-clk {
1721 <3 2 RK_FUNC_2 &pcfg_pull_up>;
1723 spi4_cs0: spi4-cs0 {
1725 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1729 <3 0 RK_FUNC_2 &pcfg_pull_up>;
1733 <3 1 RK_FUNC_2 &pcfg_pull_up>;
1738 spi5_clk: spi5-clk {
1740 <2 22 RK_FUNC_2 &pcfg_pull_up>;
1742 spi5_cs0: spi5-cs0 {
1744 <2 23 RK_FUNC_2 &pcfg_pull_up>;
1748 <2 20 RK_FUNC_2 &pcfg_pull_up>;
1752 <2 21 RK_FUNC_2 &pcfg_pull_up>;
1757 otp_gpio: otp-gpio {
1758 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
1762 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
1767 uart0_xfer: uart0-xfer {
1769 <2 16 RK_FUNC_1 &pcfg_pull_up>,
1770 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1773 uart0_cts: uart0-cts {
1775 <2 18 RK_FUNC_1 &pcfg_pull_none>;
1778 uart0_rts: uart0-rts {
1780 <2 19 RK_FUNC_1 &pcfg_pull_none>;
1785 uart1_xfer: uart1-xfer {
1787 <3 12 RK_FUNC_2 &pcfg_pull_up>,
1788 <3 13 RK_FUNC_2 &pcfg_pull_none>;
1793 uart2a_xfer: uart2a-xfer {
1795 <4 8 RK_FUNC_2 &pcfg_pull_up>,
1796 <4 9 RK_FUNC_2 &pcfg_pull_none>;
1801 uart2b_xfer: uart2b-xfer {
1803 <4 16 RK_FUNC_2 &pcfg_pull_up>,
1804 <4 17 RK_FUNC_2 &pcfg_pull_none>;
1809 uart2c_xfer: uart2c-xfer {
1811 <4 19 RK_FUNC_1 &pcfg_pull_up>,
1812 <4 20 RK_FUNC_1 &pcfg_pull_none>;
1817 uart3_xfer: uart3-xfer {
1819 <3 14 RK_FUNC_2 &pcfg_pull_up>,
1820 <3 15 RK_FUNC_2 &pcfg_pull_none>;
1823 uart3_cts: uart3-cts {
1825 <3 18 RK_FUNC_2 &pcfg_pull_none>;
1828 uart3_rts: uart3-rts {
1830 <3 19 RK_FUNC_2 &pcfg_pull_none>;
1835 uart4_xfer: uart4-xfer {
1837 <1 7 RK_FUNC_1 &pcfg_pull_up>,
1838 <1 8 RK_FUNC_1 &pcfg_pull_none>;
1843 uarthdcp_xfer: uarthdcp-xfer {
1845 <4 21 RK_FUNC_2 &pcfg_pull_up>,
1846 <4 22 RK_FUNC_2 &pcfg_pull_none>;
1851 pwm0_pin: pwm0-pin {
1853 <4 18 RK_FUNC_1 &pcfg_pull_none>;
1856 vop0_pwm_pin: vop0-pwm-pin {
1858 <4 18 RK_FUNC_2 &pcfg_pull_none>;
1863 pwm1_pin: pwm1-pin {
1865 <4 22 RK_FUNC_1 &pcfg_pull_none>;
1868 vop1_pwm_pin: vop1-pwm-pin {
1870 <4 18 RK_FUNC_3 &pcfg_pull_none>;
1875 pwm2_pin: pwm2-pin {
1877 <1 19 RK_FUNC_1 &pcfg_pull_none>;
1882 pwm3a_pin: pwm3a-pin {
1884 <0 6 RK_FUNC_1 &pcfg_pull_none>;
1889 pwm3b_pin: pwm3b-pin {
1891 <1 14 RK_FUNC_1 &pcfg_pull_none>;
1898 <4 23 RK_FUNC_2 &pcfg_pull_none>;