arch/arm64/boot/dts/rockchip/rk3399.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3399-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/interrupt-controller/irq.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/power/rk3399-power.h>
  49 #include <dt-bindings/thermal/thermal.h>
  50
  51 / {
  52         compatible = "rockchip,rk3399";
  53         interrupt-parent = <&gic>;
  54         #address-cells = <2>;
  55         #size-cells = <2>;
  56
  57         aliases {
  58                 i2c0 = &i2c0;
  59                 i2c1 = &i2c1;
  60                 i2c2 = &i2c2;
  61                 i2c3 = &i2c3;
  62                 i2c4 = &i2c4;
  63                 i2c5 = &i2c5;
  64                 i2c6 = &i2c6;
  65                 i2c7 = &i2c7;
  66                 i2c8 = &i2c8;
  67                 serial0 = &uart0;
  68                 serial1 = &uart1;
  69                 serial2 = &uart2;
  70                 serial3 = &uart3;
  71                 serial4 = &uart4;
  72         };
  73
  74         psci {
  75                 compatible = "arm,psci-1.0";
  76                 method = "smc";
  77         };
  78
  79         cpus {
  80                 #address-cells = <2>;
  81                 #size-cells = <0>;
  82
  83                 cpu-map {
  84                         cluster0 {
  85                                 core0 {
  86                                         cpu = <&cpu_l0>;
  87                                 };
  88                                 core1 {
  89                                         cpu = <&cpu_l1>;
  90                                 };
  91                                 core2 {
  92                                         cpu = <&cpu_l2>;
  93                                 };
  94                                 core3 {
  95                                         cpu = <&cpu_l3>;
  96                                 };
  97                         };
  98
  99                         cluster1 {
 100                                 core0 {
 101                                         cpu = <&cpu_b0>;
 102                                 };
 103                                 core1 {
 104                                         cpu = <&cpu_b1>;
 105                                 };
 106                         };
 107                 };
 108
 109                 cpu_l0: cpu@0 {
 110                         device_type = "cpu";
 111                         compatible = "arm,cortex-a53", "arm,armv8";
 112                         reg = <0x0 0x0>;
 113                         enable-method = "psci";
 114                         #cooling-cells = <2>; /* min followed by max */
 115                         clocks = <&cru ARMCLKL>;
 116                         cpu-idle-states = <&cpu_sleep>;
 117                         operating-points-v2 = <&cluster0_opp>;
 118                 };
 119
 120                 cpu_l1: cpu@1 {
 121                         device_type = "cpu";
 122                         compatible = "arm,cortex-a53", "arm,armv8";
 123                         reg = <0x0 0x1>;
 124                         enable-method = "psci";
 125                         clocks = <&cru ARMCLKL>;
 126                         cpu-idle-states = <&cpu_sleep>;
 127                         operating-points-v2 = <&cluster0_opp>;
 128                 };
 129
 130                 cpu_l2: cpu@2 {
 131                         device_type = "cpu";
 132                         compatible = "arm,cortex-a53", "arm,armv8";
 133                         reg = <0x0 0x2>;
 134                         enable-method = "psci";
 135                         clocks = <&cru ARMCLKL>;
 136                         cpu-idle-states = <&cpu_sleep>;
 137                         operating-points-v2 = <&cluster0_opp>;
 138                 };
 139
 140                 cpu_l3: cpu@3 {
 141                         device_type = "cpu";
 142                         compatible = "arm,cortex-a53", "arm,armv8";
 143                         reg = <0x0 0x3>;
 144                         enable-method = "psci";
 145                         clocks = <&cru ARMCLKL>;
 146                         cpu-idle-states = <&cpu_sleep>;
 147                         operating-points-v2 = <&cluster0_opp>;
 148                 };
 149
 150                 cpu_b0: cpu@100 {
 151                         device_type = "cpu";
 152                         compatible = "arm,cortex-a72", "arm,armv8";
 153                         reg = <0x0 0x100>;
 154                         enable-method = "psci";
 155                         #cooling-cells = <2>; /* min followed by max */
 156                         clocks = <&cru ARMCLKB>;
 157                         cpu-idle-states = <&cpu_sleep>;
 158                         operating-points-v2 = <&cluster1_opp>;
 159                 };
 160
 161                 cpu_b1: cpu@101 {
 162                         device_type = "cpu";
 163                         compatible = "arm,cortex-a72", "arm,armv8";
 164                         reg = <0x0 0x101>;
 165                         enable-method = "psci";
 166                         clocks = <&cru ARMCLKB>;
 167                         cpu-idle-states = <&cpu_sleep>;
 168                         operating-points-v2 = <&cluster1_opp>;
 169                 };
 170
 171                 idle-states {
 172                         entry-method = "psci";
 173                         cpu_sleep: cpu-sleep-0 {
 174                                 compatible = "arm,idle-state";
 175                                 local-timer-stop;
 176                                 arm,psci-suspend-param = <0x0010000>;
 177                                 entry-latency-us = <350>;
 178                                 exit-latency-us = <600>;
 179                                 min-residency-us = <1150>;
 180                         };
 181                 };
 182         };
 183
 184         cluster0_opp: opp_table0 {
 185                 compatible = "operating-points-v2";
 186                 opp-shared;
 187
 188                 opp00 {
 189                         opp-hz = /bits/ 64 <408000000>;
 190                         opp-microvolt = <800000>;
 191                         clock-latency-ns = <40000>;
 192                 };
 193                 opp01 {
 194                         opp-hz = /bits/ 64 <600000000>;
 195                         opp-microvolt = <800000>;
 196                 };
 197                 opp02 {
 198                         opp-hz = /bits/ 64 <816000000>;
 199                         opp-microvolt = <800000>;
 200                 };
 201                 opp03 {
 202                         opp-hz = /bits/ 64 <1008000000>;
 203                         opp-microvolt = <875000>;
 204                 };
 205                 opp04 {
 206                         opp-hz = /bits/ 64 <1200000000>;
 207                         opp-microvolt = <925000>;
 208                 };
 209                 opp05 {
 210                         opp-hz = /bits/ 64 <1416000000>;
 211                         opp-microvolt = <1025000>;
 212                 };
 213         };
 214
 215         cluster1_opp: opp_table1 {
 216                 compatible = "operating-points-v2";
 217                 opp-shared;
 218
 219                 opp00 {
 220                         opp-hz = /bits/ 64 <408000000>;
 221                         opp-microvolt = <800000>;
 222                         clock-latency-ns = <40000>;
 223                 };
 224                 opp01 {
 225                         opp-hz = /bits/ 64 <600000000>;
 226                         opp-microvolt = <800000>;
 227                 };
 228                 opp02 {
 229                         opp-hz = /bits/ 64 <816000000>;
 230                         opp-microvolt = <800000>;
 231                 };
 232                 opp03 {
 233                         opp-hz = /bits/ 64 <1008000000>;
 234                         opp-microvolt = <850000>;
 235                 };
 236                 opp04 {
 237                         opp-hz = /bits/ 64 <1200000000>;
 238                         opp-microvolt = <925000>;
 239                 };
 240         };
 241
 242         timer {
 243                 compatible = "arm,armv8-timer";
 244                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
 245                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
 246                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
 247                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
 248         };
 249
 250         arm-pmu {
 251                 compatible = "arm,armv8-pmuv3";
 252                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
 253         };
 254
 255         xin24m: xin24m {
 256                 compatible = "fixed-clock";
 257                 #clock-cells = <0>;
 258                 clock-frequency = <24000000>;
 259                 clock-output-names = "xin24m";
 260         };
 261
 262         amba {
 263                 compatible = "arm,amba-bus";
 264                 #address-cells = <2>;
 265                 #size-cells = <2>;
 266                 ranges;
 267
 268                 dmac_bus: dma-controller@ff6d0000 {
 269                         compatible = "arm,pl330", "arm,primecell";
 270                         reg = <0x0 0xff6d0000 0x0 0x4000>;
 271                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 272                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 273                         #dma-cells = <1>;
 274                         clocks = <&cru ACLK_DMAC0_PERILP>;
 275                         clock-names = "apb_pclk";
 276                 };
 277
 278                 dmac_peri: dma-controller@ff6e0000 {
 279                         compatible = "arm,pl330", "arm,primecell";
 280                         reg = <0x0 0xff6e0000 0x0 0x4000>;
 281                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 282                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 283                         #dma-cells = <1>;
 284                         clocks = <&cru ACLK_DMAC1_PERILP>;
 285                         clock-names = "apb_pclk";
 286                 };
 287         };
 288
 289         gmac: eth@fe300000 {
 290                 compatible = "rockchip,rk3399-gmac";
 291                 reg = <0x0 0xfe300000 0x0 0x10000>;
 292                 rockchip,grf = <&grf>;
 293                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 294                 interrupt-names = "macirq";
 295                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
 296                          <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
 297                          <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
 298                          <&cru PCLK_GMAC>;
 299                 clock-names = "stmmaceth", "mac_clk_rx",
 300                               "mac_clk_tx", "clk_mac_ref",
 301                               "clk_mac_refout", "aclk_mac",
 302                               "pclk_mac";
 303                 resets = <&cru SRST_A_GMAC>;
 304                 reset-names = "stmmaceth";
 305                 status = "disabled";
 306         };
 307
 308         emmc_phy: phy {
 309                 compatible = "rockchip,rk3399-emmc-phy";
 310                 reg-offset = <0xf780>;
 311                 #phy-cells = <0>;
 312                 rockchip,grf = <&grf>;
 313                 status = "disabled";
 314         };
 315
 316         sdio0: dwmmc@fe310000 {
 317                 compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc";
 318                 reg = <0x0 0xfe310000 0x0 0x4000>;
 319                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 320                 clock-freq-min-max = <400000 150000000>;
 321                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 322                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 323                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 324                 fifo-depth = <0x100>;
 325                 status = "disabled";
 326         };
 327
 328         sdmmc: dwmmc@fe320000 {
 329                 compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc";
 330                 reg = <0x0 0xfe320000 0x0 0x4000>;
 331                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 332                 clock-freq-min-max = <400000 150000000>;
 333                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 334                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 335                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 336                 fifo-depth = <0x100>;
 337                 status = "disabled";
 338         };
 339
 340         sdhci: sdhci@fe330000 {
 341                 compatible = "arasan,sdhci-5.1";
 342                 reg = <0x0 0xfe330000 0x0 0x10000>;
 343                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 344                 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
 345                 clock-names = "clk_xin", "clk_ahb";
 346                 assigned-clocks = <&cru SCLK_EMMC>;
 347                 assigned-clock-parents = <&cru PLL_CPLL>;
 348                 assigned-clock-rates = <200000000>;
 349                 phys = <&emmc_phy>;
 350                 phy-names = "phy_arasan";
 351                 status = "disabled";
 352         };
 353
 354         usb2phy: usb2phy {
 355                 compatible = "rockchip,rk3399-usb-phy";
 356                 rockchip,grf = <&grf>;
 357                 #address-cells = <1>;
 358                 #size-cells = <0>;
 359
 360                 usb2phy0: usb2-phy0 {
 361                         #phy-cells = <0>;
 362                         #clock-cells = <0>;
 363                         reg = <0xe458>;
 364                 };
 365
 366                 usb2phy1: usb2-phy1 {
 367                         #phy-cells = <0>;
 368                         #clock-cells = <0>;
 369                         reg = <0xe468>;
 370                 };
 371         };
 372
 373         usb_host0_echi: usb@fe380000 {
 374                 compatible = "generic-ehci";
 375                 reg = <0x0 0xfe380000 0x0 0x20000>;
 376                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 377                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
 378                 clock-names = "hclk_host0", "hclk_host0_arb";
 379                 phys = <&usb2phy0>;
 380                 phy-names = "usb2_phy0";
 381                 status = "disabled";
 382         };
 383
 384         usb_host0_ohci: usb@fe3a0000 {
 385                 compatible = "generic-ohci";
 386                 reg = <0x0 0xfe3a0000 0x0 0x20000>;
 387                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 388                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
 389                 clock-names = "hclk_host0", "hclk_host0_arb";
 390                 status = "disabled";
 391         };
 392
 393         usb_host1_echi: usb@fe3c0000 {
 394                 compatible = "generic-ehci";
 395                 reg = <0x0 0xfe3c0000 0x0 0x20000>;
 396                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 397                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
 398                 clock-names = "hclk_host1", "hclk_host1_arb";
 399                 phys = <&usb2phy1>;
 400                 phy-names = "usb2_phy1";
 401                 status = "disabled";
 402         };
 403
 404         usb_host1_ohci: usb@fe3e0000 {
 405                 compatible = "generic-ohci";
 406                 reg = <0x0 0xfe3e0000 0x0 0x20000>;
 407                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 408                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
 409                 clock-names = "hclk_host1", "hclk_host1_arb";
 410                 status = "disabled";
 411         };
 412
 413         usbdrd3_0: usb@fe800000 {
 414                 compatible = "rockchip,dwc3";
 415                 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
 416                          <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
 417                          <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
 418                 clock-names = "clk_usb3otg0_ref", "clk_usb3otg0_suspend",
 419                               "aclk_usb3otg0", "aclk_usb3_rksoc_axi_perf",
 420                               "aclk_usb3", "aclk_usb3_grf";
 421                 #address-cells = <2>;
 422                 #size-cells = <2>;
 423                 ranges;
 424                 status = "disabled";
 425                 usbdrd_dwc3_0: dwc3 {
 426                         compatible = "snps,dwc3";
 427                         reg = <0x0 0xfe800000 0x0 0x100000>;
 428                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 429                         dr_mode = "otg";
 430                         tx-fifo-resize;
 431                         snps,dis_enblslpm_quirk;
 432                         snps,phyif_utmi_16_bits;
 433                         snps,dis_u2_freeclk_exists_quirk;
 434                         snps,dis_del_phy_power_chg_quirk;
 435                         status = "disabled";
 436                 };
 437         };
 438
 439         usbdrd3_1: usb@fe900000 {
 440                 compatible = "rockchip,dwc3";
 441                 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
 442                          <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
 443                          <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
 444                 clock-names = "clk_usb3otg1_ref", "clk_usb3otg1_suspend",
 445                               "aclk_usb3otg1", "aclk_usb3_rksoc_axi_perf",
 446                               "aclk_usb3", "aclk_usb3_grf";
 447                 #address-cells = <2>;
 448                 #size-cells = <2>;
 449                 ranges;
 450                 status = "disabled";
 451                 usbdrd_dwc3_1: dwc3 {
 452                         compatible = "snps,dwc3";
 453                         reg = <0x0 0xfe900000 0x0 0x100000>;
 454                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 455                         dr_mode = "otg";
 456                         tx-fifo-resize;
 457                         snps,dis_enblslpm_quirk;
 458                         snps,phyif_utmi_16_bits;
 459                         snps,dis_u2_freeclk_exists_quirk;
 460                         snps,dis_del_phy_power_chg_quirk;
 461                         status = "disabled";
 462                 };
 463         };
 464
 465         gic: interrupt-controller@fee00000 {
 466                 compatible = "arm,gic-v3";
 467                 #interrupt-cells = <3>;
 468                 #address-cells = <2>;
 469                 #size-cells = <2>;
 470                 ranges;
 471                 interrupt-controller;
 472
 473                 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
 474                       <0x0 0xfef00000 0 0xc0000>, /* GICR */
 475                       <0x0 0xfff00000 0 0x10000>, /* GICC */
 476                       <0x0 0xfff10000 0 0x10000>, /* GICH */
 477                       <0x0 0xfff20000 0 0x10000>; /* GICV */
 478                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 479                 its: interrupt-controller@fee20000 {
 480                         compatible = "arm,gic-v3-its";
 481                         msi-controller;
 482                         reg = <0x0 0xfee20000 0x0 0x20000>;
 483                 };
 484         };
 485
 486         saradc: saradc@ff100000 {
 487                 compatible = "rockchip,rk3399-saradc";
 488                 reg = <0x0 0xff100000 0x0 0x100>;
 489                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 490                 #io-channel-cells = <1>;
 491                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 492                 clock-names = "saradc", "apb_pclk";
 493                 status = "disabled";
 494         };
 495
 496         i2c0: i2c@ff3c0000 {
 497                 compatible = "rockchip,rk3399-i2c";
 498                 reg = <0x0 0xff3c0000 0x0 0x1000>;
 499                 clocks =  <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
 500                 clock-names = "i2c", "pclk";
 501                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 502                 pinctrl-names = "default";
 503                 pinctrl-0 = <&i2c0_xfer>;
 504                 #address-cells = <1>;
 505                 #size-cells = <0>;
 506                 status = "disabled";
 507         };
 508
 509         i2c1: i2c@ff110000 {
 510                 compatible = "rockchip,rk3399-i2c";
 511                 reg = <0x0 0xff110000 0x0 0x1000>;
 512                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 513                 clock-names = "i2c", "pclk";
 514                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 515                 pinctrl-names = "default";
 516                 pinctrl-0 = <&i2c1_xfer>;
 517                 #address-cells = <1>;
 518                 #size-cells = <0>;
 519                 status = "disabled";
 520         };
 521
 522         i2c2: i2c@ff120000 {
 523                 compatible = "rockchip,rk3399-i2c";
 524                 reg = <0x0 0xff120000 0x0 0x1000>;
 525                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 526                 clock-names = "i2c", "pclk";
 527                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 528                 pinctrl-names = "default";
 529                 pinctrl-0 = <&i2c2_xfer>;
 530                 #address-cells = <1>;
 531                 #size-cells = <0>;
 532                 status = "disabled";
 533         };
 534
 535         i2c3: i2c@ff130000 {
 536                 compatible = "rockchip,rk3399-i2c";
 537                 reg = <0x0 0xff130000 0x0 0x1000>;
 538                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 539                 clock-names = "i2c", "pclk";
 540                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 541                 pinctrl-names = "default";
 542                 pinctrl-0 = <&i2c3_xfer>;
 543                 #address-cells = <1>;
 544                 #size-cells = <0>;
 545                 status = "disabled";
 546         };
 547
 548         i2c5: i2c@ff140000 {
 549                 compatible = "rockchip,rk3399-i2c";
 550                 reg = <0x0 0xff140000 0x0 0x1000>;
 551                 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
 552                 clock-names = "i2c", "pclk";
 553                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 554                 pinctrl-names = "default";
 555                 pinctrl-0 = <&i2c5_xfer>;
 556                 #address-cells = <1>;
 557                 #size-cells = <0>;
 558                 status = "disabled";
 559         };
 560
 561         i2c6: i2c@ff150000 {
 562                 compatible = "rockchip,rk3399-i2c";
 563                 reg = <0x0 0xff150000 0x0 0x1000>;
 564                 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
 565                 clock-names = "i2c", "pclk";
 566                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 567                 pinctrl-names = "default";
 568                 pinctrl-0 = <&i2c6_xfer>;
 569                 #address-cells = <1>;
 570                 #size-cells = <0>;
 571                 status = "disabled";
 572         };
 573
 574         i2c7: i2c@ff160000 {
 575                 compatible = "rockchip,rk3399-i2c";
 576                 reg = <0x0 0xff160000 0x0 0x1000>;
 577                 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
 578                 clock-names = "i2c", "pclk";
 579                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 580                 pinctrl-names = "default";
 581                 pinctrl-0 = <&i2c7_xfer>;
 582                 #address-cells = <1>;
 583                 #size-cells = <0>;
 584                 status = "disabled";
 585         };
 586
 587         uart0: serial@ff180000 {
 588                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 589                 reg = <0x0 0xff180000 0x0 0x100>;
 590                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 591                 clock-names = "baudclk", "apb_pclk";
 592                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 593                 reg-shift = <2>;
 594                 reg-io-width = <4>;
 595                 pinctrl-names = "default";
 596                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 597                 status = "disabled";
 598         };
 599
 600         uart1: serial@ff190000 {
 601                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 602                 reg = <0x0 0xff190000 0x0 0x100>;
 603                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 604                 clock-names = "baudclk", "apb_pclk";
 605                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 606                 reg-shift = <2>;
 607                 reg-io-width = <4>;
 608                 pinctrl-names = "default";
 609                 pinctrl-0 = <&uart1_xfer>;
 610                 status = "disabled";
 611         };
 612
 613         uart2: serial@ff1a0000 {
 614                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 615                 reg = <0x0 0xff1a0000 0x0 0x100>;
 616                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 617                 clock-names = "baudclk", "apb_pclk";
 618                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 619                 reg-shift = <2>;
 620                 reg-io-width = <4>;
 621                 pinctrl-names = "default";
 622                 pinctrl-0 = <&uart2c_xfer>;
 623                 status = "disabled";
 624         };
 625
 626         uart3: serial@ff1b0000 {
 627                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 628                 reg = <0x0 0xff1b0000 0x0 0x100>;
 629                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 630                 clock-names = "baudclk", "apb_pclk";
 631                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 632                 reg-shift = <2>;
 633                 reg-io-width = <4>;
 634                 pinctrl-names = "default";
 635                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 636                 status = "disabled";
 637         };
 638
 639         spi0: spi@ff1c0000 {
 640                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 641                 reg = <0x0 0xff1c0000 0x0 0x1000>;
 642                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 643                 clock-names = "spiclk", "apb_pclk";
 644                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 645                 pinctrl-names = "default";
 646                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 647                 #address-cells = <1>;
 648                 #size-cells = <0>;
 649                 status = "disabled";
 650         };
 651
 652         spi1: spi@ff1d0000 {
 653                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 654                 reg = <0x0 0xff1d0000 0x0 0x1000>;
 655                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 656                 clock-names = "spiclk", "apb_pclk";
 657                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 658                 pinctrl-names = "default";
 659                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 660                 #address-cells = <1>;
 661                 #size-cells = <0>;
 662                 status = "disabled";
 663         };
 664
 665         spi2: spi@ff1e0000 {
 666                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 667                 reg = <0x0 0xff1e0000 0x0 0x1000>;
 668                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 669                 clock-names = "spiclk", "apb_pclk";
 670                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 671                 pinctrl-names = "default";
 672                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 673                 #address-cells = <1>;
 674                 #size-cells = <0>;
 675                 status = "disabled";
 676         };
 677
 678         spi4: spi@ff1f0000 {
 679                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 680                 reg = <0x0 0xff1f0000 0x0 0x1000>;
 681                 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
 682                 clock-names = "spiclk", "apb_pclk";
 683                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 684                 pinctrl-names = "default";
 685                 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
 686                 #address-cells = <1>;
 687                 #size-cells = <0>;
 688                 status = "disabled";
 689         };
 690
 691         spi5: spi@ff200000 {
 692                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 693                 reg = <0x0 0xff200000 0x0 0x1000>;
 694                 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
 695                 clock-names = "spiclk", "apb_pclk";
 696                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
 697                 pinctrl-names = "default";
 698                 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
 699                 #address-cells = <1>;
 700                 #size-cells = <0>;
 701                 status = "disabled";
 702         };
 703
 704         thermal-zones {
 705                 cpu {
 706                         polling-delay-passive = <100>; /* milliseconds */
 707                         polling-delay = <1000>; /* milliseconds */
 708
 709                         thermal-sensors = <&tsadc 0>;
 710
 711                         trips {
 712                                 cpu_alert0: cpu_alert0 {
 713                                         temperature = <70000>; /* millicelsius */
 714                                         hysteresis = <2000>; /* millicelsius */
 715                                         type = "passive";
 716                                 };
 717                                 cpu_alert1: cpu_alert1 {
 718                                         temperature = <75000>; /* millicelsius */
 719                                         hysteresis = <2000>; /* millicelsius */
 720                                         type = "passive";
 721                                 };
 722                                 cpu_crit: cpu_crit {
 723                                         temperature = <95000>; /* millicelsius */
 724                                         hysteresis = <2000>; /* millicelsius */
 725                                         type = "critical";
 726                                 };
 727                         };
 728
 729                         cooling-maps {
 730                                 map0 {
 731                                         trip = <&cpu_alert0>;
 732                                         cooling-device =
 733                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 734                                 };
 735                                 map1 {
 736                                         trip = <&cpu_alert1>;
 737                                         cooling-device =
 738                                                 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 739                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 740                                 };
 741                         };
 742                 };
 743
 744                 gpu {
 745                         polling-delay-passive = <100>; /* milliseconds */
 746                         polling-delay = <1000>; /* milliseconds */
 747
 748                         thermal-sensors = <&tsadc 1>;
 749
 750                         trips {
 751                                 gpu_alert0: gpu_alert0 {
 752                                         temperature = <75000>; /* millicelsius */
 753                                         hysteresis = <2000>; /* millicelsius */
 754                                         type = "passive";
 755                                 };
 756                                 gpu_crit: gpu_crit {
 757                                         temperature = <950000>; /* millicelsius */
 758                                         hysteresis = <2000>; /* millicelsius */
 759                                         type = "critical";
 760                                 };
 761                         };
 762
 763                         cooling-maps {
 764                                 map0 {
 765                                         trip = <&gpu_alert0>;
 766                                         cooling-device =
 767                                                 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 768                                 };
 769                         };
 770                 };
 771         };
 772
 773         tsadc: tsadc@ff260000 {
 774                 compatible = "rockchip,rk3399-tsadc";
 775                 reg = <0x0 0xff260000 0x0 0x100>;
 776                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 777                 rockchip,grf = <&grf>;
 778                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 779                 clock-names = "tsadc", "apb_pclk";
 780                 assigned-clocks = <&cru SCLK_TSADC>;
 781                 assigned-clock-rates = <750000>;
 782                 resets = <&cru SRST_TSADC>;
 783                 reset-names = "tsadc-apb";
 784                 pinctrl-names = "init", "default", "sleep";
 785                 pinctrl-0 = <&otp_gpio>;
 786                 pinctrl-1 = <&otp_out>;
 787                 pinctrl-2 = <&otp_gpio>;
 788                 #thermal-sensor-cells = <1>;
 789                 rockchip,hw-tshut-temp = <95000>;
 790                 status = "disabled";
 791         };
 792
 793         pmu: power-management@ff31000 {
 794                 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
 795                 reg = <0x0 0xff310000 0x0 0x1000>;
 796
 797                 power: power-controller {
 798                         status = "disabled";
 799                         compatible = "rockchip,rk3399-power-controller";
 800                         #power-domain-cells = <1>;
 801                         #address-cells = <1>;
 802                         #size-cells = <0>;
 803
 804                         pd_center {
 805                                 reg = <RK3399_PD_CENTER>;
 806                                 #address-cells = <1>;
 807                                 #size-cells = <0>;
 808
 809                                 pd_vdu {
 810                                         reg = <RK3399_PD_VDU>;
 811                                 };
 812                                 pd_vcodec {
 813                                         reg = <RK3399_PD_VCODEC>;
 814                                 };
 815                                 pd_iep {
 816                                         reg = <RK3399_PD_IEP>;
 817                                 };
 818                                 pd_rga {
 819                                         reg = <RK3399_PD_RGA>;
 820                                 };
 821                         };
 822                         pd_vio {
 823                                 reg = <RK3399_PD_VIO>;
 824                                 #address-cells = <1>;
 825                                 #size-cells = <0>;
 826
 827                                 pd_isp0 {
 828                                         reg = <RK3399_PD_ISP0>;
 829                                 };
 830                                 pd_isp1 {
 831                                         reg = <RK3399_PD_ISP1>;
 832                                 };
 833                                 pd_hdcp {
 834                                         reg = <RK3399_PD_HDCP>;
 835                                 };
 836                                 pd_vo {
 837                                         reg = <RK3399_PD_VO>;
 838                                         #address-cells = <1>;
 839                                         #size-cells = <0>;
 840
 841                                         pd_vopb {
 842                                                 reg = <RK3399_PD_VOPB>;
 843                                         };
 844                                         pd_vopl {
 845                                                 reg = <RK3399_PD_VOPL>;
 846                                         };
 847                                 };
 848                         };
 849                         pd_gpu {
 850                                 reg = <RK3399_PD_GPU>;
 851                         };
 852                 };
 853         };
 854
 855         pmugrf: syscon@ff320000 {
 856                 compatible = "rockchip,rk3399-pmugrf", "syscon";
 857                 reg = <0x0 0xff320000 0x0 0x1000>;
 858         };
 859
 860         spi3: spi@ff350000 {
 861                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 862                 reg = <0x0 0xff350000 0x0 0x1000>;
 863                 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
 864                 clock-names = "spiclk", "apb_pclk";
 865                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 866                 pinctrl-names = "default";
 867                 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
 868                 #address-cells = <1>;
 869                 #size-cells = <0>;
 870                 status = "disabled";
 871         };
 872
 873         uart4: serial@ff370000 {
 874                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 875                 reg = <0x0 0xff370000 0x0 0x100>;
 876                 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
 877                 clock-names = "baudclk", "apb_pclk";
 878                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 879                 reg-shift = <2>;
 880                 reg-io-width = <4>;
 881                 pinctrl-names = "default";
 882                 pinctrl-0 = <&uart4_xfer>;
 883                 status = "disabled";
 884         };
 885
 886         i2c4: i2c@ff3d0000 {
 887                 compatible = "rockchip,rk3399-i2c";
 888                 reg = <0x0 0xff3d0000 0x0 0x1000>;
 889                 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
 890                 clock-names = "i2c", "pclk";
 891                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 892                 pinctrl-names = "default";
 893                 pinctrl-0 = <&i2c4_xfer>;
 894                 #address-cells = <1>;
 895                 #size-cells = <0>;
 896                 status = "disabled";
 897         };
 898
 899         i2c8: i2c@ff3e0000 {
 900                 compatible = "rockchip,rk3399-i2c";
 901                 reg = <0x0 0xff3e0000 0x0 0x1000>;
 902                 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
 903                 clock-names = "i2c", "pclk";
 904                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 905                 pinctrl-names = "default";
 906                 pinctrl-0 = <&i2c8_xfer>;
 907                 #address-cells = <1>;
 908                 #size-cells = <0>;
 909                 status = "disabled";
 910         };
 911
 912         pwm0: pwm@ff420000 {
 913                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 914                 reg = <0x0 0xff420000 0x0 0x10>;
 915                 #pwm-cells = <3>;
 916                 pinctrl-names = "default";
 917                 pinctrl-0 = <&pwm0_pin>;
 918                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 919                 clock-names = "pwm";
 920                 status = "disabled";
 921         };
 922
 923         pwm1: pwm@ff420010 {
 924                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 925                 reg = <0x0 0xff420010 0x0 0x10>;
 926                 #pwm-cells = <3>;
 927                 pinctrl-names = "default";
 928                 pinctrl-0 = <&pwm1_pin>;
 929                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 930                 clock-names = "pwm";
 931                 status = "disabled";
 932         };
 933
 934         pwm2: pwm@ff420020 {
 935                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 936                 reg = <0x0 0xff420020 0x0 0x10>;
 937                 #pwm-cells = <3>;
 938                 pinctrl-names = "default";
 939                 pinctrl-0 = <&pwm2_pin>;
 940                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 941                 clock-names = "pwm";
 942                 status = "disabled";
 943         };
 944
 945         pwm3: pwm@ff420030 {
 946                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 947                 reg = <0x0 0xff420030 0x0 0x10>;
 948                 #pwm-cells = <3>;
 949                 pinctrl-names = "default";
 950                 pinctrl-0 = <&pwm3a_pin>;
 951                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 952                 clock-names = "pwm";
 953                 status = "disabled";
 954         };
 955
 956         rga: rga@ff680000 {
 957                 compatible = "rockchip,rk3399-rga";
 958                 reg = <0x0 0xff680000 0x0 0x10000>;
 959                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 960                 interrupt-names = "rga";
 961                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
 962                 clock-names = "aclk", "hclk", "sclk";
 963                 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
 964                 reset-names = "core", "axi", "ahb";
 965                 status = "disabled";
 966         };
 967
 968         pmucru: pmu-clock-controller@ff750000 {
 969                 compatible = "rockchip,rk3399-pmucru";
 970                 reg = <0x0 0xff750000 0x0 0x1000>;
 971                 #clock-cells = <1>;
 972                 #reset-cells = <1>;
 973                 assigned-clocks = <&pmucru PLL_PPLL>;
 974                 assigned-clock-rates = <676000000>;
 975         };
 976
 977         cru: clock-controller@ff760000 {
 978                 compatible = "rockchip,rk3399-cru";
 979                 reg = <0x0 0xff760000 0x0 0x1000>;
 980                 #clock-cells = <1>;
 981                 #reset-cells = <1>;
 982                 assigned-clocks =
 983                         <&cru ACLK_VOP0>, <&cru HCLK_VOP0>,
 984                         <&cru ACLK_VOP1>, <&cru HCLK_VOP1>,
 985                         <&cru ARMCLKL>, <&cru ARMCLKB>,
 986                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 987                         <&cru PLL_NPLL>,
 988                         <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
 989                         <&cru PCLK_PERIHP>,
 990                         <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
 991                         <&cru PCLK_PERILP0>,
 992                         <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
 993                 assigned-clock-rates =
 994                          <400000000>,  <200000000>,
 995                          <400000000>,  <200000000>,
 996                          <816000000>, <1008000000>,
 997                          <594000000>,  <800000000>,
 998                         <1000000000>,
 999                          <150000000>,   <75000000>,
1000                           <37500000>,
1001                          <100000000>,  <100000000>,
1002                           <50000000>,
1003                          <100000000>,   <50000000>;
1004         };
1005
1006         grf: syscon@ff770000 {
1007                 compatible = "rockchip,rk3399-grf", "syscon";
1008                 reg = <0x0 0xff770000 0x0 0x10000>;
1009         };
1010
1011         wdt0: watchdog@ff840000 {
1012                 compatible = "snps,dw-wdt";
1013                 reg = <0x0 0xff840000 0x0 0x100>;
1014                 clocks = <&cru PCLK_WDT>;
1015                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1016                 status = "disabled";
1017         };
1018
1019         spdif: spdif@ff870000 {
1020                 compatible = "rockchip,rk3399-spdif";
1021                 reg = <0x0 0xff870000 0x0 0x1000>;
1022                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
1023                 dmas = <&dmac_bus 7>;
1024                 dma-names = "tx";
1025                 clock-names = "mclk", "hclk";
1026                 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1027                 pinctrl-names = "default";
1028                 pinctrl-0 = <&spdif_bus>;
1029                 status = "disabled";
1030         };
1031
1032         i2s0: i2s@ff880000 {
1033                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1034                 reg = <0x0 0xff880000 0x0 0x1000>;
1035                 rockchip,grf = <&grf>;
1036                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1037                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1038                 dma-names = "tx", "rx";
1039                 clock-names = "i2s_clk", "i2s_hclk";
1040                 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1041                 pinctrl-names = "default";
1042                 pinctrl-0 = <&i2s0_8ch_bus>;
1043                 status = "disabled";
1044         };
1045
1046         i2s1: i2s@ff890000 {
1047                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1048                 reg = <0x0 0xff890000 0x0 0x1000>;
1049                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1050                 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1051                 dma-names = "tx", "rx";
1052                 clock-names = "i2s_clk", "i2s_hclk";
1053                 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1054                 pinctrl-names = "default";
1055                 pinctrl-0 = <&i2s1_2ch_bus>;
1056                 status = "disabled";
1057         };
1058
1059         i2s2: i2s@ff8a0000 {
1060                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1061                 reg = <0x0 0xff8a0000 0x0 0x1000>;
1062                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1063                 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1064                 dma-names = "tx", "rx";
1065                 clock-names = "i2s_clk", "i2s_hclk";
1066                 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1067                 status = "disabled";
1068         };
1069
1070         gpu: gpu@ff9a0000 {
1071                 compatible = "arm,malit860",
1072                              "arm,malit86x",
1073                              "arm,malit8xx",
1074                              "arm,mali-midgard";
1075
1076                 reg = <0x0 0xff9a0000 0x0 0x10000>;
1077
1078                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
1079                              <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
1080                              <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1081                 interrupt-names = "GPU", "JOB", "MMU";
1082
1083                 clocks = <&cru ACLK_GPU>;
1084                 clock-names = "clk_mali";
1085                 #cooling-cells = <2>; /* min followed by max */
1086                 operating-points-v2 = <&gpu_opp_table>;
1087
1088                 status = "disabled";
1089
1090                 power_model {
1091                         compatible = "arm,mali-simple-power-model";
1092                         voltage = <900>;
1093                         frequency = <500>;
1094                         static-power = <500>;
1095                         dynamic-power = <1500>;
1096                         ts = <20000 2000 (-20) 2>;
1097                         thermal-zone = "gpu";
1098                 };
1099         };
1100
1101         gpu_opp_table: gpu_opp_table {
1102                 compatible = "operating-points-v2";
1103                 opp-shared;
1104
1105                 opp00 {
1106                         opp-hz = /bits/ 64 <200000000>;
1107                         opp-microvolt = <900000>;
1108                 };
1109                 opp01 {
1110                         opp-hz = /bits/ 64 <300000000>;
1111                         opp-microvolt = <900000>;
1112                 };
1113                 opp02 {
1114                         opp-hz = /bits/ 64 <400000000>;
1115                         opp-microvolt = <900000>;
1116                 };
1117
1118         };
1119
1120         vopl: vop@ff8f0000 {
1121                 compatible = "rockchip,rk3399-vop-lit";
1122                 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1123                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
1124                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1125                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1126                 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1127                 reset-names = "axi", "ahb", "dclk";
1128                 iommus = <&vopl_mmu>;
1129                 status = "disabled";
1130
1131                 vopl_out: port {
1132                         #address-cells = <1>;
1133                         #size-cells = <0>;
1134
1135                         vopl_out_mipi: endpoint@0 {
1136                                 reg = <0>;
1137                                 remote-endpoint = <&mipi_in_vopl>;
1138                         };
1139
1140                         vopl_out_edp: endpoint@1 {
1141                                 reg = <1>;
1142                                 remote-endpoint = <&edp_in_vopl>;
1143                         };
1144                 };
1145         };
1146
1147         vopl_mmu: iommu@ff8f3f00 {
1148                 compatible = "rockchip,iommu";
1149                 reg = <0x0 0xff8f3f00 0x0 0x100>;
1150                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
1151                 interrupt-names = "vopl_mmu";
1152                 #iommu-cells = <0>;
1153                 status = "disabled";
1154         };
1155
1156         vopb: vop@ff900000 {
1157                 compatible = "rockchip,rk3399-vop-big";
1158                 reg = <0x0 0xff900000 0x0 0x3efc>;
1159                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1160                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1161                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1162                 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1163                 reset-names = "axi", "ahb", "dclk";
1164                 iommus = <&vopb_mmu>;
1165                 status = "disabled";
1166
1167                 vopb_out: port {
1168                         #address-cells = <1>;
1169                         #size-cells = <0>;
1170
1171                         vopb_out_edp: endpoint@0 {
1172                                 reg = <0>;
1173                                 remote-endpoint = <&edp_in_vopb>;
1174                         };
1175
1176                         vopb_out_mipi: endpoint@1 {
1177                                 reg = <1>;
1178                                 remote-endpoint = <&mipi_in_vopb>;
1179                         };
1180                 };
1181         };
1182
1183         vopb_mmu: iommu@ff903f00 {
1184                 compatible = "rockchip,iommu";
1185                 reg = <0x0 0xff903f00 0x0 0x100>;
1186                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1187                 interrupt-names = "vopb_mmu";
1188                 #iommu-cells = <0>;
1189                 status = "disabled";
1190         };
1191
1192         mipi_dsi: mipi@ff960000 {
1193                 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1194                 reg = <0x0 0xff960000 0x0 0x8000>;
1195                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1196                 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
1197                          <&cru SCLK_DPHY_TX0_CFG>;
1198                 clock-names = "ref", "pclk", "phy_cfg";
1199                 rockchip,grf = <&grf>;
1200                 #address-cells = <1>;
1201                 #size-cells = <0>;
1202                 status = "disabled";
1203
1204                 ports {
1205                         #address-cells = <1>;
1206                         #size-cells = <0>;
1207                         reg = <1>;
1208
1209                         mipi_in: port {
1210                                 #address-cells = <1>;
1211                                 #size-cells = <0>;
1212
1213                                 mipi_in_vopb: endpoint@0 {
1214                                         reg = <0>;
1215                                         remote-endpoint = <&vopb_out_mipi>;
1216                                 };
1217                                 mipi_in_vopl: endpoint@1 {
1218                                         reg = <1>;
1219                                         remote-endpoint = <&vopl_out_mipi>;
1220                                 };
1221                         };
1222                 };
1223         };
1224
1225         edp: edp@ff970000 {
1226                 compatible = "rockchip,rk3399-edp";
1227                 reg = <0x0 0xff970000 0x0 0x8000>;
1228                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1229                 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1230                 clock-names = "dp", "pclk";
1231                 resets = <&cru SRST_P_EDP_CTRL>;
1232                 reset-names = "dp";
1233                 rockchip,grf = <&grf>;
1234                 status = "disabled";
1235                 pinctrl-names = "default";
1236                 pinctrl-0 = <&edp_hpd>;
1237
1238                 ports {
1239                         #address-cells = <1>;
1240                         #size-cells = <0>;
1241
1242                         edp_in: port@0 {
1243                                 reg = <0>;
1244                                 #address-cells = <1>;
1245                                 #size-cells = <0>;
1246
1247                                 edp_in_vopb: endpoint@0 {
1248                                         reg = <0>;
1249                                         remote-endpoint = <&vopb_out_edp>;
1250                                 };
1251
1252                                 edp_in_vopl: endpoint@1 {
1253                                         reg = <1>;
1254                                         remote-endpoint = <&vopl_out_edp>;
1255                                 };
1256                         };
1257                 };
1258         };
1259
1260         display_subsystem: display-subsystem {
1261                 compatible = "rockchip,display-subsystem";
1262                 ports = <&vopl_out>, <&vopb_out>;
1263                 status = "disabled";
1264         };
1265
1266         pinctrl: pinctrl {
1267                 compatible = "rockchip,rk3399-pinctrl";
1268                 rockchip,grf = <&grf>;
1269                 rockchip,pmu = <&pmugrf>;
1270                 #address-cells = <0x2>;
1271                 #size-cells = <0x2>;
1272                 ranges;
1273
1274                 gpio0: gpio0@ff720000 {
1275                         compatible = "rockchip,gpio-bank";
1276                         reg = <0x0 0xff720000 0x0 0x100>;
1277                         clocks = <&pmucru PCLK_GPIO0_PMU>;
1278                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1279
1280                         gpio-controller;
1281                         #gpio-cells = <0x2>;
1282
1283                         interrupt-controller;
1284                         #interrupt-cells = <0x2>;
1285                 };
1286
1287                 gpio1: gpio1@ff730000 {
1288                         compatible = "rockchip,gpio-bank";
1289                         reg = <0x0 0xff730000 0x0 0x100>;
1290                         clocks = <&pmucru PCLK_GPIO1_PMU>;
1291                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1292
1293                         gpio-controller;
1294                         #gpio-cells = <0x2>;
1295
1296                         interrupt-controller;
1297                         #interrupt-cells = <0x2>;
1298                 };
1299
1300                 gpio2: gpio2@ff780000 {
1301                         compatible = "rockchip,gpio-bank";
1302                         reg = <0x0 0xff780000 0x0 0x100>;
1303                         clocks = <&cru PCLK_GPIO2>;
1304                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1305
1306                         gpio-controller;
1307                         #gpio-cells = <0x2>;
1308
1309                         interrupt-controller;
1310                         #interrupt-cells = <0x2>;
1311                 };
1312
1313                 gpio3: gpio3@ff788000 {
1314                         compatible = "rockchip,gpio-bank";
1315                         reg = <0x0 0xff788000 0x0 0x100>;
1316                         clocks = <&cru PCLK_GPIO3>;
1317                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1318
1319                         gpio-controller;
1320                         #gpio-cells = <0x2>;
1321
1322                         interrupt-controller;
1323                         #interrupt-cells = <0x2>;
1324                 };
1325
1326                 gpio4: gpio4@ff790000 {
1327                         compatible = "rockchip,gpio-bank";
1328                         reg = <0x0 0xff790000 0x0 0x100>;
1329                         clocks = <&cru PCLK_GPIO4>;
1330                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1331
1332                         gpio-controller;
1333                         #gpio-cells = <0x2>;
1334
1335                         interrupt-controller;
1336                         #interrupt-cells = <0x2>;
1337                 };
1338
1339                 pcfg_pull_up: pcfg-pull-up {
1340                         bias-pull-up;
1341                 };
1342
1343                 pcfg_pull_down: pcfg-pull-down {
1344                         bias-pull-down;
1345                 };
1346
1347                 pcfg_pull_none: pcfg-pull-none {
1348                         bias-disable;
1349                 };
1350
1351                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1352                         bias-disable;
1353                         drive-strength = <12>;
1354                 };
1355
1356                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1357                         bias-pull-up;
1358                         drive-strength = <8>;
1359                 };
1360
1361                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1362                         bias-pull-down;
1363                         drive-strength = <4>;
1364                 };
1365
1366                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1367                         bias-pull-up;
1368                         drive-strength = <2>;
1369                 };
1370
1371                 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
1372                         bias-pull-down;
1373                         drive-strength = <12>;
1374                 };
1375
1376                 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
1377                         bias-disable;
1378                         drive-strength = <13>;
1379                 };
1380
1381                 emmc {
1382                         emmc_pwr: emmc-pwr {
1383                                 rockchip,pins =
1384                                         <0 5 RK_FUNC_1 &pcfg_pull_up>;
1385                         };
1386                 };
1387
1388                 gmac {
1389                         rgmii_pins: rgmii-pins {
1390                                 rockchip,pins =
1391                                         /* mac_txclk */
1392                                         <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
1393                                         /* mac_rxclk */
1394                                         <3 14 RK_FUNC_1 &pcfg_pull_none>,
1395                                         /* mac_mdio */
1396                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
1397                                         /* mac_txen */
1398                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1399                                         /* mac_clk */
1400                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
1401                                         /* mac_rxdv */
1402                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
1403                                         /* mac_mdc */
1404                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
1405                                         /* mac_rxd1 */
1406                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
1407                                         /* mac_rxd0 */
1408                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
1409                                         /* mac_txd1 */
1410                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1411                                         /* mac_txd0 */
1412                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
1413                                         /* mac_rxd3 */
1414                                         <3 3 RK_FUNC_1 &pcfg_pull_none>,
1415                                         /* mac_rxd2 */
1416                                         <3 2 RK_FUNC_1 &pcfg_pull_none>,
1417                                         /* mac_txd3 */
1418                                         <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
1419                                         /* mac_txd2 */
1420                                         <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
1421                         };
1422
1423                         rmii_pins: rmii-pins {
1424                                 rockchip,pins =
1425                                         /* mac_mdio */
1426                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
1427                                         /* mac_txen */
1428                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1429                                         /* mac_clk */
1430                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
1431                                         /* mac_rxer */
1432                                         <3 10 RK_FUNC_1 &pcfg_pull_none>,
1433                                         /* mac_rxdv */
1434                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
1435                                         /* mac_mdc */
1436                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
1437                                         /* mac_rxd1 */
1438                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
1439                                         /* mac_rxd0 */
1440                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
1441                                         /* mac_txd1 */
1442                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1443                                         /* mac_txd0 */
1444                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
1445                         };
1446                 };
1447
1448                 i2c0 {
1449                         i2c0_xfer: i2c0-xfer {
1450                                 rockchip,pins =
1451                                         <1 15 RK_FUNC_2 &pcfg_pull_none>,
1452                                         <1 16 RK_FUNC_2 &pcfg_pull_none>;
1453                         };
1454                 };
1455
1456                 i2c1 {
1457                         i2c1_xfer: i2c1-xfer {
1458                                 rockchip,pins =
1459                                         <4 2 RK_FUNC_1 &pcfg_pull_none>,
1460                                         <4 1 RK_FUNC_1 &pcfg_pull_none>;
1461                         };
1462                 };
1463
1464                 i2c2 {
1465                         i2c2_xfer: i2c2-xfer {
1466                                 rockchip,pins =
1467                                         <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1468                                         <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
1469                         };
1470                 };
1471
1472                 i2c3 {
1473                         i2c3_xfer: i2c3-xfer {
1474                                 rockchip,pins =
1475                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
1476                                         <4 16 RK_FUNC_1 &pcfg_pull_none>;
1477                         };
1478                 };
1479
1480                 i2c4 {
1481                         i2c4_xfer: i2c4-xfer {
1482                                 rockchip,pins =
1483                                         <1 12 RK_FUNC_1 &pcfg_pull_none>,
1484                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
1485                         };
1486                 };
1487
1488                 i2c5 {
1489                         i2c5_xfer: i2c5-xfer {
1490                                 rockchip,pins =
1491                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
1492                                         <3 10 RK_FUNC_2 &pcfg_pull_none>;
1493                         };
1494                 };
1495
1496                 i2c6 {
1497                         i2c6_xfer: i2c6-xfer {
1498                                 rockchip,pins =
1499                                         <2 10 RK_FUNC_2 &pcfg_pull_none>,
1500                                         <2 9 RK_FUNC_2 &pcfg_pull_none>;
1501                         };
1502                 };
1503
1504                 i2c7 {
1505                         i2c7_xfer: i2c7-xfer {
1506                                 rockchip,pins =
1507                                         <2 8 RK_FUNC_2 &pcfg_pull_none>,
1508                                         <2 7 RK_FUNC_2 &pcfg_pull_none>;
1509                         };
1510                 };
1511
1512                 i2c8 {
1513                         i2c8_xfer: i2c8-xfer {
1514                                 rockchip,pins =
1515                                         <1 21 RK_FUNC_1 &pcfg_pull_none>,
1516                                         <1 20 RK_FUNC_1 &pcfg_pull_none>;
1517                         };
1518                 };
1519
1520                 i2s0 {
1521                         i2s0_8ch_bus: i2s0-8ch-bus {
1522                                 rockchip,pins =
1523                                         <3 24 RK_FUNC_1 &pcfg_pull_none>,
1524                                         <3 25 RK_FUNC_1 &pcfg_pull_none>,
1525                                         <3 26 RK_FUNC_1 &pcfg_pull_none>,
1526                                         <3 27 RK_FUNC_1 &pcfg_pull_none>,
1527                                         <3 28 RK_FUNC_1 &pcfg_pull_none>,
1528                                         <3 29 RK_FUNC_1 &pcfg_pull_none>,
1529                                         <3 30 RK_FUNC_1 &pcfg_pull_none>,
1530                                         <3 31 RK_FUNC_1 &pcfg_pull_none>,
1531                                         <4 0 RK_FUNC_1 &pcfg_pull_none>;
1532                         };
1533                 };
1534
1535                 i2s1 {
1536                         i2s1_2ch_bus: i2s1-2ch-bus {
1537                                 rockchip,pins =
1538                                         <4 3 RK_FUNC_1 &pcfg_pull_none>,
1539                                         <4 4 RK_FUNC_1 &pcfg_pull_none>,
1540                                         <4 5 RK_FUNC_1 &pcfg_pull_none>,
1541                                         <4 6 RK_FUNC_1 &pcfg_pull_none>,
1542                                         <4 7 RK_FUNC_1 &pcfg_pull_none>;
1543                         };
1544                 };
1545
1546                 sdio0 {
1547                         sdio0_bus1: sdio0-bus1 {
1548                                 rockchip,pins =
1549                                         <2 20 RK_FUNC_1 &pcfg_pull_up>;
1550                         };
1551
1552                         sdio0_bus4: sdio0-bus4 {
1553                                 rockchip,pins =
1554                                         <2 20 RK_FUNC_1 &pcfg_pull_up>,
1555                                         <2 21 RK_FUNC_1 &pcfg_pull_up>,
1556                                         <2 22 RK_FUNC_1 &pcfg_pull_up>,
1557                                         <2 23 RK_FUNC_1 &pcfg_pull_up>;
1558                         };
1559
1560                         sdio0_cmd: sdio0-cmd {
1561                                 rockchip,pins =
1562                                         <2 24 RK_FUNC_1 &pcfg_pull_up>;
1563                         };
1564
1565                         sdio0_clk: sdio0-clk {
1566                                 rockchip,pins =
1567                                         <2 25 RK_FUNC_1 &pcfg_pull_none>;
1568                         };
1569
1570                         sdio0_cd: sdio0-cd {
1571                                 rockchip,pins =
1572                                         <2 26 RK_FUNC_1 &pcfg_pull_up>;
1573                         };
1574
1575                         sdio0_pwr: sdio0-pwr {
1576                                 rockchip,pins =
1577                                         <2 27 RK_FUNC_1 &pcfg_pull_up>;
1578                         };
1579
1580                         sdio0_bkpwr: sdio0-bkpwr {
1581                                 rockchip,pins =
1582                                         <2 28 RK_FUNC_1 &pcfg_pull_up>;
1583                         };
1584
1585                         sdio0_wp: sdio0-wp {
1586                                 rockchip,pins =
1587                                         <0 3 RK_FUNC_1 &pcfg_pull_up>;
1588                         };
1589
1590                         sdio0_int: sdio0-int {
1591                                 rockchip,pins =
1592                                         <0 4 RK_FUNC_1 &pcfg_pull_up>;
1593                         };
1594                 };
1595
1596                 sdmmc {
1597                         sdmmc_bus1: sdmmc-bus1 {
1598                                 rockchip,pins =
1599                                         <4 8 RK_FUNC_1 &pcfg_pull_up>;
1600                         };
1601
1602                         sdmmc_bus4: sdmmc-bus4 {
1603                                 rockchip,pins =
1604                                         <4 8 RK_FUNC_1 &pcfg_pull_up>,
1605                                         <4 9 RK_FUNC_1 &pcfg_pull_up>,
1606                                         <4 10 RK_FUNC_1 &pcfg_pull_up>,
1607                                         <4 11 RK_FUNC_1 &pcfg_pull_up>;
1608                         };
1609
1610                         sdmmc_clk: sdmmc-clk {
1611                                 rockchip,pins =
1612                                         <4 12 RK_FUNC_1 &pcfg_pull_none>;
1613                         };
1614
1615                         sdmmc_cmd: sdmmc-cmd {
1616                                 rockchip,pins =
1617                                         <4 13 RK_FUNC_1 &pcfg_pull_up>;
1618                         };
1619
1620                         sdmmc_cd: sdmcc-cd {
1621                                 rockchip,pins =
1622                                         <0 7 RK_FUNC_1 &pcfg_pull_up>;
1623                         };
1624
1625                         sdmmc_wp: sdmmc-wp {
1626                                 rockchip,pins =
1627                                         <0 8 RK_FUNC_1 &pcfg_pull_up>;
1628                         };
1629                 };
1630
1631                 spdif {
1632                         spdif_bus: spdif-bus {
1633                                 rockchip,pins =
1634                                         <4 21 RK_FUNC_1 &pcfg_pull_none>;
1635                         };
1636                 };
1637
1638                 spi0 {
1639                         spi0_clk: spi0-clk {
1640                                 rockchip,pins =
1641                                         <3 6 RK_FUNC_2 &pcfg_pull_up>;
1642                         };
1643                         spi0_cs0: spi0-cs0 {
1644                                 rockchip,pins =
1645                                         <3 7 RK_FUNC_2 &pcfg_pull_up>;
1646                         };
1647                         spi0_cs1: spi0-cs1 {
1648                                 rockchip,pins =
1649                                         <3 8 RK_FUNC_2 &pcfg_pull_up>;
1650                         };
1651                         spi0_tx: spi0-tx {
1652                                 rockchip,pins =
1653                                         <3 5 RK_FUNC_2 &pcfg_pull_up>;
1654                         };
1655                         spi0_rx: spi0-rx {
1656                                 rockchip,pins =
1657                                         <3 4 RK_FUNC_2 &pcfg_pull_up>;
1658                         };
1659                 };
1660
1661                 spi1 {
1662                         spi1_clk: spi1-clk {
1663                                 rockchip,pins =
1664                                         <1 9 RK_FUNC_2 &pcfg_pull_up>;
1665                         };
1666                         spi1_cs0: spi1-cs0 {
1667                                 rockchip,pins =
1668                                         <1 10 RK_FUNC_2 &pcfg_pull_up>;
1669                         };
1670                         spi1_rx: spi1-rx {
1671                                 rockchip,pins =
1672                                         <1 7 RK_FUNC_2 &pcfg_pull_up>;
1673                         };
1674                         spi1_tx: spi1-tx {
1675                                 rockchip,pins =
1676                                         <1 8 RK_FUNC_2 &pcfg_pull_up>;
1677                         };
1678                 };
1679
1680                 spi2 {
1681                         spi2_clk: spi2-clk {
1682                                 rockchip,pins =
1683                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
1684                         };
1685                         spi2_cs0: spi2-cs0 {
1686                                 rockchip,pins =
1687                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
1688                         };
1689                         spi2_rx: spi2-rx {
1690                                 rockchip,pins =
1691                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
1692                         };
1693                         spi2_tx: spi2-tx {
1694                                 rockchip,pins =
1695                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
1696                         };
1697                 };
1698
1699                 spi3 {
1700                         spi3_clk: spi3-clk {
1701                                 rockchip,pins =
1702                                         <1 17 RK_FUNC_1 &pcfg_pull_up>;
1703                         };
1704                         spi3_cs0: spi3-cs0 {
1705                                 rockchip,pins =
1706                                         <1 18 RK_FUNC_1 &pcfg_pull_up>;
1707                         };
1708                         spi3_rx: spi3-rx {
1709                                 rockchip,pins =
1710                                         <1 15 RK_FUNC_1 &pcfg_pull_up>;
1711                         };
1712                         spi3_tx: spi3-tx {
1713                                 rockchip,pins =
1714                                         <1 16 RK_FUNC_1 &pcfg_pull_up>;
1715                         };
1716                 };
1717
1718                 spi4 {
1719                         spi4_clk: spi4-clk {
1720                                 rockchip,pins =
1721                                         <3 2 RK_FUNC_2 &pcfg_pull_up>;
1722                         };
1723                         spi4_cs0: spi4-cs0 {
1724                                 rockchip,pins =
1725                                         <3 3 RK_FUNC_2 &pcfg_pull_up>;
1726                         };
1727                         spi4_rx: spi4-rx {
1728                                 rockchip,pins =
1729                                         <3 0 RK_FUNC_2 &pcfg_pull_up>;
1730                         };
1731                         spi4_tx: spi4-tx {
1732                                 rockchip,pins =
1733                                         <3 1 RK_FUNC_2 &pcfg_pull_up>;
1734                         };
1735                 };
1736
1737                 spi5 {
1738                         spi5_clk: spi5-clk {
1739                                 rockchip,pins =
1740                                         <2 22 RK_FUNC_2 &pcfg_pull_up>;
1741                         };
1742                         spi5_cs0: spi5-cs0 {
1743                                 rockchip,pins =
1744                                         <2 23 RK_FUNC_2 &pcfg_pull_up>;
1745                         };
1746                         spi5_rx: spi5-rx {
1747                                 rockchip,pins =
1748                                         <2 20 RK_FUNC_2 &pcfg_pull_up>;
1749                         };
1750                         spi5_tx: spi5-tx {
1751                                 rockchip,pins =
1752                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
1753                         };
1754                 };
1755
1756                 tsadc {
1757                         otp_gpio: otp-gpio {
1758                                 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
1759                         };
1760
1761                         otp_out: otp-out {
1762                                 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
1763                         };
1764                 };
1765
1766                 uart0 {
1767                         uart0_xfer: uart0-xfer {
1768                                 rockchip,pins =
1769                                         <2 16 RK_FUNC_1 &pcfg_pull_up>,
1770                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
1771                         };
1772
1773                         uart0_cts: uart0-cts {
1774                                 rockchip,pins =
1775                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
1776                         };
1777
1778                         uart0_rts: uart0-rts {
1779                                 rockchip,pins =
1780                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
1781                         };
1782                 };
1783
1784                 uart1 {
1785                         uart1_xfer: uart1-xfer {
1786                                 rockchip,pins =
1787                                         <3 12 RK_FUNC_2 &pcfg_pull_up>,
1788                                         <3 13 RK_FUNC_2 &pcfg_pull_none>;
1789                         };
1790                 };
1791
1792                 uart2a {
1793                         uart2a_xfer: uart2a-xfer {
1794                                 rockchip,pins =
1795                                         <4 8 RK_FUNC_2 &pcfg_pull_up>,
1796                                         <4 9 RK_FUNC_2 &pcfg_pull_none>;
1797                         };
1798                 };
1799
1800                 uart2b {
1801                         uart2b_xfer: uart2b-xfer {
1802                                 rockchip,pins =
1803                                         <4 16 RK_FUNC_2 &pcfg_pull_up>,
1804                                         <4 17 RK_FUNC_2 &pcfg_pull_none>;
1805                         };
1806                 };
1807
1808                 uart2c {
1809                         uart2c_xfer: uart2c-xfer {
1810                                 rockchip,pins =
1811                                         <4 19 RK_FUNC_1 &pcfg_pull_up>,
1812                                         <4 20 RK_FUNC_1 &pcfg_pull_none>;
1813                         };
1814                 };
1815
1816                 uart3 {
1817                         uart3_xfer: uart3-xfer {
1818                                 rockchip,pins =
1819                                         <3 14 RK_FUNC_2 &pcfg_pull_up>,
1820                                         <3 15 RK_FUNC_2 &pcfg_pull_none>;
1821                         };
1822
1823                         uart3_cts: uart3-cts {
1824                                 rockchip,pins =
1825                                         <3 18 RK_FUNC_2 &pcfg_pull_none>;
1826                         };
1827
1828                         uart3_rts: uart3-rts {
1829                                 rockchip,pins =
1830                                         <3 19 RK_FUNC_2 &pcfg_pull_none>;
1831                         };
1832                 };
1833
1834                 uart4 {
1835                         uart4_xfer: uart4-xfer {
1836                                 rockchip,pins =
1837                                         <1 7 RK_FUNC_1 &pcfg_pull_up>,
1838                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
1839                         };
1840                 };
1841
1842                 uarthdcp {
1843                         uarthdcp_xfer: uarthdcp-xfer {
1844                                 rockchip,pins =
1845                                         <4 21 RK_FUNC_2 &pcfg_pull_up>,
1846                                         <4 22 RK_FUNC_2 &pcfg_pull_none>;
1847                         };
1848                 };
1849
1850                 pwm0 {
1851                         pwm0_pin: pwm0-pin {
1852                                 rockchip,pins =
1853                                         <4 18 RK_FUNC_1 &pcfg_pull_none>;
1854                         };
1855
1856                         vop0_pwm_pin: vop0-pwm-pin {
1857                                 rockchip,pins =
1858                                         <4 18 RK_FUNC_2 &pcfg_pull_none>;
1859                         };
1860                 };
1861
1862                 pwm1 {
1863                         pwm1_pin: pwm1-pin {
1864                                 rockchip,pins =
1865                                         <4 22 RK_FUNC_1 &pcfg_pull_none>;
1866                         };
1867
1868                         vop1_pwm_pin: vop1-pwm-pin {
1869                                 rockchip,pins =
1870                                         <4 18 RK_FUNC_3 &pcfg_pull_none>;
1871                         };
1872                 };
1873
1874                 pwm2 {
1875                         pwm2_pin: pwm2-pin {
1876                                 rockchip,pins =
1877                                         <1 19 RK_FUNC_1 &pcfg_pull_none>;
1878                         };
1879                 };
1880
1881                 pwm3a {
1882                         pwm3a_pin: pwm3a-pin {
1883                                 rockchip,pins =
1884                                         <0 6 RK_FUNC_1 &pcfg_pull_none>;
1885                         };
1886                 };
1887
1888                 pwm3b {
1889                         pwm3b_pin: pwm3b-pin {
1890                                 rockchip,pins =
1891                                         <1 14 RK_FUNC_1 &pcfg_pull_none>;
1892                         };
1893                 };
1894
1895                 edp {
1896                         edp_hpd: edp-hpd {
1897                                 rockchip,pins =
1898                                         <4 23 RK_FUNC_2 &pcfg_pull_none>;
1899                         };
1900                 };
1901         };
1902 };