2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/clock/rk3399-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/interrupt-controller/irq.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/power/rk3399-power.h>
49 #include <dt-bindings/soc/rockchip_boot-mode.h>
50 #include <dt-bindings/thermal/thermal.h>
52 #include "rk3399-dram-default-timing.dtsi"
55 compatible = "rockchip,rk3399";
57 interrupt-parent = <&gic>;
79 compatible = "arm,psci-1.0";
115 compatible = "arm,cortex-a53", "arm,armv8";
117 enable-method = "psci";
118 #cooling-cells = <2>; /* min followed by max */
119 dynamic-power-coefficient = <100>;
120 clocks = <&cru ARMCLKL>;
121 cpu-idle-states = <&cpu_sleep>;
122 operating-points-v2 = <&cluster0_opp>;
123 sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
128 compatible = "arm,cortex-a53", "arm,armv8";
130 enable-method = "psci";
131 clocks = <&cru ARMCLKL>;
132 cpu-idle-states = <&cpu_sleep>;
133 operating-points-v2 = <&cluster0_opp>;
134 sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
139 compatible = "arm,cortex-a53", "arm,armv8";
141 enable-method = "psci";
142 clocks = <&cru ARMCLKL>;
143 cpu-idle-states = <&cpu_sleep>;
144 operating-points-v2 = <&cluster0_opp>;
145 sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
150 compatible = "arm,cortex-a53", "arm,armv8";
152 enable-method = "psci";
153 clocks = <&cru ARMCLKL>;
154 cpu-idle-states = <&cpu_sleep>;
155 operating-points-v2 = <&cluster0_opp>;
156 sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
161 compatible = "arm,cortex-a72", "arm,armv8";
163 enable-method = "psci";
164 #cooling-cells = <2>; /* min followed by max */
165 dynamic-power-coefficient = <436>;
166 clocks = <&cru ARMCLKB>;
167 cpu-idle-states = <&cpu_sleep>;
168 operating-points-v2 = <&cluster1_opp>;
169 sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>;
174 compatible = "arm,cortex-a72", "arm,armv8";
176 enable-method = "psci";
177 clocks = <&cru ARMCLKB>;
178 cpu-idle-states = <&cpu_sleep>;
179 operating-points-v2 = <&cluster1_opp>;
180 sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>;
184 entry-method = "psci";
185 cpu_sleep: cpu-sleep-0 {
186 compatible = "arm,idle-state";
188 arm,psci-suspend-param = <0x0010000>;
189 entry-latency-us = <350>;
190 exit-latency-us = <600>;
191 min-residency-us = <1150>;
195 /include/ "rk3399-sched-energy.dtsi"
199 cluster0_opp: opp_table0 {
200 compatible = "operating-points-v2";
204 opp-hz = /bits/ 64 <408000000>;
205 opp-microvolt = <800000>;
206 clock-latency-ns = <40000>;
209 opp-hz = /bits/ 64 <600000000>;
210 opp-microvolt = <800000>;
213 opp-hz = /bits/ 64 <816000000>;
214 opp-microvolt = <800000>;
217 opp-hz = /bits/ 64 <1008000000>;
218 opp-microvolt = <875000>;
221 opp-hz = /bits/ 64 <1200000000>;
222 opp-microvolt = <925000>;
225 opp-hz = /bits/ 64 <1416000000>;
226 opp-microvolt = <1025000>;
230 cluster1_opp: opp_table1 {
231 compatible = "operating-points-v2";
235 opp-hz = /bits/ 64 <408000000>;
236 opp-microvolt = <800000>;
237 clock-latency-ns = <40000>;
240 opp-hz = /bits/ 64 <600000000>;
241 opp-microvolt = <800000>;
244 opp-hz = /bits/ 64 <816000000>;
245 opp-microvolt = <800000>;
248 opp-hz = /bits/ 64 <1008000000>;
249 opp-microvolt = <850000>;
252 opp-hz = /bits/ 64 <1200000000>;
253 opp-microvolt = <925000>;
258 compatible = "arm,armv8-timer";
259 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
260 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
261 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
262 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
266 compatible = "arm,cortex-a53-pmu";
267 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &part0>;
271 compatible = "arm,cortex-a72-pmu";
272 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &part1>;
276 compatible = "fixed-clock";
278 clock-frequency = <24000000>;
279 clock-output-names = "xin24m";
283 compatible = "arm,amba-bus";
284 #address-cells = <2>;
288 dmac_bus: dma-controller@ff6d0000 {
289 compatible = "arm,pl330", "arm,primecell";
290 reg = <0x0 0xff6d0000 0x0 0x4000>;
291 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
292 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
294 clocks = <&cru ACLK_DMAC0_PERILP>;
295 clock-names = "apb_pclk";
296 peripherals-req-type-burst;
299 dmac_peri: dma-controller@ff6e0000 {
300 compatible = "arm,pl330", "arm,primecell";
301 reg = <0x0 0xff6e0000 0x0 0x4000>;
302 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
303 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>;
305 clocks = <&cru ACLK_DMAC1_PERILP>;
306 clock-names = "apb_pclk";
307 peripherals-req-type-burst;
312 compatible = "rockchip,rk3399-gmac";
313 reg = <0x0 0xfe300000 0x0 0x10000>;
314 rockchip,grf = <&grf>;
315 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
316 interrupt-names = "macirq";
317 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
318 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
319 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
321 clock-names = "stmmaceth", "mac_clk_rx",
322 "mac_clk_tx", "clk_mac_ref",
323 "clk_mac_refout", "aclk_mac",
325 resets = <&cru SRST_A_GMAC>;
326 reset-names = "stmmaceth";
327 power-domains = <&power RK3399_PD_GMAC>;
331 sdio0: dwmmc@fe310000 {
332 compatible = "rockchip,rk3399-dw-mshc",
333 "rockchip,rk3288-dw-mshc";
334 reg = <0x0 0xfe310000 0x0 0x4000>;
335 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>;
336 clock-freq-min-max = <400000 150000000>;
337 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
338 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
339 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
340 fifo-depth = <0x100>;
341 power-domains = <&power RK3399_PD_SDIOAUDIO>;
345 sdmmc: dwmmc@fe320000 {
346 compatible = "rockchip,rk3399-dw-mshc",
347 "rockchip,rk3288-dw-mshc";
348 reg = <0x0 0xfe320000 0x0 0x4000>;
349 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
350 clock-freq-min-max = <400000 150000000>;
351 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
352 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
353 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
354 fifo-depth = <0x100>;
355 power-domains = <&power RK3399_PD_SD>;
359 sdhci: sdhci@fe330000 {
360 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
361 reg = <0x0 0xfe330000 0x0 0x10000>;
362 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
363 arasan,soc-ctl-syscon = <&grf>;
364 assigned-clocks = <&cru SCLK_EMMC>;
365 assigned-clock-rates = <200000000>;
366 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
367 clock-names = "clk_xin", "clk_ahb";
368 clock-output-names = "emmc_cardclock";
371 phy-names = "phy_arasan";
372 power-domains = <&power RK3399_PD_EMMC>;
376 usb_host0_ehci: usb@fe380000 {
377 compatible = "generic-ehci";
378 reg = <0x0 0xfe380000 0x0 0x20000>;
379 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
380 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
381 <&cru SCLK_USBPHY0_480M_SRC>;
382 clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m";
383 phys = <&u2phy0_host>;
385 power-domains = <&power RK3399_PD_PERIHP>;
389 usb_host0_ohci: usb@fe3a0000 {
390 compatible = "generic-ohci";
391 reg = <0x0 0xfe3a0000 0x0 0x20000>;
392 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
393 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
394 <&cru SCLK_USBPHY0_480M_SRC>;
395 clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m";
396 phys = <&u2phy0_host>;
398 power-domains = <&power RK3399_PD_PERIHP>;
402 usb_host1_ehci: usb@fe3c0000 {
403 compatible = "generic-ehci";
404 reg = <0x0 0xfe3c0000 0x0 0x20000>;
405 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
406 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
407 <&cru SCLK_USBPHY1_480M_SRC>;
408 clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m";
409 phys = <&u2phy1_host>;
411 power-domains = <&power RK3399_PD_PERIHP>;
415 usb_host1_ohci: usb@fe3e0000 {
416 compatible = "generic-ohci";
417 reg = <0x0 0xfe3e0000 0x0 0x20000>;
418 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
419 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
420 <&cru SCLK_USBPHY1_480M_SRC>;
421 clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m";
422 phys = <&u2phy1_host>;
424 power-domains = <&power RK3399_PD_PERIHP>;
428 usbdrd3_0: usb@fe800000 {
429 compatible = "rockchip,rk3399-dwc3";
430 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
431 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_GRF>;
432 clock-names = "ref_clk", "suspend_clk",
433 "bus_clk", "grf_clk";
434 power-domains = <&power RK3399_PD_USB3>;
435 resets = <&cru SRST_A_USB3_OTG0>;
436 reset-names = "usb3-otg";
437 #address-cells = <2>;
441 usbdrd_dwc3_0: dwc3@fe800000 {
442 compatible = "snps,dwc3";
443 reg = <0x0 0xfe800000 0x0 0x100000>;
444 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
446 phys = <&u2phy0_otg>, <&tcphy0 1>;
447 phy-names = "usb2-phy", "usb3-phy";
448 phy_type = "utmi_wide";
449 snps,dis_enblslpm_quirk;
450 snps,dis-u2-freeclk-exists-quirk;
451 snps,dis-del-phy-power-chg-quirk;
452 snps,xhci-slow-suspend-quirk;
457 usbdrd3_1: usb@fe900000 {
458 compatible = "rockchip,rk3399-dwc3";
459 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
460 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_GRF>;
461 clock-names = "ref_clk", "suspend_clk",
462 "bus_clk", "grf_clk";
463 power-domains = <&power RK3399_PD_USB3>;
464 resets = <&cru SRST_A_USB3_OTG1>;
465 reset-names = "usb3-otg";
466 #address-cells = <2>;
470 usbdrd_dwc3_1: dwc3@fe900000 {
471 compatible = "snps,dwc3";
472 reg = <0x0 0xfe900000 0x0 0x100000>;
473 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
475 phys = <&u2phy1_otg>, <&tcphy1 1>;
476 phy-names = "usb2-phy", "usb3-phy";
477 phy_type = "utmi_wide";
478 snps,dis_enblslpm_quirk;
479 snps,dis-u2-freeclk-exists-quirk;
480 snps,dis-del-phy-power-chg-quirk;
481 snps,xhci-slow-suspend-quirk;
486 gic: interrupt-controller@fee00000 {
487 compatible = "arm,gic-v3";
488 #interrupt-cells = <4>;
489 #address-cells = <2>;
492 interrupt-controller;
494 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
495 <0x0 0xfef00000 0 0xc0000>, /* GICR */
496 <0x0 0xfff00000 0 0x10000>, /* GICC */
497 <0x0 0xfff10000 0 0x10000>, /* GICH */
498 <0x0 0xfff20000 0 0x10000>; /* GICV */
499 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
500 its: interrupt-controller@fee20000 {
501 compatible = "arm,gic-v3-its";
503 reg = <0x0 0xfee20000 0x0 0x20000>;
507 part0: interrupt-partition-0 {
508 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
511 part1: interrupt-partition-1 {
512 affinity = <&cpu_b0 &cpu_b1>;
517 saradc: saradc@ff100000 {
518 compatible = "rockchip,rk3399-saradc";
519 reg = <0x0 0xff100000 0x0 0x100>;
520 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>;
521 #io-channel-cells = <1>;
522 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
523 clock-names = "saradc", "apb_pclk";
528 compatible = "rockchip,rk3399-i2c";
529 reg = <0x0 0xff3c0000 0x0 0x1000>;
530 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
531 clock-names = "i2c", "pclk";
532 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
533 pinctrl-names = "default";
534 pinctrl-0 = <&i2c0_xfer>;
535 #address-cells = <1>;
541 compatible = "rockchip,rk3399-i2c";
542 reg = <0x0 0xff110000 0x0 0x1000>;
543 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
544 clock-names = "i2c", "pclk";
545 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>;
546 pinctrl-names = "default";
547 pinctrl-0 = <&i2c1_xfer>;
548 #address-cells = <1>;
554 compatible = "rockchip,rk3399-i2c";
555 reg = <0x0 0xff120000 0x0 0x1000>;
556 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
557 clock-names = "i2c", "pclk";
558 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>;
559 pinctrl-names = "default";
560 pinctrl-0 = <&i2c2_xfer>;
561 #address-cells = <1>;
567 compatible = "rockchip,rk3399-i2c";
568 reg = <0x0 0xff130000 0x0 0x1000>;
569 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
570 clock-names = "i2c", "pclk";
571 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>;
572 pinctrl-names = "default";
573 pinctrl-0 = <&i2c3_xfer>;
574 #address-cells = <1>;
580 compatible = "rockchip,rk3399-i2c";
581 reg = <0x0 0xff140000 0x0 0x1000>;
582 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
583 clock-names = "i2c", "pclk";
584 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>;
585 pinctrl-names = "default";
586 pinctrl-0 = <&i2c5_xfer>;
587 #address-cells = <1>;
593 compatible = "rockchip,rk3399-i2c";
594 reg = <0x0 0xff150000 0x0 0x1000>;
595 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
596 clock-names = "i2c", "pclk";
597 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>;
598 pinctrl-names = "default";
599 pinctrl-0 = <&i2c6_xfer>;
600 #address-cells = <1>;
606 compatible = "rockchip,rk3399-i2c";
607 reg = <0x0 0xff160000 0x0 0x1000>;
608 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
609 clock-names = "i2c", "pclk";
610 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>;
611 pinctrl-names = "default";
612 pinctrl-0 = <&i2c7_xfer>;
613 #address-cells = <1>;
618 uart0: serial@ff180000 {
619 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
620 reg = <0x0 0xff180000 0x0 0x100>;
621 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
622 clock-names = "baudclk", "apb_pclk";
623 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
626 pinctrl-names = "default";
627 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
631 uart1: serial@ff190000 {
632 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
633 reg = <0x0 0xff190000 0x0 0x100>;
634 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
635 clock-names = "baudclk", "apb_pclk";
636 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>;
639 pinctrl-names = "default";
640 pinctrl-0 = <&uart1_xfer>;
644 uart2: serial@ff1a0000 {
645 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
646 reg = <0x0 0xff1a0000 0x0 0x100>;
647 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
648 clock-names = "baudclk", "apb_pclk";
649 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
652 pinctrl-names = "default";
653 pinctrl-0 = <&uart2c_xfer>;
657 uart3: serial@ff1b0000 {
658 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
659 reg = <0x0 0xff1b0000 0x0 0x100>;
660 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
661 clock-names = "baudclk", "apb_pclk";
662 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
665 pinctrl-names = "default";
666 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
671 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
672 reg = <0x0 0xff1c0000 0x0 0x1000>;
673 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
674 clock-names = "spiclk", "apb_pclk";
675 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>;
676 pinctrl-names = "default";
677 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
678 #address-cells = <1>;
684 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
685 reg = <0x0 0xff1d0000 0x0 0x1000>;
686 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
687 clock-names = "spiclk", "apb_pclk";
688 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>;
689 pinctrl-names = "default";
690 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
691 #address-cells = <1>;
697 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
698 reg = <0x0 0xff1e0000 0x0 0x1000>;
699 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
700 clock-names = "spiclk", "apb_pclk";
701 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>;
702 pinctrl-names = "default";
703 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
704 #address-cells = <1>;
710 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
711 reg = <0x0 0xff1f0000 0x0 0x1000>;
712 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
713 clock-names = "spiclk", "apb_pclk";
714 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>;
715 pinctrl-names = "default";
716 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
717 #address-cells = <1>;
723 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
724 reg = <0x0 0xff200000 0x0 0x1000>;
725 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
726 clock-names = "spiclk", "apb_pclk";
727 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
728 pinctrl-names = "default";
729 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
730 #address-cells = <1>;
736 soc_thermal: soc-thermal {
737 polling-delay-passive = <20>; /* milliseconds */
738 polling-delay = <1000>; /* milliseconds */
739 sustainable-power = <1000>; /* milliwatts */
741 thermal-sensors = <&tsadc 0>;
744 threshold: trip-point@0 {
745 temperature = <70000>; /* millicelsius */
746 hysteresis = <2000>; /* millicelsius */
749 target: trip-point@1 {
750 temperature = <85000>; /* millicelsius */
751 hysteresis = <2000>; /* millicelsius */
755 temperature = <95000>; /* millicelsius */
756 hysteresis = <2000>; /* millicelsius */
765 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
766 contribution = <4096>;
771 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
772 contribution = <1024>;
777 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
778 contribution = <4096>;
783 gpu_thermal: gpu-thermal {
784 polling-delay-passive = <100>; /* milliseconds */
785 polling-delay = <1000>; /* milliseconds */
787 thermal-sensors = <&tsadc 1>;
791 tsadc: tsadc@ff260000 {
792 compatible = "rockchip,rk3399-tsadc";
793 reg = <0x0 0xff260000 0x0 0x100>;
794 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
795 rockchip,grf = <&grf>;
796 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
797 clock-names = "tsadc", "apb_pclk";
798 assigned-clocks = <&cru SCLK_TSADC>;
799 assigned-clock-rates = <750000>;
800 resets = <&cru SRST_TSADC>;
801 reset-names = "tsadc-apb";
802 pinctrl-names = "init", "default", "sleep";
803 pinctrl-0 = <&otp_gpio>;
804 pinctrl-1 = <&otp_out>;
805 pinctrl-2 = <&otp_gpio>;
806 #thermal-sensor-cells = <1>;
807 rockchip,hw-tshut-temp = <95000>;
811 qos_emmc: qos@ffa58000 {
812 compatible = "syscon";
813 reg = <0x0 0xffa58000 0x0 0x20>;
816 qos_gmac: qos@ffa5c000 {
817 compatible = "syscon";
818 reg = <0x0 0xffa5c000 0x0 0x20>;
821 qos_pcie: qos@ffa60080 {
822 compatible = "syscon";
823 reg = <0x0 0xffa60080 0x0 0x20>;
826 qos_usb_host0: qos@ffa60100 {
827 compatible = "syscon";
828 reg = <0x0 0xffa60100 0x0 0x20>;
831 qos_usb_host1: qos@ffa60180 {
832 compatible = "syscon";
833 reg = <0x0 0xffa60180 0x0 0x20>;
836 qos_usb_otg0: qos@ffa70000 {
837 compatible = "syscon";
838 reg = <0x0 0xffa70000 0x0 0x20>;
841 qos_usb_otg1: qos@ffa70080 {
842 compatible = "syscon";
843 reg = <0x0 0xffa70080 0x0 0x20>;
846 qos_sd: qos@ffa74000 {
847 compatible = "syscon";
848 reg = <0x0 0xffa74000 0x0 0x20>;
851 qos_sdioaudio: qos@ffa76000 {
852 compatible = "syscon";
853 reg = <0x0 0xffa76000 0x0 0x20>;
856 qos_hdcp: qos@ffa90000 {
857 compatible = "syscon";
858 reg = <0x0 0xffa90000 0x0 0x20>;
861 qos_iep: qos@ffa98000 {
862 compatible = "syscon";
863 reg = <0x0 0xffa98000 0x0 0x20>;
866 qos_isp0_m0: qos@ffaa0000 {
867 compatible = "syscon";
868 reg = <0x0 0xffaa0000 0x0 0x20>;
871 qos_isp0_m1: qos@ffaa0080 {
872 compatible = "syscon";
873 reg = <0x0 0xffaa0080 0x0 0x20>;
876 qos_isp1_m0: qos@ffaa8000 {
877 compatible = "syscon";
878 reg = <0x0 0xffaa8000 0x0 0x20>;
881 qos_isp1_m1: qos@ffaa8080 {
882 compatible = "syscon";
883 reg = <0x0 0xffaa8080 0x0 0x20>;
886 qos_rga_r: qos@ffab0000 {
887 compatible = "syscon";
888 reg = <0x0 0xffab0000 0x0 0x20>;
891 qos_rga_w: qos@ffab0080 {
892 compatible = "syscon";
893 reg = <0x0 0xffab0080 0x0 0x20>;
896 qos_video_m0: qos@ffab8000 {
897 compatible = "syscon";
898 reg = <0x0 0xffab8000 0x0 0x20>;
901 qos_video_m1_r: qos@ffac0000 {
902 compatible = "syscon";
903 reg = <0x0 0xffac0000 0x0 0x20>;
906 qos_video_m1_w: qos@ffac0080 {
907 compatible = "syscon";
908 reg = <0x0 0xffac0080 0x0 0x20>;
911 qos_vop_big_r: qos@ffac8000 {
912 compatible = "syscon";
913 reg = <0x0 0xffac8000 0x0 0x20>;
916 qos_vop_big_w: qos@ffac8080 {
917 compatible = "syscon";
918 reg = <0x0 0xffac8080 0x0 0x20>;
921 qos_vop_little: qos@ffad0000 {
922 compatible = "syscon";
923 reg = <0x0 0xffad0000 0x0 0x20>;
926 qos_perihp: qos@ffad8080 {
927 compatible = "syscon";
928 reg = <0x0 0xffad8080 0x0 0x20>;
931 qos_gpu: qos@ffae0000 {
932 compatible = "syscon";
933 reg = <0x0 0xffae0000 0x0 0x20>;
936 pmu: power-management@ff310000 {
937 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
938 reg = <0x0 0xff310000 0x0 0x1000>;
941 * Note: RK3399 supports 6 voltage domains including VD_CORE_L,
942 * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
943 * Some of the power domains are grouped together for every
945 * The detail contents as below.
947 power: power-controller {
948 compatible = "rockchip,rk3399-power-controller";
949 #power-domain-cells = <1>;
950 #address-cells = <1>;
953 /* These power domains are grouped by VD_CENTER */
954 pd_iep@RK3399_PD_IEP {
955 reg = <RK3399_PD_IEP>;
956 clocks = <&cru ACLK_IEP>,
960 pd_rga@RK3399_PD_RGA {
961 reg = <RK3399_PD_RGA>;
962 clocks = <&cru ACLK_RGA>,
964 pm_qos = <&qos_rga_r>,
967 pd_vcodec@RK3399_PD_VCODEC {
968 reg = <RK3399_PD_VCODEC>;
969 clocks = <&cru ACLK_VCODEC>,
971 pm_qos = <&qos_video_m0>;
973 pd_vdu@RK3399_PD_VDU {
974 reg = <RK3399_PD_VDU>;
975 clocks = <&cru ACLK_VDU>,
977 pm_qos = <&qos_video_m1_r>,
981 /* These power domains are grouped by VD_GPU */
982 pd_gpu@RK3399_PD_GPU {
983 reg = <RK3399_PD_GPU>;
984 clocks = <&cru ACLK_GPU>;
988 /* These power domains are grouped by VD_LOGIC */
989 pd_edp@RK3399_PD_EDP {
990 reg = <RK3399_PD_EDP>;
991 clocks = <&cru PCLK_EDP_CTRL>;
993 pd_emmc@RK3399_PD_EMMC {
994 reg = <RK3399_PD_EMMC>;
995 clocks = <&cru ACLK_EMMC>;
996 pm_qos = <&qos_emmc>;
998 pd_gmac@RK3399_PD_GMAC {
999 reg = <RK3399_PD_GMAC>;
1000 clocks = <&cru ACLK_GMAC>;
1001 pm_qos = <&qos_gmac>;
1003 pd_perihp@RK3399_PD_PERIHP {
1004 reg = <RK3399_PD_PERIHP>;
1005 #address-cells = <1>;
1007 clocks = <&cru ACLK_PERIHP>;
1008 pm_qos = <&qos_perihp>,
1013 pd_sd@RK3399_PD_SD {
1014 reg = <RK3399_PD_SD>;
1015 clocks = <&cru HCLK_SDMMC>,
1020 pd_sdioaudio@RK3399_PD_SDIOAUDIO {
1021 reg = <RK3399_PD_SDIOAUDIO>;
1022 clocks = <&cru HCLK_SDIO>;
1023 pm_qos = <&qos_sdioaudio>;
1025 pd_usb3@RK3399_PD_USB3 {
1026 reg = <RK3399_PD_USB3>;
1027 clocks = <&cru ACLK_USB3>;
1028 pm_qos = <&qos_usb_otg0>,
1031 pd_vio@RK3399_PD_VIO {
1032 reg = <RK3399_PD_VIO>;
1033 #address-cells = <1>;
1036 pd_hdcp@RK3399_PD_HDCP {
1037 reg = <RK3399_PD_HDCP>;
1038 clocks = <&cru ACLK_HDCP>,
1041 pm_qos = <&qos_hdcp>;
1043 pd_isp0@RK3399_PD_ISP0 {
1044 reg = <RK3399_PD_ISP0>;
1045 clocks = <&cru ACLK_ISP0>,
1047 pm_qos = <&qos_isp0_m0>,
1050 pd_isp1@RK3399_PD_ISP1 {
1051 reg = <RK3399_PD_ISP1>;
1052 clocks = <&cru ACLK_ISP1>,
1054 pm_qos = <&qos_isp1_m0>,
1057 pd_vo@RK3399_PD_VO {
1058 reg = <RK3399_PD_VO>;
1059 #address-cells = <1>;
1062 pd_vopb@RK3399_PD_VOPB {
1063 reg = <RK3399_PD_VOPB>;
1064 clocks = <&cru ACLK_VOP0>,
1066 pm_qos = <&qos_vop_big_r>,
1069 pd_vopl@RK3399_PD_VOPL {
1070 reg = <RK3399_PD_VOPL>;
1071 clocks = <&cru ACLK_VOP1>,
1073 pm_qos = <&qos_vop_little>;
1080 pmugrf: syscon@ff320000 {
1081 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
1082 reg = <0x0 0xff320000 0x0 0x1000>;
1085 compatible = "syscon-reboot-mode";
1087 mode-bootloader = <BOOT_LOADER>;
1088 mode-charge = <BOOT_CHARGING>;
1089 mode-fastboot = <BOOT_FASTBOOT>;
1090 mode-loader = <BOOT_LOADER>;
1091 mode-normal = <BOOT_NORMAL>;
1092 mode-recovery = <BOOT_RECOVERY>;
1093 mode-ums = <BOOT_UMS>;
1097 spi3: spi@ff350000 {
1098 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
1099 reg = <0x0 0xff350000 0x0 0x1000>;
1100 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
1101 clock-names = "spiclk", "apb_pclk";
1102 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>;
1103 pinctrl-names = "default";
1104 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
1105 #address-cells = <1>;
1107 status = "disabled";
1110 uart4: serial@ff370000 {
1111 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
1112 reg = <0x0 0xff370000 0x0 0x100>;
1113 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
1114 clock-names = "baudclk", "apb_pclk";
1115 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>;
1118 pinctrl-names = "default";
1119 pinctrl-0 = <&uart4_xfer>;
1120 status = "disabled";
1123 i2c4: i2c@ff3d0000 {
1124 compatible = "rockchip,rk3399-i2c";
1125 reg = <0x0 0xff3d0000 0x0 0x1000>;
1126 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
1127 clock-names = "i2c", "pclk";
1128 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>;
1129 pinctrl-names = "default";
1130 pinctrl-0 = <&i2c4_xfer>;
1131 #address-cells = <1>;
1133 status = "disabled";
1136 i2c8: i2c@ff3e0000 {
1137 compatible = "rockchip,rk3399-i2c";
1138 reg = <0x0 0xff3e0000 0x0 0x1000>;
1139 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
1140 clock-names = "i2c", "pclk";
1141 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
1142 pinctrl-names = "default";
1143 pinctrl-0 = <&i2c8_xfer>;
1144 #address-cells = <1>;
1146 status = "disabled";
1149 pcie_phy: phy@e220 {
1150 compatible = "rockchip,rk3399-pcie-phy";
1152 rockchip,grf = <&grf>;
1153 clocks = <&cru SCLK_PCIEPHY_REF>;
1154 clock-names = "refclk";
1155 resets = <&cru SRST_PCIEPHY>;
1156 reset-names = "phy";
1157 status = "disabled";
1160 pcie0: pcie@f8000000 {
1161 compatible = "rockchip,rk3399-pcie";
1162 #address-cells = <3>;
1164 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
1165 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
1166 clock-names = "aclk", "aclk-perf",
1168 bus-range = <0x0 0x1>;
1169 msi-map = <0x0 &its 0x0 0x1000>;
1170 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
1171 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
1172 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
1173 interrupt-names = "sys", "legacy", "client";
1174 #interrupt-cells = <1>;
1175 interrupt-map-mask = <0 0 0 7>;
1176 interrupt-map = <0 0 0 1 &pcie0_intc 0>,
1177 <0 0 0 2 &pcie0_intc 1>,
1178 <0 0 0 3 &pcie0_intc 2>,
1179 <0 0 0 4 &pcie0_intc 3>;
1181 phy-names = "pcie-phy";
1182 ranges = <0x82000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000
1183 0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>;
1184 reg = <0x0 0xf8000000 0x0 0x2000000>,
1185 <0x0 0xfd000000 0x0 0x1000000>;
1186 reg-names = "axi-base", "apb-base";
1187 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
1188 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>;
1189 reset-names = "core", "mgmt", "mgmt-sticky", "pipe";
1190 status = "disabled";
1191 pcie0_intc: interrupt-controller {
1192 interrupt-controller;
1193 #address-cells = <0>;
1194 #interrupt-cells = <1>;
1198 pwm0: pwm@ff420000 {
1199 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1200 reg = <0x0 0xff420000 0x0 0x10>;
1202 pinctrl-names = "default";
1203 pinctrl-0 = <&pwm0_pin>;
1204 clocks = <&pmucru PCLK_RKPWM_PMU>;
1205 clock-names = "pwm";
1206 status = "disabled";
1209 pwm1: pwm@ff420010 {
1210 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1211 reg = <0x0 0xff420010 0x0 0x10>;
1213 pinctrl-names = "default";
1214 pinctrl-0 = <&pwm1_pin>;
1215 clocks = <&pmucru PCLK_RKPWM_PMU>;
1216 clock-names = "pwm";
1217 status = "disabled";
1220 pwm2: pwm@ff420020 {
1221 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1222 reg = <0x0 0xff420020 0x0 0x10>;
1224 pinctrl-names = "default";
1225 pinctrl-0 = <&pwm2_pin>;
1226 clocks = <&pmucru PCLK_RKPWM_PMU>;
1227 clock-names = "pwm";
1228 status = "disabled";
1231 pwm3: pwm@ff420030 {
1232 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1233 reg = <0x0 0xff420030 0x0 0x10>;
1235 pinctrl-names = "default";
1236 pinctrl-0 = <&pwm3a_pin>;
1237 clocks = <&pmucru PCLK_RKPWM_PMU>;
1238 clock-names = "pwm";
1239 status = "disabled";
1243 reg = <0x00 0xff630000 0x00 0x4000>;
1244 compatible = "rockchip,rk3399-dfi";
1245 rockchip,pmu = <&pmugrf>;
1246 clocks = <&cru PCLK_DDR_MON>;
1247 clock-names = "pclk_ddr_mon";
1248 status = "disabled";
1252 compatible = "rockchip,rk3399-dmc";
1253 devfreq-events = <&dfi>;
1254 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>;
1255 clocks = <&cru SCLK_DDRCLK>;
1256 clock-names = "dmc_clk";
1257 ddr_timing = <&ddr_timing>;
1258 operating-points-v2 = <&dmc_opp_table>;
1259 status = "disabled";
1262 dmc_opp_table: dmc_opp_table {
1263 compatible = "operating-points-v2";
1266 opp-hz = /bits/ 64 <666000000>;
1267 opp-microvolt = <900000>;
1272 compatible = "rockchip,rk3399-rga";
1273 reg = <0x0 0xff680000 0x0 0x10000>;
1274 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
1275 interrupt-names = "rga";
1276 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
1277 clock-names = "aclk", "hclk", "sclk";
1278 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
1279 reset-names = "core", "axi", "ahb";
1280 power-domains = <&power RK3399_PD_RGA>;
1281 status = "disabled";
1284 efuse0: efuse@ff690000 {
1285 compatible = "rockchip,rk3399-efuse";
1286 reg = <0x0 0xff690000 0x0 0x80>;
1287 #address-cells = <1>;
1289 clocks = <&cru PCLK_EFUSE1024NS>;
1290 clock-names = "pclk_efuse";
1293 cpul_leakage: cpul-leakage {
1296 cpub_leakage: cpub-leakage {
1299 gpu_leakage: gpu-leakage {
1302 center_leakage: center-leakage {
1305 logic_leakage: logic-leakage {
1308 wafer_info: wafer-info {
1313 pmucru: pmu-clock-controller@ff750000 {
1314 compatible = "rockchip,rk3399-pmucru";
1315 reg = <0x0 0xff750000 0x0 0x1000>;
1318 assigned-clocks = <&pmucru PLL_PPLL>;
1319 assigned-clock-rates = <676000000>;
1322 cru: clock-controller@ff760000 {
1323 compatible = "rockchip,rk3399-cru";
1324 reg = <0x0 0xff760000 0x0 0x1000>;
1328 <&cru ACLK_VOP0>, <&cru HCLK_VOP0>,
1329 <&cru ACLK_VOP1>, <&cru HCLK_VOP1>,
1330 <&cru ARMCLKL>, <&cru ARMCLKB>,
1331 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1333 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1335 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1336 <&cru PCLK_PERILP0>,
1337 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
1338 assigned-clock-rates =
1339 <400000000>, <200000000>,
1340 <400000000>, <200000000>,
1341 <816000000>, <816000000>,
1342 <594000000>, <800000000>,
1344 <150000000>, <75000000>,
1346 <100000000>, <100000000>,
1348 <100000000>, <50000000>;
1351 grf: syscon@ff770000 {
1352 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
1353 reg = <0x0 0xff770000 0x0 0x10000>;
1354 #address-cells = <1>;
1357 emmc_phy: phy@f780 {
1358 compatible = "rockchip,rk3399-emmc-phy";
1359 reg = <0xf780 0x24>;
1361 clock-names = "emmcclk";
1363 status = "disabled";
1366 u2phy0: usb2-phy@e450 {
1367 compatible = "rockchip,rk3399-usb2phy";
1368 reg = <0xe450 0x10>;
1369 clocks = <&cru SCLK_USB2PHY0_REF>;
1370 clock-names = "phyclk";
1372 clock-output-names = "clk_usbphy0_480m";
1373 status = "disabled";
1375 u2phy0_otg: otg-port {
1377 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
1378 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
1379 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
1380 interrupt-names = "otg-bvalid", "otg-id",
1382 status = "disabled";
1385 u2phy0_host: host-port {
1387 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
1388 interrupt-names = "linestate";
1389 status = "disabled";
1393 u2phy1: usb2-phy@e460 {
1394 compatible = "rockchip,rk3399-usb2phy";
1395 reg = <0xe460 0x10>;
1396 clocks = <&cru SCLK_USB2PHY1_REF>;
1397 clock-names = "phyclk";
1399 clock-output-names = "clk_usbphy1_480m";
1400 status = "disabled";
1402 u2phy1_otg: otg-port {
1404 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
1405 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
1406 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1407 interrupt-names = "otg-bvalid", "otg-id",
1409 status = "disabled";
1412 u2phy1_host: host-port {
1414 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
1415 interrupt-names = "linestate";
1416 status = "disabled";
1421 tcphy0: phy@ff7c0000 {
1422 compatible = "rockchip,rk3399-typec-phy";
1423 reg = <0x0 0xff7c0000 0x0 0x40000>;
1424 rockchip,grf = <&grf>;
1426 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1427 <&cru SCLK_UPHY0_TCPDPHY_REF>;
1428 clock-names = "tcpdcore", "tcpdphy-ref";
1429 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
1430 assigned-clock-rates = <50000000>;
1431 resets = <&cru SRST_UPHY0>,
1432 <&cru SRST_UPHY0_PIPE_L00>,
1433 <&cru SRST_P_UPHY0_TCPHY>;
1434 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1435 rockchip,typec-conn-dir = <0xe580 0 16>;
1436 rockchip,usb3tousb2-en = <0xe580 3 19>;
1437 rockchip,external-psm = <0xe588 14 30>;
1438 rockchip,pipe-status = <0xe5c0 0 0>;
1439 rockchip,uphy-dp-sel = <0x6268 19 19>;
1440 status = "disabled";
1443 tcphy1: phy@ff800000 {
1444 compatible = "rockchip,rk3399-typec-phy";
1445 reg = <0x0 0xff800000 0x0 0x40000>;
1446 rockchip,grf = <&grf>;
1448 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1449 <&cru SCLK_UPHY1_TCPDPHY_REF>;
1450 clock-names = "tcpdcore", "tcpdphy-ref";
1451 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
1452 assigned-clock-rates = <50000000>;
1453 resets = <&cru SRST_UPHY1>,
1454 <&cru SRST_UPHY1_PIPE_L00>,
1455 <&cru SRST_P_UPHY1_TCPHY>;
1456 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1457 rockchip,typec-conn-dir = <0xe58c 0 16>;
1458 rockchip,usb3tousb2-en = <0xe58c 3 19>;
1459 rockchip,external-psm = <0xe594 14 30>;
1460 rockchip,pipe-status = <0xe5c0 16 16>;
1461 rockchip,uphy-dp-sel = <0x6268 3 19>;
1462 status = "disabled";
1466 compatible = "snps,dw-wdt";
1467 reg = <0x0 0xff848000 0x0 0x100>;
1468 clocks = <&cru PCLK_WDT>;
1469 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
1472 rktimer: rktimer@ff850000 {
1473 compatible = "rockchip,rk3399-timer";
1474 reg = <0x0 0xff850000 0x0 0x1000>;
1475 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
1476 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1477 clock-names = "pclk", "timer";
1480 spdif: spdif@ff870000 {
1481 compatible = "rockchip,rk3399-spdif";
1482 reg = <0x0 0xff870000 0x0 0x1000>;
1483 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
1484 dmas = <&dmac_bus 7>;
1486 clock-names = "mclk", "hclk";
1487 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1488 pinctrl-names = "default";
1489 pinctrl-0 = <&spdif_bus>;
1490 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1491 status = "disabled";
1494 i2s0: i2s@ff880000 {
1495 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1496 reg = <0x0 0xff880000 0x0 0x1000>;
1497 rockchip,grf = <&grf>;
1498 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>;
1499 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1500 dma-names = "tx", "rx";
1501 clock-names = "i2s_clk", "i2s_hclk";
1502 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1503 pinctrl-names = "default";
1504 pinctrl-0 = <&i2s0_8ch_bus>;
1505 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1506 status = "disabled";
1509 i2s1: i2s@ff890000 {
1510 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1511 reg = <0x0 0xff890000 0x0 0x1000>;
1512 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>;
1513 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1514 dma-names = "tx", "rx";
1515 clock-names = "i2s_clk", "i2s_hclk";
1516 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1517 pinctrl-names = "default";
1518 pinctrl-0 = <&i2s1_2ch_bus>;
1519 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1520 status = "disabled";
1523 i2s2: i2s@ff8a0000 {
1524 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1525 reg = <0x0 0xff8a0000 0x0 0x1000>;
1526 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>;
1527 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1528 dma-names = "tx", "rx";
1529 clock-names = "i2s_clk", "i2s_hclk";
1530 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1531 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1532 status = "disabled";
1536 compatible = "arm,malit860",
1541 reg = <0x0 0xff9a0000 0x0 0x10000>;
1543 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>,
1544 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
1545 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>;
1546 interrupt-names = "GPU", "JOB", "MMU";
1548 clocks = <&cru ACLK_GPU>;
1549 clock-names = "clk_mali";
1550 #cooling-cells = <2>; /* min followed by max */
1551 operating-points-v2 = <&gpu_opp_table>;
1552 power-domains = <&power RK3399_PD_GPU>;
1553 power-off-delay-ms = <200>;
1554 status = "disabled";
1556 gpu_power_model: power_model {
1557 compatible = "arm,mali-simple-power-model";
1560 static-power = <300>;
1561 dynamic-power = <396>;
1562 ts = <32000 4700 (-80) 2>;
1563 thermal-zone = "gpu-thermal";
1567 gpu_opp_table: gpu_opp_table {
1568 compatible = "operating-points-v2";
1572 opp-hz = /bits/ 64 <200000000>;
1573 opp-microvolt = <900000>;
1576 opp-hz = /bits/ 64 <300000000>;
1577 opp-microvolt = <900000>;
1580 opp-hz = /bits/ 64 <400000000>;
1581 opp-microvolt = <900000>;
1586 vopl: vop@ff8f0000 {
1587 compatible = "rockchip,rk3399-vop-lit";
1588 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1589 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1590 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1591 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1592 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1593 reset-names = "axi", "ahb", "dclk";
1594 power-domains = <&power RK3399_PD_VOPL>;
1595 iommus = <&vopl_mmu>;
1596 status = "disabled";
1599 #address-cells = <1>;
1602 vopl_out_mipi: endpoint@0 {
1604 remote-endpoint = <&mipi_in_vopl>;
1607 vopl_out_edp: endpoint@1 {
1609 remote-endpoint = <&edp_in_vopl>;
1612 vopl_out_hdmi: endpoint@2 {
1614 remote-endpoint = <&hdmi_in_vopl>;
1619 vop1_pwm: voppwm@ff8f01a0 {
1620 compatible = "rockchip,vop-pwm";
1621 reg = <0x0 0xff8f01a0 0x0 0x10>;
1623 pinctrl-names = "default";
1624 pinctrl-0 = <&vop1_pwm_pin>;
1625 clocks = <&cru SCLK_VOP1_PWM>;
1626 clock-names = "pwm";
1627 status = "disabled";
1630 vopl_mmu: iommu@ff8f3f00 {
1631 compatible = "rockchip,iommu";
1632 reg = <0x0 0xff8f3f00 0x0 0x100>;
1633 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1634 interrupt-names = "vopl_mmu";
1636 status = "disabled";
1639 vopb: vop@ff900000 {
1640 compatible = "rockchip,rk3399-vop-big";
1641 reg = <0x0 0xff900000 0x0 0x3efc>;
1642 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1643 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1644 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1645 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1646 reset-names = "axi", "ahb", "dclk";
1647 power-domains = <&power RK3399_PD_VOPB>;
1648 iommus = <&vopb_mmu>;
1649 status = "disabled";
1652 #address-cells = <1>;
1655 vopb_out_edp: endpoint@0 {
1657 remote-endpoint = <&edp_in_vopb>;
1660 vopb_out_mipi: endpoint@1 {
1662 remote-endpoint = <&mipi_in_vopb>;
1665 vopb_out_hdmi: endpoint@2 {
1667 remote-endpoint = <&hdmi_in_vopb>;
1672 vop0_pwm: voppwm@ff9001a0 {
1673 compatible = "rockchip,vop-pwm";
1674 reg = <0x0 0xff9001a0 0x0 0x10>;
1676 pinctrl-names = "default";
1677 pinctrl-0 = <&vop0_pwm_pin>;
1678 clocks = <&cru SCLK_VOP0_PWM>;
1679 clock-names = "pwm";
1680 status = "disabled";
1683 vopb_mmu: iommu@ff903f00 {
1684 compatible = "rockchip,iommu";
1685 reg = <0x0 0xff903f00 0x0 0x100>;
1686 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1687 interrupt-names = "vopb_mmu";
1689 status = "disabled";
1692 hdmi: hdmi@ff940000 {
1693 compatible = "rockchip,rk3399-dw-hdmi";
1694 reg = <0x0 0xff940000 0x0 0x20000>;
1696 rockchip,grf = <&grf>;
1697 power-domains = <&power RK3399_PD_HDCP>;
1698 pinctrl-names = "default";
1699 pinctrl-0 = <&hdmi_i2c_xfer>;
1700 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
1701 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_SFR>, <&cru SCLK_HDMI_SFR>, <&cru PCLK_EDP_CTRL>;
1702 clock-names = "iahb", "isfr", "vpll", "grf";
1703 status = "disabled";
1707 #address-cells = <1>;
1709 hdmi_in_vopb: endpoint@0 {
1711 remote-endpoint = <&vopb_out_hdmi>;
1713 hdmi_in_vopl: endpoint@1 {
1715 remote-endpoint = <&vopl_out_hdmi>;
1721 mipi_dsi: mipi@ff960000 {
1722 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1723 reg = <0x0 0xff960000 0x0 0x8000>;
1724 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
1725 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
1726 <&cru SCLK_DPHY_TX0_CFG>;
1727 clock-names = "ref", "pclk", "phy_cfg";
1728 power-domains = <&power RK3399_PD_VIO>;
1729 rockchip,grf = <&grf>;
1730 #address-cells = <1>;
1732 status = "disabled";
1735 #address-cells = <1>;
1740 #address-cells = <1>;
1743 mipi_in_vopb: endpoint@0 {
1745 remote-endpoint = <&vopb_out_mipi>;
1747 mipi_in_vopl: endpoint@1 {
1749 remote-endpoint = <&vopl_out_mipi>;
1756 compatible = "rockchip,rk3399-edp";
1757 reg = <0x0 0xff970000 0x0 0x8000>;
1758 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
1759 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1760 clock-names = "dp", "pclk";
1761 resets = <&cru SRST_P_EDP_CTRL>;
1763 rockchip,grf = <&grf>;
1764 status = "disabled";
1765 pinctrl-names = "default";
1766 pinctrl-0 = <&edp_hpd>;
1769 #address-cells = <1>;
1774 #address-cells = <1>;
1777 edp_in_vopb: endpoint@0 {
1779 remote-endpoint = <&vopb_out_edp>;
1782 edp_in_vopl: endpoint@1 {
1784 remote-endpoint = <&vopl_out_edp>;
1790 display_subsystem: display-subsystem {
1791 compatible = "rockchip,display-subsystem";
1792 ports = <&vopl_out>, <&vopb_out>;
1793 status = "disabled";
1797 compatible = "rockchip,rk3399-pinctrl";
1798 rockchip,grf = <&grf>;
1799 rockchip,pmu = <&pmugrf>;
1800 #address-cells = <0x2>;
1801 #size-cells = <0x2>;
1804 gpio0: gpio0@ff720000 {
1805 compatible = "rockchip,gpio-bank";
1806 reg = <0x0 0xff720000 0x0 0x100>;
1807 clocks = <&pmucru PCLK_GPIO0_PMU>;
1808 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
1811 #gpio-cells = <0x2>;
1813 interrupt-controller;
1814 #interrupt-cells = <0x2>;
1817 gpio1: gpio1@ff730000 {
1818 compatible = "rockchip,gpio-bank";
1819 reg = <0x0 0xff730000 0x0 0x100>;
1820 clocks = <&pmucru PCLK_GPIO1_PMU>;
1821 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
1824 #gpio-cells = <0x2>;
1826 interrupt-controller;
1827 #interrupt-cells = <0x2>;
1830 gpio2: gpio2@ff780000 {
1831 compatible = "rockchip,gpio-bank";
1832 reg = <0x0 0xff780000 0x0 0x100>;
1833 clocks = <&cru PCLK_GPIO2>;
1834 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>;
1837 #gpio-cells = <0x2>;
1839 interrupt-controller;
1840 #interrupt-cells = <0x2>;
1843 gpio3: gpio3@ff788000 {
1844 compatible = "rockchip,gpio-bank";
1845 reg = <0x0 0xff788000 0x0 0x100>;
1846 clocks = <&cru PCLK_GPIO3>;
1847 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
1850 #gpio-cells = <0x2>;
1852 interrupt-controller;
1853 #interrupt-cells = <0x2>;
1856 gpio4: gpio4@ff790000 {
1857 compatible = "rockchip,gpio-bank";
1858 reg = <0x0 0xff790000 0x0 0x100>;
1859 clocks = <&cru PCLK_GPIO4>;
1860 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
1863 #gpio-cells = <0x2>;
1865 interrupt-controller;
1866 #interrupt-cells = <0x2>;
1869 pcfg_pull_up: pcfg-pull-up {
1873 pcfg_pull_down: pcfg-pull-down {
1877 pcfg_pull_none: pcfg-pull-none {
1881 pcfg_pull_up_20ma: pcfg-pull-up-20ma {
1883 drive-strength = <20>;
1886 pcfg_pull_none_20ma: pcfg-pull-none-20ma {
1888 drive-strength = <20>;
1891 pcfg_pull_none_18ma: pcfg-pull-none-18ma {
1893 drive-strength = <18>;
1896 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1898 drive-strength = <12>;
1901 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1903 drive-strength = <8>;
1906 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1908 drive-strength = <4>;
1911 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1913 drive-strength = <2>;
1916 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
1918 drive-strength = <12>;
1921 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
1923 drive-strength = <13>;
1926 pcfg_output_high: pcfg-output-high {
1930 pcfg_output_low: pcfg-output-low {
1934 pcfg_input: pcfg-input {
1939 emmc_pwr: emmc-pwr {
1941 <0 5 RK_FUNC_1 &pcfg_pull_up>;
1946 rgmii_pins: rgmii-pins {
1949 <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
1951 <3 14 RK_FUNC_1 &pcfg_pull_none>,
1953 <3 13 RK_FUNC_1 &pcfg_pull_none>,
1955 <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1957 <3 11 RK_FUNC_1 &pcfg_pull_none>,
1959 <3 9 RK_FUNC_1 &pcfg_pull_none>,
1961 <3 8 RK_FUNC_1 &pcfg_pull_none>,
1963 <3 7 RK_FUNC_1 &pcfg_pull_none>,
1965 <3 6 RK_FUNC_1 &pcfg_pull_none>,
1967 <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1969 <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
1971 <3 3 RK_FUNC_1 &pcfg_pull_none>,
1973 <3 2 RK_FUNC_1 &pcfg_pull_none>,
1975 <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
1977 <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
1980 rmii_pins: rmii-pins {
1983 <3 13 RK_FUNC_1 &pcfg_pull_none>,
1985 <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1987 <3 11 RK_FUNC_1 &pcfg_pull_none>,
1989 <3 10 RK_FUNC_1 &pcfg_pull_none>,
1991 <3 9 RK_FUNC_1 &pcfg_pull_none>,
1993 <3 8 RK_FUNC_1 &pcfg_pull_none>,
1995 <3 7 RK_FUNC_1 &pcfg_pull_none>,
1997 <3 6 RK_FUNC_1 &pcfg_pull_none>,
1999 <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
2001 <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
2006 i2c0_xfer: i2c0-xfer {
2008 <1 15 RK_FUNC_2 &pcfg_pull_none>,
2009 <1 16 RK_FUNC_2 &pcfg_pull_none>;
2014 i2c1_xfer: i2c1-xfer {
2016 <4 2 RK_FUNC_1 &pcfg_pull_none>,
2017 <4 1 RK_FUNC_1 &pcfg_pull_none>;
2022 i2c2_xfer: i2c2-xfer {
2024 <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
2025 <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
2030 i2c3_xfer: i2c3-xfer {
2032 <4 17 RK_FUNC_1 &pcfg_pull_none>,
2033 <4 16 RK_FUNC_1 &pcfg_pull_none>;
2036 i2c3_gpio: i2c3_gpio {
2038 <4 17 RK_FUNC_GPIO &pcfg_pull_none>,
2039 <4 16 RK_FUNC_GPIO &pcfg_pull_none>;
2045 i2c4_xfer: i2c4-xfer {
2047 <1 12 RK_FUNC_1 &pcfg_pull_none>,
2048 <1 11 RK_FUNC_1 &pcfg_pull_none>;
2053 i2c5_xfer: i2c5-xfer {
2055 <3 11 RK_FUNC_2 &pcfg_pull_none>,
2056 <3 10 RK_FUNC_2 &pcfg_pull_none>;
2061 i2c6_xfer: i2c6-xfer {
2063 <2 10 RK_FUNC_2 &pcfg_pull_none>,
2064 <2 9 RK_FUNC_2 &pcfg_pull_none>;
2069 i2c7_xfer: i2c7-xfer {
2071 <2 8 RK_FUNC_2 &pcfg_pull_none>,
2072 <2 7 RK_FUNC_2 &pcfg_pull_none>;
2077 i2c8_xfer: i2c8-xfer {
2079 <1 21 RK_FUNC_1 &pcfg_pull_none>,
2080 <1 20 RK_FUNC_1 &pcfg_pull_none>;
2085 i2s0_8ch_bus: i2s0-8ch-bus {
2087 <3 24 RK_FUNC_1 &pcfg_pull_none>,
2088 <3 25 RK_FUNC_1 &pcfg_pull_none>,
2089 <3 26 RK_FUNC_1 &pcfg_pull_none>,
2090 <3 27 RK_FUNC_1 &pcfg_pull_none>,
2091 <3 28 RK_FUNC_1 &pcfg_pull_none>,
2092 <3 29 RK_FUNC_1 &pcfg_pull_none>,
2093 <3 30 RK_FUNC_1 &pcfg_pull_none>,
2094 <3 31 RK_FUNC_1 &pcfg_pull_none>,
2095 <4 0 RK_FUNC_1 &pcfg_pull_none>;
2100 i2s1_2ch_bus: i2s1-2ch-bus {
2102 <4 3 RK_FUNC_1 &pcfg_pull_none>,
2103 <4 4 RK_FUNC_1 &pcfg_pull_none>,
2104 <4 5 RK_FUNC_1 &pcfg_pull_none>,
2105 <4 6 RK_FUNC_1 &pcfg_pull_none>,
2106 <4 7 RK_FUNC_1 &pcfg_pull_none>;
2111 sdio0_bus1: sdio0-bus1 {
2113 <2 20 RK_FUNC_1 &pcfg_pull_up>;
2116 sdio0_bus4: sdio0-bus4 {
2118 <2 20 RK_FUNC_1 &pcfg_pull_up>,
2119 <2 21 RK_FUNC_1 &pcfg_pull_up>,
2120 <2 22 RK_FUNC_1 &pcfg_pull_up>,
2121 <2 23 RK_FUNC_1 &pcfg_pull_up>;
2124 sdio0_cmd: sdio0-cmd {
2126 <2 24 RK_FUNC_1 &pcfg_pull_up>;
2129 sdio0_clk: sdio0-clk {
2131 <2 25 RK_FUNC_1 &pcfg_pull_none>;
2134 sdio0_cd: sdio0-cd {
2136 <2 26 RK_FUNC_1 &pcfg_pull_up>;
2139 sdio0_pwr: sdio0-pwr {
2141 <2 27 RK_FUNC_1 &pcfg_pull_up>;
2144 sdio0_bkpwr: sdio0-bkpwr {
2146 <2 28 RK_FUNC_1 &pcfg_pull_up>;
2149 sdio0_wp: sdio0-wp {
2151 <0 3 RK_FUNC_1 &pcfg_pull_up>;
2154 sdio0_int: sdio0-int {
2156 <0 4 RK_FUNC_1 &pcfg_pull_up>;
2161 sdmmc_bus1: sdmmc-bus1 {
2163 <4 8 RK_FUNC_1 &pcfg_pull_up>;
2166 sdmmc_bus4: sdmmc-bus4 {
2168 <4 8 RK_FUNC_1 &pcfg_pull_up>,
2169 <4 9 RK_FUNC_1 &pcfg_pull_up>,
2170 <4 10 RK_FUNC_1 &pcfg_pull_up>,
2171 <4 11 RK_FUNC_1 &pcfg_pull_up>;
2174 sdmmc_clk: sdmmc-clk {
2176 <4 12 RK_FUNC_1 &pcfg_pull_none>;
2179 sdmmc_cmd: sdmmc-cmd {
2181 <4 13 RK_FUNC_1 &pcfg_pull_up>;
2184 sdmmc_cd: sdmcc-cd {
2186 <0 7 RK_FUNC_1 &pcfg_pull_up>;
2189 sdmmc_wp: sdmmc-wp {
2191 <0 8 RK_FUNC_1 &pcfg_pull_up>;
2196 spdif_bus: spdif-bus {
2198 <4 21 RK_FUNC_1 &pcfg_pull_none>;
2201 spdif_bus_1: spdif-bus-1 {
2203 <3 16 RK_FUNC_3 &pcfg_pull_none>;
2208 spi0_clk: spi0-clk {
2210 <3 6 RK_FUNC_2 &pcfg_pull_up>;
2212 spi0_cs0: spi0-cs0 {
2214 <3 7 RK_FUNC_2 &pcfg_pull_up>;
2216 spi0_cs1: spi0-cs1 {
2218 <3 8 RK_FUNC_2 &pcfg_pull_up>;
2222 <3 5 RK_FUNC_2 &pcfg_pull_up>;
2226 <3 4 RK_FUNC_2 &pcfg_pull_up>;
2231 spi1_clk: spi1-clk {
2233 <1 9 RK_FUNC_2 &pcfg_pull_up>;
2235 spi1_cs0: spi1-cs0 {
2237 <1 10 RK_FUNC_2 &pcfg_pull_up>;
2241 <1 7 RK_FUNC_2 &pcfg_pull_up>;
2245 <1 8 RK_FUNC_2 &pcfg_pull_up>;
2250 spi2_clk: spi2-clk {
2252 <2 11 RK_FUNC_1 &pcfg_pull_up>;
2254 spi2_cs0: spi2-cs0 {
2256 <2 12 RK_FUNC_1 &pcfg_pull_up>;
2260 <2 9 RK_FUNC_1 &pcfg_pull_up>;
2264 <2 10 RK_FUNC_1 &pcfg_pull_up>;
2269 spi3_clk: spi3-clk {
2271 <1 17 RK_FUNC_1 &pcfg_pull_up>;
2273 spi3_cs0: spi3-cs0 {
2275 <1 18 RK_FUNC_1 &pcfg_pull_up>;
2279 <1 15 RK_FUNC_1 &pcfg_pull_up>;
2283 <1 16 RK_FUNC_1 &pcfg_pull_up>;
2288 spi4_clk: spi4-clk {
2290 <3 2 RK_FUNC_2 &pcfg_pull_up>;
2292 spi4_cs0: spi4-cs0 {
2294 <3 3 RK_FUNC_2 &pcfg_pull_up>;
2298 <3 0 RK_FUNC_2 &pcfg_pull_up>;
2302 <3 1 RK_FUNC_2 &pcfg_pull_up>;
2307 spi5_clk: spi5-clk {
2309 <2 22 RK_FUNC_2 &pcfg_pull_up>;
2311 spi5_cs0: spi5-cs0 {
2313 <2 23 RK_FUNC_2 &pcfg_pull_up>;
2317 <2 20 RK_FUNC_2 &pcfg_pull_up>;
2321 <2 21 RK_FUNC_2 &pcfg_pull_up>;
2326 otp_gpio: otp-gpio {
2327 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
2331 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
2336 uart0_xfer: uart0-xfer {
2338 <2 16 RK_FUNC_1 &pcfg_pull_up>,
2339 <2 17 RK_FUNC_1 &pcfg_pull_none>;
2342 uart0_cts: uart0-cts {
2344 <2 18 RK_FUNC_1 &pcfg_pull_none>;
2347 uart0_rts: uart0-rts {
2349 <2 19 RK_FUNC_1 &pcfg_pull_none>;
2354 uart1_xfer: uart1-xfer {
2356 <3 12 RK_FUNC_2 &pcfg_pull_up>,
2357 <3 13 RK_FUNC_2 &pcfg_pull_none>;
2362 uart2a_xfer: uart2a-xfer {
2364 <4 8 RK_FUNC_2 &pcfg_pull_up>,
2365 <4 9 RK_FUNC_2 &pcfg_pull_none>;
2370 uart2b_xfer: uart2b-xfer {
2372 <4 16 RK_FUNC_2 &pcfg_pull_up>,
2373 <4 17 RK_FUNC_2 &pcfg_pull_none>;
2378 uart2c_xfer: uart2c-xfer {
2380 <4 19 RK_FUNC_1 &pcfg_pull_up>,
2381 <4 20 RK_FUNC_1 &pcfg_pull_none>;
2386 uart3_xfer: uart3-xfer {
2388 <3 14 RK_FUNC_2 &pcfg_pull_up>,
2389 <3 15 RK_FUNC_2 &pcfg_pull_none>;
2392 uart3_cts: uart3-cts {
2394 <3 18 RK_FUNC_2 &pcfg_pull_none>;
2397 uart3_rts: uart3-rts {
2399 <3 19 RK_FUNC_2 &pcfg_pull_none>;
2404 uart4_xfer: uart4-xfer {
2406 <1 7 RK_FUNC_1 &pcfg_pull_up>,
2407 <1 8 RK_FUNC_1 &pcfg_pull_none>;
2412 uarthdcp_xfer: uarthdcp-xfer {
2414 <4 21 RK_FUNC_2 &pcfg_pull_up>,
2415 <4 22 RK_FUNC_2 &pcfg_pull_none>;
2420 pwm0_pin: pwm0-pin {
2422 <4 18 RK_FUNC_1 &pcfg_pull_none>;
2425 vop0_pwm_pin: vop0-pwm-pin {
2427 <4 18 RK_FUNC_2 &pcfg_pull_none>;
2432 pwm1_pin: pwm1-pin {
2434 <4 22 RK_FUNC_1 &pcfg_pull_none>;
2437 vop1_pwm_pin: vop1-pwm-pin {
2439 <4 18 RK_FUNC_3 &pcfg_pull_none>;
2444 pwm2_pin: pwm2-pin {
2446 <1 19 RK_FUNC_1 &pcfg_pull_none>;
2451 pwm3a_pin: pwm3a-pin {
2453 <0 6 RK_FUNC_1 &pcfg_pull_none>;
2458 pwm3b_pin: pwm3b-pin {
2460 <1 14 RK_FUNC_1 &pcfg_pull_none>;
2467 <4 23 RK_FUNC_2 &pcfg_pull_none>;
2472 hdmi_i2c_xfer: hdmi-i2c-xfer {
2474 <4 17 RK_FUNC_3 &pcfg_pull_none>,
2475 <4 16 RK_FUNC_3 &pcfg_pull_none>;
2478 hdmi_cec: hdmi-cec {
2480 <4 23 RK_FUNC_1 &pcfg_pull_none>;
2485 pcie_clkreqn: pci-clkreqn {
2487 <2 26 RK_FUNC_2 &pcfg_pull_none>;
2490 pcie_clkreqnb: pci-clkreqnb {
2492 <4 24 RK_FUNC_1 &pcfg_pull_none>;