UPSTREAM: ARM64: dts: rockchip: update rk3399.dtsi for emmc&phy
[firefly-linux-kernel-4.4.55.git] / arch / arm64 / boot / dts / rockchip / rk3399.dtsi
1 /*
2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
3  *
4  * This file is dual-licensed: you can use it either under the terms
5  * of the GPL or the X11 license, at your option. Note that this dual
6  * licensing only applies to this file, and not this project as a
7  * whole.
8  *
9  *  a) This library is free software; you can redistribute it and/or
10  *     modify it under the terms of the GNU General Public License as
11  *     published by the Free Software Foundation; either version 2 of the
12  *     License, or (at your option) any later version.
13  *
14  *     This library is distributed in the hope that it will be useful,
15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  *     GNU General Public License for more details.
18  *
19  * Or, alternatively,
20  *
21  *  b) Permission is hereby granted, free of charge, to any person
22  *     obtaining a copy of this software and associated documentation
23  *     files (the "Software"), to deal in the Software without
24  *     restriction, including without limitation the rights to use,
25  *     copy, modify, merge, publish, distribute, sublicense, and/or
26  *     sell copies of the Software, and to permit persons to whom the
27  *     Software is furnished to do so, subject to the following
28  *     conditions:
29  *
30  *     The above copyright notice and this permission notice shall be
31  *     included in all copies or substantial portions of the Software.
32  *
33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40  *     OTHER DEALINGS IN THE SOFTWARE.
41  */
42
43 #include <dt-bindings/clock/rk3399-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/interrupt-controller/irq.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/power/rk3399-power.h>
49 #include <dt-bindings/soc/rockchip_boot-mode.h>
50 #include <dt-bindings/thermal/thermal.h>
51
52 #include "rk3399-dram-default-timing.dtsi"
53
54 / {
55         compatible = "rockchip,rk3399";
56
57         interrupt-parent = <&gic>;
58         #address-cells = <2>;
59         #size-cells = <2>;
60
61         aliases {
62                 i2c0 = &i2c0;
63                 i2c1 = &i2c1;
64                 i2c2 = &i2c2;
65                 i2c3 = &i2c3;
66                 i2c4 = &i2c4;
67                 i2c5 = &i2c5;
68                 i2c6 = &i2c6;
69                 i2c7 = &i2c7;
70                 i2c8 = &i2c8;
71                 serial0 = &uart0;
72                 serial1 = &uart1;
73                 serial2 = &uart2;
74                 serial3 = &uart3;
75                 serial4 = &uart4;
76         };
77
78         psci {
79                 compatible = "arm,psci-1.0";
80                 method = "smc";
81         };
82
83         cpus {
84                 #address-cells = <2>;
85                 #size-cells = <0>;
86
87                 cpu-map {
88                         cluster0 {
89                                 core0 {
90                                         cpu = <&cpu_l0>;
91                                 };
92                                 core1 {
93                                         cpu = <&cpu_l1>;
94                                 };
95                                 core2 {
96                                         cpu = <&cpu_l2>;
97                                 };
98                                 core3 {
99                                         cpu = <&cpu_l3>;
100                                 };
101                         };
102
103                         cluster1 {
104                                 core0 {
105                                         cpu = <&cpu_b0>;
106                                 };
107                                 core1 {
108                                         cpu = <&cpu_b1>;
109                                 };
110                         };
111                 };
112
113                 cpu_l0: cpu@0 {
114                         device_type = "cpu";
115                         compatible = "arm,cortex-a53", "arm,armv8";
116                         reg = <0x0 0x0>;
117                         enable-method = "psci";
118                         #cooling-cells = <2>; /* min followed by max */
119                         dynamic-power-coefficient = <100>;
120                         clocks = <&cru ARMCLKL>;
121                         cpu-idle-states = <&cpu_sleep>;
122                         operating-points-v2 = <&cluster0_opp>;
123                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
124                 };
125
126                 cpu_l1: cpu@1 {
127                         device_type = "cpu";
128                         compatible = "arm,cortex-a53", "arm,armv8";
129                         reg = <0x0 0x1>;
130                         enable-method = "psci";
131                         clocks = <&cru ARMCLKL>;
132                         cpu-idle-states = <&cpu_sleep>;
133                         operating-points-v2 = <&cluster0_opp>;
134                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
135                 };
136
137                 cpu_l2: cpu@2 {
138                         device_type = "cpu";
139                         compatible = "arm,cortex-a53", "arm,armv8";
140                         reg = <0x0 0x2>;
141                         enable-method = "psci";
142                         clocks = <&cru ARMCLKL>;
143                         cpu-idle-states = <&cpu_sleep>;
144                         operating-points-v2 = <&cluster0_opp>;
145                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
146                 };
147
148                 cpu_l3: cpu@3 {
149                         device_type = "cpu";
150                         compatible = "arm,cortex-a53", "arm,armv8";
151                         reg = <0x0 0x3>;
152                         enable-method = "psci";
153                         clocks = <&cru ARMCLKL>;
154                         cpu-idle-states = <&cpu_sleep>;
155                         operating-points-v2 = <&cluster0_opp>;
156                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
157                 };
158
159                 cpu_b0: cpu@100 {
160                         device_type = "cpu";
161                         compatible = "arm,cortex-a72", "arm,armv8";
162                         reg = <0x0 0x100>;
163                         enable-method = "psci";
164                         #cooling-cells = <2>; /* min followed by max */
165                         dynamic-power-coefficient = <436>;
166                         clocks = <&cru ARMCLKB>;
167                         cpu-idle-states = <&cpu_sleep>;
168                         operating-points-v2 = <&cluster1_opp>;
169                         sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>;
170                 };
171
172                 cpu_b1: cpu@101 {
173                         device_type = "cpu";
174                         compatible = "arm,cortex-a72", "arm,armv8";
175                         reg = <0x0 0x101>;
176                         enable-method = "psci";
177                         clocks = <&cru ARMCLKB>;
178                         cpu-idle-states = <&cpu_sleep>;
179                         operating-points-v2 = <&cluster1_opp>;
180                         sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>;
181                 };
182
183                 idle-states {
184                         entry-method = "psci";
185                         cpu_sleep: cpu-sleep-0 {
186                                 compatible = "arm,idle-state";
187                                 local-timer-stop;
188                                 arm,psci-suspend-param = <0x0010000>;
189                                 entry-latency-us = <350>;
190                                 exit-latency-us = <600>;
191                                 min-residency-us = <1150>;
192                         };
193                 };
194
195                 /include/ "rk3399-sched-energy.dtsi"
196
197         };
198
199         cluster0_opp: opp_table0 {
200                 compatible = "operating-points-v2";
201                 opp-shared;
202
203                 opp@408000000 {
204                         opp-hz = /bits/ 64 <408000000>;
205                         opp-microvolt = <800000>;
206                         clock-latency-ns = <40000>;
207                 };
208                 opp@600000000 {
209                         opp-hz = /bits/ 64 <600000000>;
210                         opp-microvolt = <800000>;
211                 };
212                 opp@816000000 {
213                         opp-hz = /bits/ 64 <816000000>;
214                         opp-microvolt = <800000>;
215                 };
216                 opp@1008000000 {
217                         opp-hz = /bits/ 64 <1008000000>;
218                         opp-microvolt = <875000>;
219                 };
220                 opp@1200000000 {
221                         opp-hz = /bits/ 64 <1200000000>;
222                         opp-microvolt = <925000>;
223                 };
224                 opp@1416000000 {
225                         opp-hz = /bits/ 64 <1416000000>;
226                         opp-microvolt = <1025000>;
227                 };
228         };
229
230         cluster1_opp: opp_table1 {
231                 compatible = "operating-points-v2";
232                 opp-shared;
233
234                 opp@408000000 {
235                         opp-hz = /bits/ 64 <408000000>;
236                         opp-microvolt = <800000>;
237                         clock-latency-ns = <40000>;
238                 };
239                 opp@600000000 {
240                         opp-hz = /bits/ 64 <600000000>;
241                         opp-microvolt = <800000>;
242                 };
243                 opp@816000000 {
244                         opp-hz = /bits/ 64 <816000000>;
245                         opp-microvolt = <800000>;
246                 };
247                 opp@1008000000 {
248                         opp-hz = /bits/ 64 <1008000000>;
249                         opp-microvolt = <850000>;
250                 };
251                 opp@1200000000 {
252                         opp-hz = /bits/ 64 <1200000000>;
253                         opp-microvolt = <925000>;
254                 };
255         };
256
257         timer {
258                 compatible = "arm,armv8-timer";
259                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
260                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
261                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
262                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
263         };
264
265         pmu_a53 {
266                 compatible = "arm,cortex-a53-pmu";
267                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &part0>;
268         };
269
270         pmu_a72 {
271                 compatible = "arm,cortex-a72-pmu";
272                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &part1>;
273         };
274
275         xin24m: xin24m {
276                 compatible = "fixed-clock";
277                 #clock-cells = <0>;
278                 clock-frequency = <24000000>;
279                 clock-output-names = "xin24m";
280         };
281
282         amba {
283                 compatible = "arm,amba-bus";
284                 #address-cells = <2>;
285                 #size-cells = <2>;
286                 ranges;
287
288                 dmac_bus: dma-controller@ff6d0000 {
289                         compatible = "arm,pl330", "arm,primecell";
290                         reg = <0x0 0xff6d0000 0x0 0x4000>;
291                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
292                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
293                         #dma-cells = <1>;
294                         clocks = <&cru ACLK_DMAC0_PERILP>;
295                         clock-names = "apb_pclk";
296                         peripherals-req-type-burst;
297                 };
298
299                 dmac_peri: dma-controller@ff6e0000 {
300                         compatible = "arm,pl330", "arm,primecell";
301                         reg = <0x0 0xff6e0000 0x0 0x4000>;
302                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
303                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>;
304                         #dma-cells = <1>;
305                         clocks = <&cru ACLK_DMAC1_PERILP>;
306                         clock-names = "apb_pclk";
307                         peripherals-req-type-burst;
308                 };
309         };
310
311         gmac: eth@fe300000 {
312                 compatible = "rockchip,rk3399-gmac";
313                 reg = <0x0 0xfe300000 0x0 0x10000>;
314                 rockchip,grf = <&grf>;
315                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
316                 interrupt-names = "macirq";
317                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
318                          <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
319                          <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
320                          <&cru PCLK_GMAC>;
321                 clock-names = "stmmaceth", "mac_clk_rx",
322                               "mac_clk_tx", "clk_mac_ref",
323                               "clk_mac_refout", "aclk_mac",
324                               "pclk_mac";
325                 resets = <&cru SRST_A_GMAC>;
326                 reset-names = "stmmaceth";
327                 power-domains = <&power RK3399_PD_GMAC>;
328                 status = "disabled";
329         };
330
331         sdio0: dwmmc@fe310000 {
332                 compatible = "rockchip,rk3399-dw-mshc",
333                              "rockchip,rk3288-dw-mshc";
334                 reg = <0x0 0xfe310000 0x0 0x4000>;
335                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>;
336                 clock-freq-min-max = <400000 150000000>;
337                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
338                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
339                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
340                 fifo-depth = <0x100>;
341                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
342                 status = "disabled";
343         };
344
345         sdmmc: dwmmc@fe320000 {
346                 compatible = "rockchip,rk3399-dw-mshc",
347                              "rockchip,rk3288-dw-mshc";
348                 reg = <0x0 0xfe320000 0x0 0x4000>;
349                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
350                 clock-freq-min-max = <400000 150000000>;
351                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
352                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
353                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
354                 fifo-depth = <0x100>;
355                 power-domains = <&power RK3399_PD_SD>;
356                 status = "disabled";
357         };
358
359         sdhci: sdhci@fe330000 {
360                 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
361                 reg = <0x0 0xfe330000 0x0 0x10000>;
362                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
363                 arasan,soc-ctl-syscon = <&grf>;
364                 assigned-clocks = <&cru SCLK_EMMC>;
365                 assigned-clock-rates = <200000000>;
366                 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
367                 clock-names = "clk_xin", "clk_ahb";
368                 clock-output-names = "emmc_cardclock";
369                 #clock-cells = <0>;
370                 phys = <&emmc_phy>;
371                 phy-names = "phy_arasan";
372                 power-domains = <&power RK3399_PD_EMMC>;
373                 status = "disabled";
374         };
375
376         usb_host0_ehci: usb@fe380000 {
377                 compatible = "generic-ehci";
378                 reg = <0x0 0xfe380000 0x0 0x20000>;
379                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
380                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
381                          <&cru SCLK_USBPHY0_480M_SRC>;
382                 clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m";
383                 phys = <&u2phy0_host>;
384                 phy-names = "usb";
385                 power-domains = <&power RK3399_PD_PERIHP>;
386                 status = "disabled";
387         };
388
389         usb_host0_ohci: usb@fe3a0000 {
390                 compatible = "generic-ohci";
391                 reg = <0x0 0xfe3a0000 0x0 0x20000>;
392                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
393                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
394                          <&cru SCLK_USBPHY0_480M_SRC>;
395                 clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m";
396                 phys = <&u2phy0_host>;
397                 phy-names = "usb";
398                 power-domains = <&power RK3399_PD_PERIHP>;
399                 status = "disabled";
400         };
401
402         usb_host1_ehci: usb@fe3c0000 {
403                 compatible = "generic-ehci";
404                 reg = <0x0 0xfe3c0000 0x0 0x20000>;
405                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
406                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
407                          <&cru SCLK_USBPHY1_480M_SRC>;
408                 clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m";
409                 phys = <&u2phy1_host>;
410                 phy-names = "usb";
411                 power-domains = <&power RK3399_PD_PERIHP>;
412                 status = "disabled";
413         };
414
415         usb_host1_ohci: usb@fe3e0000 {
416                 compatible = "generic-ohci";
417                 reg = <0x0 0xfe3e0000 0x0 0x20000>;
418                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
419                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
420                          <&cru SCLK_USBPHY1_480M_SRC>;
421                 clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m";
422                 phys = <&u2phy1_host>;
423                 phy-names = "usb";
424                 power-domains = <&power RK3399_PD_PERIHP>;
425                 status = "disabled";
426         };
427
428         usbdrd3_0: usb@fe800000 {
429                 compatible = "rockchip,rk3399-dwc3";
430                 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
431                          <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_GRF>;
432                 clock-names = "ref_clk", "suspend_clk",
433                               "bus_clk", "grf_clk";
434                 power-domains = <&power RK3399_PD_USB3>;
435                 resets = <&cru SRST_A_USB3_OTG0>;
436                 reset-names = "usb3-otg";
437                 #address-cells = <2>;
438                 #size-cells = <2>;
439                 ranges;
440                 status = "disabled";
441                 usbdrd_dwc3_0: dwc3@fe800000 {
442                         compatible = "snps,dwc3";
443                         reg = <0x0 0xfe800000 0x0 0x100000>;
444                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
445                         dr_mode = "otg";
446                         phys = <&u2phy0_otg>, <&tcphy0 1>;
447                         phy-names = "usb2-phy", "usb3-phy";
448                         phy_type = "utmi_wide";
449                         snps,dis_enblslpm_quirk;
450                         snps,dis-u2-freeclk-exists-quirk;
451                         snps,dis-del-phy-power-chg-quirk;
452                         snps,xhci-slow-suspend-quirk;
453                         status = "disabled";
454                 };
455         };
456
457         usbdrd3_1: usb@fe900000 {
458                 compatible = "rockchip,rk3399-dwc3";
459                 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
460                          <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_GRF>;
461                 clock-names = "ref_clk", "suspend_clk",
462                               "bus_clk", "grf_clk";
463                 power-domains = <&power RK3399_PD_USB3>;
464                 resets = <&cru SRST_A_USB3_OTG1>;
465                 reset-names = "usb3-otg";
466                 #address-cells = <2>;
467                 #size-cells = <2>;
468                 ranges;
469                 status = "disabled";
470                 usbdrd_dwc3_1: dwc3@fe900000 {
471                         compatible = "snps,dwc3";
472                         reg = <0x0 0xfe900000 0x0 0x100000>;
473                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
474                         dr_mode = "host";
475                         phys = <&u2phy1_otg>, <&tcphy1 1>;
476                         phy-names = "usb2-phy", "usb3-phy";
477                         phy_type = "utmi_wide";
478                         snps,dis_enblslpm_quirk;
479                         snps,dis-u2-freeclk-exists-quirk;
480                         snps,dis-del-phy-power-chg-quirk;
481                         snps,xhci-slow-suspend-quirk;
482                         status = "disabled";
483                 };
484         };
485
486         gic: interrupt-controller@fee00000 {
487                 compatible = "arm,gic-v3";
488                 #interrupt-cells = <4>;
489                 #address-cells = <2>;
490                 #size-cells = <2>;
491                 ranges;
492                 interrupt-controller;
493
494                 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
495                       <0x0 0xfef00000 0 0xc0000>, /* GICR */
496                       <0x0 0xfff00000 0 0x10000>, /* GICC */
497                       <0x0 0xfff10000 0 0x10000>, /* GICH */
498                       <0x0 0xfff20000 0 0x10000>; /* GICV */
499                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
500                 its: interrupt-controller@fee20000 {
501                         compatible = "arm,gic-v3-its";
502                         msi-controller;
503                         reg = <0x0 0xfee20000 0x0 0x20000>;
504                 };
505
506                 ppi-partitions {
507                         part0: interrupt-partition-0 {
508                                 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
509                         };
510
511                         part1: interrupt-partition-1 {
512                                 affinity = <&cpu_b0 &cpu_b1>;
513                         };
514                 };
515         };
516
517         saradc: saradc@ff100000 {
518                 compatible = "rockchip,rk3399-saradc";
519                 reg = <0x0 0xff100000 0x0 0x100>;
520                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>;
521                 #io-channel-cells = <1>;
522                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
523                 clock-names = "saradc", "apb_pclk";
524                 status = "disabled";
525         };
526
527         i2c0: i2c@ff3c0000 {
528                 compatible = "rockchip,rk3399-i2c";
529                 reg = <0x0 0xff3c0000 0x0 0x1000>;
530                 clocks =  <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
531                 clock-names = "i2c", "pclk";
532                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
533                 pinctrl-names = "default";
534                 pinctrl-0 = <&i2c0_xfer>;
535                 #address-cells = <1>;
536                 #size-cells = <0>;
537                 status = "disabled";
538         };
539
540         i2c1: i2c@ff110000 {
541                 compatible = "rockchip,rk3399-i2c";
542                 reg = <0x0 0xff110000 0x0 0x1000>;
543                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
544                 clock-names = "i2c", "pclk";
545                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>;
546                 pinctrl-names = "default";
547                 pinctrl-0 = <&i2c1_xfer>;
548                 #address-cells = <1>;
549                 #size-cells = <0>;
550                 status = "disabled";
551         };
552
553         i2c2: i2c@ff120000 {
554                 compatible = "rockchip,rk3399-i2c";
555                 reg = <0x0 0xff120000 0x0 0x1000>;
556                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
557                 clock-names = "i2c", "pclk";
558                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>;
559                 pinctrl-names = "default";
560                 pinctrl-0 = <&i2c2_xfer>;
561                 #address-cells = <1>;
562                 #size-cells = <0>;
563                 status = "disabled";
564         };
565
566         i2c3: i2c@ff130000 {
567                 compatible = "rockchip,rk3399-i2c";
568                 reg = <0x0 0xff130000 0x0 0x1000>;
569                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
570                 clock-names = "i2c", "pclk";
571                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>;
572                 pinctrl-names = "default";
573                 pinctrl-0 = <&i2c3_xfer>;
574                 #address-cells = <1>;
575                 #size-cells = <0>;
576                 status = "disabled";
577         };
578
579         i2c5: i2c@ff140000 {
580                 compatible = "rockchip,rk3399-i2c";
581                 reg = <0x0 0xff140000 0x0 0x1000>;
582                 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
583                 clock-names = "i2c", "pclk";
584                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>;
585                 pinctrl-names = "default";
586                 pinctrl-0 = <&i2c5_xfer>;
587                 #address-cells = <1>;
588                 #size-cells = <0>;
589                 status = "disabled";
590         };
591
592         i2c6: i2c@ff150000 {
593                 compatible = "rockchip,rk3399-i2c";
594                 reg = <0x0 0xff150000 0x0 0x1000>;
595                 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
596                 clock-names = "i2c", "pclk";
597                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>;
598                 pinctrl-names = "default";
599                 pinctrl-0 = <&i2c6_xfer>;
600                 #address-cells = <1>;
601                 #size-cells = <0>;
602                 status = "disabled";
603         };
604
605         i2c7: i2c@ff160000 {
606                 compatible = "rockchip,rk3399-i2c";
607                 reg = <0x0 0xff160000 0x0 0x1000>;
608                 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
609                 clock-names = "i2c", "pclk";
610                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>;
611                 pinctrl-names = "default";
612                 pinctrl-0 = <&i2c7_xfer>;
613                 #address-cells = <1>;
614                 #size-cells = <0>;
615                 status = "disabled";
616         };
617
618         uart0: serial@ff180000 {
619                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
620                 reg = <0x0 0xff180000 0x0 0x100>;
621                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
622                 clock-names = "baudclk", "apb_pclk";
623                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
624                 reg-shift = <2>;
625                 reg-io-width = <4>;
626                 pinctrl-names = "default";
627                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
628                 status = "disabled";
629         };
630
631         uart1: serial@ff190000 {
632                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
633                 reg = <0x0 0xff190000 0x0 0x100>;
634                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
635                 clock-names = "baudclk", "apb_pclk";
636                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>;
637                 reg-shift = <2>;
638                 reg-io-width = <4>;
639                 pinctrl-names = "default";
640                 pinctrl-0 = <&uart1_xfer>;
641                 status = "disabled";
642         };
643
644         uart2: serial@ff1a0000 {
645                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
646                 reg = <0x0 0xff1a0000 0x0 0x100>;
647                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
648                 clock-names = "baudclk", "apb_pclk";
649                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
650                 reg-shift = <2>;
651                 reg-io-width = <4>;
652                 pinctrl-names = "default";
653                 pinctrl-0 = <&uart2c_xfer>;
654                 status = "disabled";
655         };
656
657         uart3: serial@ff1b0000 {
658                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
659                 reg = <0x0 0xff1b0000 0x0 0x100>;
660                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
661                 clock-names = "baudclk", "apb_pclk";
662                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
663                 reg-shift = <2>;
664                 reg-io-width = <4>;
665                 pinctrl-names = "default";
666                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
667                 status = "disabled";
668         };
669
670         spi0: spi@ff1c0000 {
671                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
672                 reg = <0x0 0xff1c0000 0x0 0x1000>;
673                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
674                 clock-names = "spiclk", "apb_pclk";
675                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>;
676                 pinctrl-names = "default";
677                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
678                 #address-cells = <1>;
679                 #size-cells = <0>;
680                 status = "disabled";
681         };
682
683         spi1: spi@ff1d0000 {
684                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
685                 reg = <0x0 0xff1d0000 0x0 0x1000>;
686                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
687                 clock-names = "spiclk", "apb_pclk";
688                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>;
689                 pinctrl-names = "default";
690                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
691                 #address-cells = <1>;
692                 #size-cells = <0>;
693                 status = "disabled";
694         };
695
696         spi2: spi@ff1e0000 {
697                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
698                 reg = <0x0 0xff1e0000 0x0 0x1000>;
699                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
700                 clock-names = "spiclk", "apb_pclk";
701                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>;
702                 pinctrl-names = "default";
703                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
704                 #address-cells = <1>;
705                 #size-cells = <0>;
706                 status = "disabled";
707         };
708
709         spi4: spi@ff1f0000 {
710                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
711                 reg = <0x0 0xff1f0000 0x0 0x1000>;
712                 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
713                 clock-names = "spiclk", "apb_pclk";
714                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>;
715                 pinctrl-names = "default";
716                 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
717                 #address-cells = <1>;
718                 #size-cells = <0>;
719                 status = "disabled";
720         };
721
722         spi5: spi@ff200000 {
723                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
724                 reg = <0x0 0xff200000 0x0 0x1000>;
725                 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
726                 clock-names = "spiclk", "apb_pclk";
727                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
728                 pinctrl-names = "default";
729                 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
730                 #address-cells = <1>;
731                 #size-cells = <0>;
732                 status = "disabled";
733         };
734
735         thermal-zones {
736                 soc_thermal: soc-thermal {
737                         polling-delay-passive = <20>; /* milliseconds */
738                         polling-delay = <1000>; /* milliseconds */
739                         sustainable-power = <1000>; /* milliwatts */
740
741                         thermal-sensors = <&tsadc 0>;
742
743                         trips {
744                                 threshold: trip-point@0 {
745                                         temperature = <70000>; /* millicelsius */
746                                         hysteresis = <2000>; /* millicelsius */
747                                         type = "passive";
748                                 };
749                                 target: trip-point@1 {
750                                         temperature = <85000>; /* millicelsius */
751                                         hysteresis = <2000>; /* millicelsius */
752                                         type = "passive";
753                                 };
754                                 soc_crit: soc-crit {
755                                         temperature = <95000>; /* millicelsius */
756                                         hysteresis = <2000>; /* millicelsius */
757                                         type = "critical";
758                                 };
759                         };
760
761                         cooling-maps {
762                                 map0 {
763                                         trip = <&target>;
764                                         cooling-device =
765                                                 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
766                                         contribution = <4096>;
767                                 };
768                                 map1 {
769                                         trip = <&target>;
770                                         cooling-device =
771                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
772                                         contribution = <1024>;
773                                 };
774                                 map2 {
775                                         trip = <&target>;
776                                         cooling-device =
777                                                 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
778                                         contribution = <4096>;
779                                 };
780                         };
781                 };
782
783                 gpu_thermal: gpu-thermal {
784                         polling-delay-passive = <100>; /* milliseconds */
785                         polling-delay = <1000>; /* milliseconds */
786
787                         thermal-sensors = <&tsadc 1>;
788                 };
789         };
790
791         tsadc: tsadc@ff260000 {
792                 compatible = "rockchip,rk3399-tsadc";
793                 reg = <0x0 0xff260000 0x0 0x100>;
794                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
795                 rockchip,grf = <&grf>;
796                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
797                 clock-names = "tsadc", "apb_pclk";
798                 assigned-clocks = <&cru SCLK_TSADC>;
799                 assigned-clock-rates = <750000>;
800                 resets = <&cru SRST_TSADC>;
801                 reset-names = "tsadc-apb";
802                 pinctrl-names = "init", "default", "sleep";
803                 pinctrl-0 = <&otp_gpio>;
804                 pinctrl-1 = <&otp_out>;
805                 pinctrl-2 = <&otp_gpio>;
806                 #thermal-sensor-cells = <1>;
807                 rockchip,hw-tshut-temp = <95000>;
808                 status = "disabled";
809         };
810
811         qos_emmc: qos@ffa58000 {
812                 compatible = "syscon";
813                 reg = <0x0 0xffa58000 0x0 0x20>;
814         };
815
816         qos_gmac: qos@ffa5c000 {
817                 compatible = "syscon";
818                 reg = <0x0 0xffa5c000 0x0 0x20>;
819         };
820
821         qos_pcie: qos@ffa60080 {
822                 compatible = "syscon";
823                 reg = <0x0 0xffa60080 0x0 0x20>;
824         };
825
826         qos_usb_host0: qos@ffa60100 {
827                 compatible = "syscon";
828                 reg = <0x0 0xffa60100 0x0 0x20>;
829         };
830
831         qos_usb_host1: qos@ffa60180 {
832                 compatible = "syscon";
833                 reg = <0x0 0xffa60180 0x0 0x20>;
834         };
835
836         qos_usb_otg0: qos@ffa70000 {
837                 compatible = "syscon";
838                 reg = <0x0 0xffa70000 0x0 0x20>;
839         };
840
841         qos_usb_otg1: qos@ffa70080 {
842                 compatible = "syscon";
843                 reg = <0x0 0xffa70080 0x0 0x20>;
844         };
845
846         qos_sd: qos@ffa74000 {
847                 compatible = "syscon";
848                 reg = <0x0 0xffa74000 0x0 0x20>;
849         };
850
851         qos_sdioaudio: qos@ffa76000 {
852                 compatible = "syscon";
853                 reg = <0x0 0xffa76000 0x0 0x20>;
854         };
855
856         qos_hdcp: qos@ffa90000 {
857                 compatible = "syscon";
858                 reg = <0x0 0xffa90000 0x0 0x20>;
859         };
860
861         qos_iep: qos@ffa98000 {
862                 compatible = "syscon";
863                 reg = <0x0 0xffa98000 0x0 0x20>;
864         };
865
866         qos_isp0_m0: qos@ffaa0000 {
867                 compatible = "syscon";
868                 reg = <0x0 0xffaa0000 0x0 0x20>;
869         };
870
871         qos_isp0_m1: qos@ffaa0080 {
872                 compatible = "syscon";
873                 reg = <0x0 0xffaa0080 0x0 0x20>;
874         };
875
876         qos_isp1_m0: qos@ffaa8000 {
877                 compatible = "syscon";
878                 reg = <0x0 0xffaa8000 0x0 0x20>;
879         };
880
881         qos_isp1_m1: qos@ffaa8080 {
882                 compatible = "syscon";
883                 reg = <0x0 0xffaa8080 0x0 0x20>;
884         };
885
886         qos_rga_r: qos@ffab0000 {
887                 compatible = "syscon";
888                 reg = <0x0 0xffab0000 0x0 0x20>;
889         };
890
891         qos_rga_w: qos@ffab0080 {
892                 compatible = "syscon";
893                 reg = <0x0 0xffab0080 0x0 0x20>;
894         };
895
896         qos_video_m0: qos@ffab8000 {
897                 compatible = "syscon";
898                 reg = <0x0 0xffab8000 0x0 0x20>;
899         };
900
901         qos_video_m1_r: qos@ffac0000 {
902                 compatible = "syscon";
903                 reg = <0x0 0xffac0000 0x0 0x20>;
904         };
905
906         qos_video_m1_w: qos@ffac0080 {
907                 compatible = "syscon";
908                 reg = <0x0 0xffac0080 0x0 0x20>;
909         };
910
911         qos_vop_big_r: qos@ffac8000 {
912                 compatible = "syscon";
913                 reg = <0x0 0xffac8000 0x0 0x20>;
914         };
915
916         qos_vop_big_w: qos@ffac8080 {
917                 compatible = "syscon";
918                 reg = <0x0 0xffac8080 0x0 0x20>;
919         };
920
921         qos_vop_little: qos@ffad0000 {
922                 compatible = "syscon";
923                 reg = <0x0 0xffad0000 0x0 0x20>;
924         };
925
926         qos_perihp: qos@ffad8080 {
927                 compatible = "syscon";
928                 reg = <0x0 0xffad8080 0x0 0x20>;
929         };
930
931         qos_gpu: qos@ffae0000 {
932                 compatible = "syscon";
933                 reg = <0x0 0xffae0000 0x0 0x20>;
934         };
935
936         pmu: power-management@ff310000 {
937                 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
938                 reg = <0x0 0xff310000 0x0 0x1000>;
939
940                 /*
941                  * Note: RK3399 supports 6 voltage domains including VD_CORE_L,
942                  * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
943                  * Some of the power domains are grouped together for every
944                  * voltage domain.
945                  * The detail contents as below.
946                  */
947                 power: power-controller {
948                         compatible = "rockchip,rk3399-power-controller";
949                         #power-domain-cells = <1>;
950                         #address-cells = <1>;
951                         #size-cells = <0>;
952
953                         /* These power domains are grouped by VD_CENTER */
954                         pd_iep@RK3399_PD_IEP {
955                                 reg = <RK3399_PD_IEP>;
956                                 clocks = <&cru ACLK_IEP>,
957                                          <&cru HCLK_IEP>;
958                                 pm_qos = <&qos_iep>;
959                         };
960                         pd_rga@RK3399_PD_RGA {
961                                 reg = <RK3399_PD_RGA>;
962                                 clocks = <&cru ACLK_RGA>,
963                                          <&cru HCLK_RGA>;
964                                 pm_qos = <&qos_rga_r>,
965                                          <&qos_rga_w>;
966                         };
967                         pd_vcodec@RK3399_PD_VCODEC {
968                                 reg = <RK3399_PD_VCODEC>;
969                                 clocks = <&cru ACLK_VCODEC>,
970                                          <&cru HCLK_VCODEC>;
971                                 pm_qos = <&qos_video_m0>;
972                         };
973                         pd_vdu@RK3399_PD_VDU {
974                                 reg = <RK3399_PD_VDU>;
975                                 clocks = <&cru ACLK_VDU>,
976                                          <&cru HCLK_VDU>;
977                                 pm_qos = <&qos_video_m1_r>,
978                                          <&qos_video_m1_w>;
979                         };
980
981                         /* These power domains are grouped by VD_GPU */
982                         pd_gpu@RK3399_PD_GPU {
983                                 reg = <RK3399_PD_GPU>;
984                                 clocks = <&cru ACLK_GPU>;
985                                 pm_qos = <&qos_gpu>;
986                         };
987
988                         /* These power domains are grouped by VD_LOGIC */
989                         pd_edp@RK3399_PD_EDP {
990                                 reg = <RK3399_PD_EDP>;
991                                 clocks = <&cru PCLK_EDP_CTRL>;
992                         };
993                         pd_emmc@RK3399_PD_EMMC {
994                                 reg = <RK3399_PD_EMMC>;
995                                 clocks = <&cru ACLK_EMMC>;
996                                 pm_qos = <&qos_emmc>;
997                         };
998                         pd_gmac@RK3399_PD_GMAC {
999                                 reg = <RK3399_PD_GMAC>;
1000                                 clocks = <&cru ACLK_GMAC>;
1001                                 pm_qos = <&qos_gmac>;
1002                         };
1003                         pd_perihp@RK3399_PD_PERIHP {
1004                                 reg = <RK3399_PD_PERIHP>;
1005                                 #address-cells = <1>;
1006                                 #size-cells = <0>;
1007                                 clocks = <&cru ACLK_PERIHP>;
1008                                 pm_qos = <&qos_perihp>,
1009                                          <&qos_pcie>,
1010                                          <&qos_usb_host0>,
1011                                          <&qos_usb_host1>;
1012
1013                                 pd_sd@RK3399_PD_SD {
1014                                         reg = <RK3399_PD_SD>;
1015                                         clocks = <&cru HCLK_SDMMC>,
1016                                                  <&cru SCLK_SDMMC>;
1017                                         pm_qos = <&qos_sd>;
1018                                 };
1019                         };
1020                         pd_sdioaudio@RK3399_PD_SDIOAUDIO {
1021                                 reg = <RK3399_PD_SDIOAUDIO>;
1022                                 clocks = <&cru HCLK_SDIO>;
1023                                 pm_qos = <&qos_sdioaudio>;
1024                         };
1025                         pd_usb3@RK3399_PD_USB3 {
1026                                 reg = <RK3399_PD_USB3>;
1027                                 clocks = <&cru ACLK_USB3>;
1028                                 pm_qos = <&qos_usb_otg0>,
1029                                          <&qos_usb_otg1>;
1030                         };
1031                         pd_vio@RK3399_PD_VIO {
1032                                 reg = <RK3399_PD_VIO>;
1033                                 #address-cells = <1>;
1034                                 #size-cells = <0>;
1035
1036                                 pd_hdcp@RK3399_PD_HDCP {
1037                                         reg = <RK3399_PD_HDCP>;
1038                                         clocks = <&cru ACLK_HDCP>,
1039                                                  <&cru HCLK_HDCP>,
1040                                                  <&cru PCLK_HDCP>;
1041                                         pm_qos = <&qos_hdcp>;
1042                                 };
1043                                 pd_isp0@RK3399_PD_ISP0 {
1044                                         reg = <RK3399_PD_ISP0>;
1045                                         clocks = <&cru ACLK_ISP0>,
1046                                                  <&cru HCLK_ISP0>;
1047                                         pm_qos = <&qos_isp0_m0>,
1048                                                  <&qos_isp0_m1>;
1049                                 };
1050                                 pd_isp1@RK3399_PD_ISP1 {
1051                                         reg = <RK3399_PD_ISP1>;
1052                                         clocks = <&cru ACLK_ISP1>,
1053                                                  <&cru HCLK_ISP1>;
1054                                         pm_qos = <&qos_isp1_m0>,
1055                                                  <&qos_isp1_m1>;
1056                                 };
1057                                 pd_vo@RK3399_PD_VO {
1058                                         reg = <RK3399_PD_VO>;
1059                                         #address-cells = <1>;
1060                                         #size-cells = <0>;
1061
1062                                         pd_vopb@RK3399_PD_VOPB {
1063                                                 reg = <RK3399_PD_VOPB>;
1064                                                 clocks = <&cru ACLK_VOP0>,
1065                                                          <&cru HCLK_VOP0>;
1066                                                 pm_qos = <&qos_vop_big_r>,
1067                                                          <&qos_vop_big_w>;
1068                                         };
1069                                         pd_vopl@RK3399_PD_VOPL {
1070                                                 reg = <RK3399_PD_VOPL>;
1071                                                 clocks = <&cru ACLK_VOP1>,
1072                                                          <&cru HCLK_VOP1>;
1073                                                 pm_qos = <&qos_vop_little>;
1074                                         };
1075                                 };
1076                         };
1077                 };
1078         };
1079
1080         pmugrf: syscon@ff320000 {
1081                 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
1082                 reg = <0x0 0xff320000 0x0 0x1000>;
1083
1084                 reboot-mode {
1085                         compatible = "syscon-reboot-mode";
1086                         offset = <0x300>;
1087                         mode-bootloader = <BOOT_LOADER>;
1088                         mode-charge = <BOOT_CHARGING>;
1089                         mode-fastboot = <BOOT_FASTBOOT>;
1090                         mode-loader = <BOOT_LOADER>;
1091                         mode-normal = <BOOT_NORMAL>;
1092                         mode-recovery = <BOOT_RECOVERY>;
1093                         mode-ums = <BOOT_UMS>;
1094                 };
1095         };
1096
1097         spi3: spi@ff350000 {
1098                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
1099                 reg = <0x0 0xff350000 0x0 0x1000>;
1100                 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
1101                 clock-names = "spiclk", "apb_pclk";
1102                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>;
1103                 pinctrl-names = "default";
1104                 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
1105                 #address-cells = <1>;
1106                 #size-cells = <0>;
1107                 status = "disabled";
1108         };
1109
1110         uart4: serial@ff370000 {
1111                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
1112                 reg = <0x0 0xff370000 0x0 0x100>;
1113                 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
1114                 clock-names = "baudclk", "apb_pclk";
1115                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>;
1116                 reg-shift = <2>;
1117                 reg-io-width = <4>;
1118                 pinctrl-names = "default";
1119                 pinctrl-0 = <&uart4_xfer>;
1120                 status = "disabled";
1121         };
1122
1123         i2c4: i2c@ff3d0000 {
1124                 compatible = "rockchip,rk3399-i2c";
1125                 reg = <0x0 0xff3d0000 0x0 0x1000>;
1126                 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
1127                 clock-names = "i2c", "pclk";
1128                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>;
1129                 pinctrl-names = "default";
1130                 pinctrl-0 = <&i2c4_xfer>;
1131                 #address-cells = <1>;
1132                 #size-cells = <0>;
1133                 status = "disabled";
1134         };
1135
1136         i2c8: i2c@ff3e0000 {
1137                 compatible = "rockchip,rk3399-i2c";
1138                 reg = <0x0 0xff3e0000 0x0 0x1000>;
1139                 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
1140                 clock-names = "i2c", "pclk";
1141                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
1142                 pinctrl-names = "default";
1143                 pinctrl-0 = <&i2c8_xfer>;
1144                 #address-cells = <1>;
1145                 #size-cells = <0>;
1146                 status = "disabled";
1147         };
1148
1149         pcie_phy: phy@e220 {
1150                 compatible = "rockchip,rk3399-pcie-phy";
1151                 #phy-cells = <0>;
1152                 rockchip,grf = <&grf>;
1153                 clocks = <&cru SCLK_PCIEPHY_REF>;
1154                 clock-names = "refclk";
1155                 resets = <&cru SRST_PCIEPHY>;
1156                 reset-names = "phy";
1157                 status = "disabled";
1158         };
1159
1160         pcie0: pcie@f8000000 {
1161                 compatible = "rockchip,rk3399-pcie";
1162                 #address-cells = <3>;
1163                 #size-cells = <2>;
1164                 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
1165                          <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
1166                 clock-names = "aclk", "aclk-perf",
1167                               "hclk", "pm";
1168                 bus-range = <0x0 0x1>;
1169                 msi-map = <0x0 &its 0x0 0x1000>;
1170                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
1171                              <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
1172                              <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
1173                 interrupt-names = "sys", "legacy", "client";
1174                 #interrupt-cells = <1>;
1175                 interrupt-map-mask = <0 0 0 7>;
1176                 interrupt-map = <0 0 0 1 &pcie0_intc 0>,
1177                                 <0 0 0 2 &pcie0_intc 1>,
1178                                 <0 0 0 3 &pcie0_intc 2>,
1179                                 <0 0 0 4 &pcie0_intc 3>;
1180                 phys = <&pcie_phy>;
1181                 phy-names = "pcie-phy";
1182                 ranges = <0x82000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000
1183                           0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>;
1184                 reg = <0x0 0xf8000000 0x0 0x2000000>,
1185                       <0x0 0xfd000000 0x0 0x1000000>;
1186                 reg-names = "axi-base", "apb-base";
1187                 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
1188                          <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>;
1189                 reset-names = "core", "mgmt", "mgmt-sticky", "pipe";
1190                 status = "disabled";
1191                 pcie0_intc: interrupt-controller {
1192                         interrupt-controller;
1193                         #address-cells = <0>;
1194                         #interrupt-cells = <1>;
1195                 };
1196         };
1197
1198         pwm0: pwm@ff420000 {
1199                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1200                 reg = <0x0 0xff420000 0x0 0x10>;
1201                 #pwm-cells = <3>;
1202                 pinctrl-names = "default";
1203                 pinctrl-0 = <&pwm0_pin>;
1204                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1205                 clock-names = "pwm";
1206                 status = "disabled";
1207         };
1208
1209         pwm1: pwm@ff420010 {
1210                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1211                 reg = <0x0 0xff420010 0x0 0x10>;
1212                 #pwm-cells = <3>;
1213                 pinctrl-names = "default";
1214                 pinctrl-0 = <&pwm1_pin>;
1215                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1216                 clock-names = "pwm";
1217                 status = "disabled";
1218         };
1219
1220         pwm2: pwm@ff420020 {
1221                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1222                 reg = <0x0 0xff420020 0x0 0x10>;
1223                 #pwm-cells = <3>;
1224                 pinctrl-names = "default";
1225                 pinctrl-0 = <&pwm2_pin>;
1226                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1227                 clock-names = "pwm";
1228                 status = "disabled";
1229         };
1230
1231         pwm3: pwm@ff420030 {
1232                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1233                 reg = <0x0 0xff420030 0x0 0x10>;
1234                 #pwm-cells = <3>;
1235                 pinctrl-names = "default";
1236                 pinctrl-0 = <&pwm3a_pin>;
1237                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1238                 clock-names = "pwm";
1239                 status = "disabled";
1240         };
1241
1242         dfi: dfi@ff630000 {
1243                 reg = <0x00 0xff630000 0x00 0x4000>;
1244                 compatible = "rockchip,rk3399-dfi";
1245                 rockchip,pmu = <&pmugrf>;
1246                 clocks = <&cru PCLK_DDR_MON>;
1247                 clock-names = "pclk_ddr_mon";
1248                 status = "disabled";
1249         };
1250
1251         dmc: dmc {
1252                 compatible = "rockchip,rk3399-dmc";
1253                 devfreq-events = <&dfi>;
1254                 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>;
1255                 clocks = <&cru SCLK_DDRCLK>;
1256                 clock-names = "dmc_clk";
1257                 ddr_timing = <&ddr_timing>;
1258                 operating-points-v2 = <&dmc_opp_table>;
1259                 status = "disabled";
1260         };
1261
1262         dmc_opp_table: dmc_opp_table {
1263                 compatible = "operating-points-v2";
1264
1265                 opp00 {
1266                         opp-hz = /bits/ 64 <666000000>;
1267                         opp-microvolt = <900000>;
1268                 };
1269         };
1270
1271         rga: rga@ff680000 {
1272                 compatible = "rockchip,rk3399-rga";
1273                 reg = <0x0 0xff680000 0x0 0x10000>;
1274                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
1275                 interrupt-names = "rga";
1276                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
1277                 clock-names = "aclk", "hclk", "sclk";
1278                 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
1279                 reset-names = "core", "axi", "ahb";
1280                 power-domains = <&power RK3399_PD_RGA>;
1281                 status = "disabled";
1282         };
1283
1284         efuse0: efuse@ff690000 {
1285                 compatible = "rockchip,rk3399-efuse";
1286                 reg = <0x0 0xff690000 0x0 0x80>;
1287                 #address-cells = <1>;
1288                 #size-cells = <1>;
1289                 clocks = <&cru PCLK_EFUSE1024NS>;
1290                 clock-names = "pclk_efuse";
1291
1292                 /* Data cells */
1293                 cpul_leakage: cpul-leakage {
1294                         reg = <0x1a 0x1>;
1295                 };
1296                 cpub_leakage: cpub-leakage {
1297                         reg = <0x17 0x1>;
1298                 };
1299                 gpu_leakage: gpu-leakage {
1300                         reg = <0x18 0x1>;
1301                 };
1302                 center_leakage: center-leakage {
1303                         reg = <0x19 0x1>;
1304                 };
1305                 logic_leakage: logic-leakage {
1306                         reg = <0x1b 0x1>;
1307                 };
1308                 wafer_info: wafer-info {
1309                         reg = <0x1c 0x1>;
1310                 };
1311         };
1312
1313         pmucru: pmu-clock-controller@ff750000 {
1314                 compatible = "rockchip,rk3399-pmucru";
1315                 reg = <0x0 0xff750000 0x0 0x1000>;
1316                 #clock-cells = <1>;
1317                 #reset-cells = <1>;
1318                 assigned-clocks = <&pmucru PLL_PPLL>;
1319                 assigned-clock-rates = <676000000>;
1320         };
1321
1322         cru: clock-controller@ff760000 {
1323                 compatible = "rockchip,rk3399-cru";
1324                 reg = <0x0 0xff760000 0x0 0x1000>;
1325                 #clock-cells = <1>;
1326                 #reset-cells = <1>;
1327                 assigned-clocks =
1328                         <&cru ACLK_VOP0>, <&cru HCLK_VOP0>,
1329                         <&cru ACLK_VOP1>, <&cru HCLK_VOP1>,
1330                         <&cru ARMCLKL>, <&cru ARMCLKB>,
1331                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1332                         <&cru PLL_NPLL>,
1333                         <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1334                         <&cru PCLK_PERIHP>,
1335                         <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1336                         <&cru PCLK_PERILP0>,
1337                         <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
1338                 assigned-clock-rates =
1339                          <400000000>,  <200000000>,
1340                          <400000000>,  <200000000>,
1341                          <816000000>, <816000000>,
1342                          <594000000>,  <800000000>,
1343                         <1000000000>,
1344                          <150000000>,   <75000000>,
1345                           <37500000>,
1346                          <100000000>,  <100000000>,
1347                           <50000000>,
1348                          <100000000>,   <50000000>;
1349         };
1350
1351         grf: syscon@ff770000 {
1352                 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
1353                 reg = <0x0 0xff770000 0x0 0x10000>;
1354                 #address-cells = <1>;
1355                 #size-cells = <1>;
1356
1357                 emmc_phy: phy@f780 {
1358                         compatible = "rockchip,rk3399-emmc-phy";
1359                         reg = <0xf780 0x24>;
1360                         clocks = <&sdhci>;
1361                         clock-names = "emmcclk";
1362                         #phy-cells = <0>;
1363                         status = "disabled";
1364                 };
1365
1366                 u2phy0: usb2-phy@e450 {
1367                         compatible = "rockchip,rk3399-usb2phy";
1368                         reg = <0xe450 0x10>;
1369                         clocks = <&cru SCLK_USB2PHY0_REF>;
1370                         clock-names = "phyclk";
1371                         #clock-cells = <0>;
1372                         clock-output-names = "clk_usbphy0_480m";
1373                         status = "disabled";
1374
1375                         u2phy0_otg: otg-port {
1376                                 #phy-cells = <0>;
1377                                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
1378                                              <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
1379                                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
1380                                 interrupt-names = "otg-bvalid", "otg-id",
1381                                                   "linestate";
1382                                 status = "disabled";
1383                         };
1384
1385                         u2phy0_host: host-port {
1386                                 #phy-cells = <0>;
1387                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
1388                                 interrupt-names = "linestate";
1389                                 status = "disabled";
1390                         };
1391                 };
1392
1393                 u2phy1: usb2-phy@e460 {
1394                         compatible = "rockchip,rk3399-usb2phy";
1395                         reg = <0xe460 0x10>;
1396                         clocks = <&cru SCLK_USB2PHY1_REF>;
1397                         clock-names = "phyclk";
1398                         #clock-cells = <0>;
1399                         clock-output-names = "clk_usbphy1_480m";
1400                         status = "disabled";
1401
1402                         u2phy1_otg: otg-port {
1403                                 #phy-cells = <0>;
1404                                 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
1405                                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
1406                                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1407                                 interrupt-names = "otg-bvalid", "otg-id",
1408                                                   "linestate";
1409                                 status = "disabled";
1410                         };
1411
1412                         u2phy1_host: host-port {
1413                                 #phy-cells = <0>;
1414                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
1415                                 interrupt-names = "linestate";
1416                                 status = "disabled";
1417                         };
1418                 };
1419         };
1420
1421         tcphy0: phy@ff7c0000 {
1422                 compatible = "rockchip,rk3399-typec-phy";
1423                 reg = <0x0 0xff7c0000 0x0 0x40000>;
1424                 rockchip,grf = <&grf>;
1425                 #phy-cells = <1>;
1426                 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1427                          <&cru SCLK_UPHY0_TCPDPHY_REF>;
1428                 clock-names = "tcpdcore", "tcpdphy-ref";
1429                 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
1430                 assigned-clock-rates = <50000000>;
1431                 resets = <&cru SRST_UPHY0>,
1432                          <&cru SRST_UPHY0_PIPE_L00>,
1433                          <&cru SRST_P_UPHY0_TCPHY>;
1434                 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1435                 rockchip,typec-conn-dir = <0xe580 0 16>;
1436                 rockchip,usb3tousb2-en = <0xe580 3 19>;
1437                 rockchip,external-psm = <0xe588 14 30>;
1438                 rockchip,pipe-status = <0xe5c0 0 0>;
1439                 rockchip,uphy-dp-sel = <0x6268 19 19>;
1440                 status = "disabled";
1441         };
1442
1443         tcphy1: phy@ff800000 {
1444                 compatible = "rockchip,rk3399-typec-phy";
1445                 reg = <0x0 0xff800000 0x0 0x40000>;
1446                 rockchip,grf = <&grf>;
1447                 #phy-cells = <1>;
1448                 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1449                          <&cru SCLK_UPHY1_TCPDPHY_REF>;
1450                 clock-names = "tcpdcore", "tcpdphy-ref";
1451                 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
1452                 assigned-clock-rates = <50000000>;
1453                 resets = <&cru SRST_UPHY1>,
1454                          <&cru SRST_UPHY1_PIPE_L00>,
1455                          <&cru SRST_P_UPHY1_TCPHY>;
1456                 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1457                 rockchip,typec-conn-dir = <0xe58c 0 16>;
1458                 rockchip,usb3tousb2-en = <0xe58c 3 19>;
1459                 rockchip,external-psm = <0xe594 14 30>;
1460                 rockchip,pipe-status = <0xe5c0 16 16>;
1461                 rockchip,uphy-dp-sel = <0x6268 3 19>;
1462                 status = "disabled";
1463         };
1464
1465         watchdog@ff848000 {
1466                 compatible = "snps,dw-wdt";
1467                 reg = <0x0 0xff848000 0x0 0x100>;
1468                 clocks = <&cru PCLK_WDT>;
1469                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
1470         };
1471
1472         rktimer: rktimer@ff850000 {
1473                 compatible = "rockchip,rk3399-timer";
1474                 reg = <0x0 0xff850000 0x0 0x1000>;
1475                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
1476                 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1477                 clock-names = "pclk", "timer";
1478         };
1479
1480         spdif: spdif@ff870000 {
1481                 compatible = "rockchip,rk3399-spdif";
1482                 reg = <0x0 0xff870000 0x0 0x1000>;
1483                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
1484                 dmas = <&dmac_bus 7>;
1485                 dma-names = "tx";
1486                 clock-names = "mclk", "hclk";
1487                 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1488                 pinctrl-names = "default";
1489                 pinctrl-0 = <&spdif_bus>;
1490                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1491                 status = "disabled";
1492         };
1493
1494         i2s0: i2s@ff880000 {
1495                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1496                 reg = <0x0 0xff880000 0x0 0x1000>;
1497                 rockchip,grf = <&grf>;
1498                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>;
1499                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1500                 dma-names = "tx", "rx";
1501                 clock-names = "i2s_clk", "i2s_hclk";
1502                 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1503                 pinctrl-names = "default";
1504                 pinctrl-0 = <&i2s0_8ch_bus>;
1505                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1506                 status = "disabled";
1507         };
1508
1509         i2s1: i2s@ff890000 {
1510                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1511                 reg = <0x0 0xff890000 0x0 0x1000>;
1512                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>;
1513                 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1514                 dma-names = "tx", "rx";
1515                 clock-names = "i2s_clk", "i2s_hclk";
1516                 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1517                 pinctrl-names = "default";
1518                 pinctrl-0 = <&i2s1_2ch_bus>;
1519                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1520                 status = "disabled";
1521         };
1522
1523         i2s2: i2s@ff8a0000 {
1524                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1525                 reg = <0x0 0xff8a0000 0x0 0x1000>;
1526                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>;
1527                 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1528                 dma-names = "tx", "rx";
1529                 clock-names = "i2s_clk", "i2s_hclk";
1530                 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1531                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1532                 status = "disabled";
1533         };
1534
1535         gpu: gpu@ff9a0000 {
1536                 compatible = "arm,malit860",
1537                              "arm,malit86x",
1538                              "arm,malit8xx",
1539                              "arm,mali-midgard";
1540
1541                 reg = <0x0 0xff9a0000 0x0 0x10000>;
1542
1543                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>,
1544                              <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
1545                              <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>;
1546                 interrupt-names = "GPU", "JOB", "MMU";
1547
1548                 clocks = <&cru ACLK_GPU>;
1549                 clock-names = "clk_mali";
1550                 #cooling-cells = <2>; /* min followed by max */
1551                 operating-points-v2 = <&gpu_opp_table>;
1552                 power-domains = <&power RK3399_PD_GPU>;
1553                 power-off-delay-ms = <200>;
1554                 status = "disabled";
1555
1556                 gpu_power_model: power_model {
1557                         compatible = "arm,mali-simple-power-model";
1558                         voltage = <900>;
1559                         frequency = <500>;
1560                         static-power = <300>;
1561                         dynamic-power = <396>;
1562                         ts = <32000 4700 (-80) 2>;
1563                         thermal-zone = "gpu-thermal";
1564                 };
1565         };
1566
1567         gpu_opp_table: gpu_opp_table {
1568                 compatible = "operating-points-v2";
1569                 opp-shared;
1570
1571                 opp@200000000 {
1572                         opp-hz = /bits/ 64 <200000000>;
1573                         opp-microvolt = <900000>;
1574                 };
1575                 opp@300000000 {
1576                         opp-hz = /bits/ 64 <300000000>;
1577                         opp-microvolt = <900000>;
1578                 };
1579                 opp@400000000 {
1580                         opp-hz = /bits/ 64 <400000000>;
1581                         opp-microvolt = <900000>;
1582                 };
1583
1584         };
1585
1586         vopl: vop@ff8f0000 {
1587                 compatible = "rockchip,rk3399-vop-lit";
1588                 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1589                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1590                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1591                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1592                 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1593                 reset-names = "axi", "ahb", "dclk";
1594                 power-domains = <&power RK3399_PD_VOPL>;
1595                 iommus = <&vopl_mmu>;
1596                 status = "disabled";
1597
1598                 vopl_out: port {
1599                         #address-cells = <1>;
1600                         #size-cells = <0>;
1601
1602                         vopl_out_mipi: endpoint@0 {
1603                                 reg = <0>;
1604                                 remote-endpoint = <&mipi_in_vopl>;
1605                         };
1606
1607                         vopl_out_edp: endpoint@1 {
1608                                 reg = <1>;
1609                                 remote-endpoint = <&edp_in_vopl>;
1610                         };
1611
1612                         vopl_out_hdmi: endpoint@2 {
1613                                 reg = <2>;
1614                                 remote-endpoint = <&hdmi_in_vopl>;
1615                         };
1616                 };
1617         };
1618
1619         vop1_pwm: voppwm@ff8f01a0 {
1620                 compatible = "rockchip,vop-pwm";
1621                 reg = <0x0 0xff8f01a0 0x0 0x10>;
1622                 #pwm-cells = <3>;
1623                 pinctrl-names = "default";
1624                 pinctrl-0 = <&vop1_pwm_pin>;
1625                 clocks = <&cru SCLK_VOP1_PWM>;
1626                 clock-names = "pwm";
1627                 status = "disabled";
1628         };
1629
1630         vopl_mmu: iommu@ff8f3f00 {
1631                 compatible = "rockchip,iommu";
1632                 reg = <0x0 0xff8f3f00 0x0 0x100>;
1633                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1634                 interrupt-names = "vopl_mmu";
1635                 #iommu-cells = <0>;
1636                 status = "disabled";
1637         };
1638
1639         vopb: vop@ff900000 {
1640                 compatible = "rockchip,rk3399-vop-big";
1641                 reg = <0x0 0xff900000 0x0 0x3efc>;
1642                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1643                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1644                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1645                 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1646                 reset-names = "axi", "ahb", "dclk";
1647                 power-domains = <&power RK3399_PD_VOPB>;
1648                 iommus = <&vopb_mmu>;
1649                 status = "disabled";
1650
1651                 vopb_out: port {
1652                         #address-cells = <1>;
1653                         #size-cells = <0>;
1654
1655                         vopb_out_edp: endpoint@0 {
1656                                 reg = <0>;
1657                                 remote-endpoint = <&edp_in_vopb>;
1658                         };
1659
1660                         vopb_out_mipi: endpoint@1 {
1661                                 reg = <1>;
1662                                 remote-endpoint = <&mipi_in_vopb>;
1663                         };
1664
1665                         vopb_out_hdmi: endpoint@2 {
1666                                 reg = <2>;
1667                                 remote-endpoint = <&hdmi_in_vopb>;
1668                         };
1669                 };
1670         };
1671
1672         vop0_pwm: voppwm@ff9001a0 {
1673                 compatible = "rockchip,vop-pwm";
1674                 reg = <0x0 0xff9001a0 0x0 0x10>;
1675                 #pwm-cells = <3>;
1676                 pinctrl-names = "default";
1677                 pinctrl-0 = <&vop0_pwm_pin>;
1678                 clocks = <&cru SCLK_VOP0_PWM>;
1679                 clock-names = "pwm";
1680                 status = "disabled";
1681         };
1682
1683         vopb_mmu: iommu@ff903f00 {
1684                 compatible = "rockchip,iommu";
1685                 reg = <0x0 0xff903f00 0x0 0x100>;
1686                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1687                 interrupt-names = "vopb_mmu";
1688                 #iommu-cells = <0>;
1689                 status = "disabled";
1690         };
1691
1692         hdmi: hdmi@ff940000 {
1693                 compatible = "rockchip,rk3399-dw-hdmi";
1694                 reg = <0x0 0xff940000 0x0 0x20000>;
1695                 reg-io-width = <4>;
1696                 rockchip,grf = <&grf>;
1697                 power-domains = <&power RK3399_PD_HDCP>;
1698                 pinctrl-names = "default";
1699                 pinctrl-0 = <&hdmi_i2c_xfer>;
1700                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
1701                 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_SFR>, <&cru SCLK_HDMI_SFR>, <&cru PCLK_EDP_CTRL>;
1702                 clock-names = "iahb", "isfr", "vpll", "grf";
1703                 status = "disabled";
1704
1705                 ports {
1706                         hdmi_in: port {
1707                                 #address-cells = <1>;
1708                                 #size-cells = <0>;
1709                                 hdmi_in_vopb: endpoint@0 {
1710                                         reg = <0>;
1711                                         remote-endpoint = <&vopb_out_hdmi>;
1712                                 };
1713                                 hdmi_in_vopl: endpoint@1 {
1714                                         reg = <1>;
1715                                         remote-endpoint = <&vopl_out_hdmi>;
1716                                 };
1717                         };
1718                 };
1719         };
1720
1721         mipi_dsi: mipi@ff960000 {
1722                 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1723                 reg = <0x0 0xff960000 0x0 0x8000>;
1724                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
1725                 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
1726                          <&cru SCLK_DPHY_TX0_CFG>;
1727                 clock-names = "ref", "pclk", "phy_cfg";
1728                 power-domains = <&power RK3399_PD_VIO>;
1729                 rockchip,grf = <&grf>;
1730                 #address-cells = <1>;
1731                 #size-cells = <0>;
1732                 status = "disabled";
1733
1734                 ports {
1735                         #address-cells = <1>;
1736                         #size-cells = <0>;
1737                         reg = <1>;
1738
1739                         mipi_in: port {
1740                                 #address-cells = <1>;
1741                                 #size-cells = <0>;
1742
1743                                 mipi_in_vopb: endpoint@0 {
1744                                         reg = <0>;
1745                                         remote-endpoint = <&vopb_out_mipi>;
1746                                 };
1747                                 mipi_in_vopl: endpoint@1 {
1748                                         reg = <1>;
1749                                         remote-endpoint = <&vopl_out_mipi>;
1750                                 };
1751                         };
1752                 };
1753         };
1754
1755         edp: edp@ff970000 {
1756                 compatible = "rockchip,rk3399-edp";
1757                 reg = <0x0 0xff970000 0x0 0x8000>;
1758                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
1759                 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1760                 clock-names = "dp", "pclk";
1761                 resets = <&cru SRST_P_EDP_CTRL>;
1762                 reset-names = "dp";
1763                 rockchip,grf = <&grf>;
1764                 status = "disabled";
1765                 pinctrl-names = "default";
1766                 pinctrl-0 = <&edp_hpd>;
1767
1768                 ports {
1769                         #address-cells = <1>;
1770                         #size-cells = <0>;
1771
1772                         edp_in: port@0 {
1773                                 reg = <0>;
1774                                 #address-cells = <1>;
1775                                 #size-cells = <0>;
1776
1777                                 edp_in_vopb: endpoint@0 {
1778                                         reg = <0>;
1779                                         remote-endpoint = <&vopb_out_edp>;
1780                                 };
1781
1782                                 edp_in_vopl: endpoint@1 {
1783                                         reg = <1>;
1784                                         remote-endpoint = <&vopl_out_edp>;
1785                                 };
1786                         };
1787                 };
1788         };
1789
1790         display_subsystem: display-subsystem {
1791                 compatible = "rockchip,display-subsystem";
1792                 ports = <&vopl_out>, <&vopb_out>;
1793                 status = "disabled";
1794         };
1795
1796         pinctrl: pinctrl {
1797                 compatible = "rockchip,rk3399-pinctrl";
1798                 rockchip,grf = <&grf>;
1799                 rockchip,pmu = <&pmugrf>;
1800                 #address-cells = <0x2>;
1801                 #size-cells = <0x2>;
1802                 ranges;
1803
1804                 gpio0: gpio0@ff720000 {
1805                         compatible = "rockchip,gpio-bank";
1806                         reg = <0x0 0xff720000 0x0 0x100>;
1807                         clocks = <&pmucru PCLK_GPIO0_PMU>;
1808                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
1809
1810                         gpio-controller;
1811                         #gpio-cells = <0x2>;
1812
1813                         interrupt-controller;
1814                         #interrupt-cells = <0x2>;
1815                 };
1816
1817                 gpio1: gpio1@ff730000 {
1818                         compatible = "rockchip,gpio-bank";
1819                         reg = <0x0 0xff730000 0x0 0x100>;
1820                         clocks = <&pmucru PCLK_GPIO1_PMU>;
1821                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
1822
1823                         gpio-controller;
1824                         #gpio-cells = <0x2>;
1825
1826                         interrupt-controller;
1827                         #interrupt-cells = <0x2>;
1828                 };
1829
1830                 gpio2: gpio2@ff780000 {
1831                         compatible = "rockchip,gpio-bank";
1832                         reg = <0x0 0xff780000 0x0 0x100>;
1833                         clocks = <&cru PCLK_GPIO2>;
1834                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>;
1835
1836                         gpio-controller;
1837                         #gpio-cells = <0x2>;
1838
1839                         interrupt-controller;
1840                         #interrupt-cells = <0x2>;
1841                 };
1842
1843                 gpio3: gpio3@ff788000 {
1844                         compatible = "rockchip,gpio-bank";
1845                         reg = <0x0 0xff788000 0x0 0x100>;
1846                         clocks = <&cru PCLK_GPIO3>;
1847                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
1848
1849                         gpio-controller;
1850                         #gpio-cells = <0x2>;
1851
1852                         interrupt-controller;
1853                         #interrupt-cells = <0x2>;
1854                 };
1855
1856                 gpio4: gpio4@ff790000 {
1857                         compatible = "rockchip,gpio-bank";
1858                         reg = <0x0 0xff790000 0x0 0x100>;
1859                         clocks = <&cru PCLK_GPIO4>;
1860                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
1861
1862                         gpio-controller;
1863                         #gpio-cells = <0x2>;
1864
1865                         interrupt-controller;
1866                         #interrupt-cells = <0x2>;
1867                 };
1868
1869                 pcfg_pull_up: pcfg-pull-up {
1870                         bias-pull-up;
1871                 };
1872
1873                 pcfg_pull_down: pcfg-pull-down {
1874                         bias-pull-down;
1875                 };
1876
1877                 pcfg_pull_none: pcfg-pull-none {
1878                         bias-disable;
1879                 };
1880
1881                 pcfg_pull_up_20ma: pcfg-pull-up-20ma {
1882                         bias-pull-up;
1883                         drive-strength = <20>;
1884                 };
1885
1886                 pcfg_pull_none_20ma: pcfg-pull-none-20ma {
1887                         bias-disable;
1888                         drive-strength = <20>;
1889                 };
1890
1891                 pcfg_pull_none_18ma: pcfg-pull-none-18ma {
1892                         bias-disable;
1893                         drive-strength = <18>;
1894                 };
1895
1896                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1897                         bias-disable;
1898                         drive-strength = <12>;
1899                 };
1900
1901                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1902                         bias-pull-up;
1903                         drive-strength = <8>;
1904                 };
1905
1906                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1907                         bias-pull-down;
1908                         drive-strength = <4>;
1909                 };
1910
1911                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1912                         bias-pull-up;
1913                         drive-strength = <2>;
1914                 };
1915
1916                 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
1917                         bias-pull-down;
1918                         drive-strength = <12>;
1919                 };
1920
1921                 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
1922                         bias-disable;
1923                         drive-strength = <13>;
1924                 };
1925
1926                 pcfg_output_high: pcfg-output-high {
1927                         output-high;
1928                 };
1929
1930                 pcfg_output_low: pcfg-output-low {
1931                         output-low;
1932                 };
1933
1934                 pcfg_input: pcfg-input {
1935                         input-enable;
1936                 };
1937
1938                 emmc {
1939                         emmc_pwr: emmc-pwr {
1940                                 rockchip,pins =
1941                                         <0 5 RK_FUNC_1 &pcfg_pull_up>;
1942                         };
1943                 };
1944
1945                 gmac {
1946                         rgmii_pins: rgmii-pins {
1947                                 rockchip,pins =
1948                                         /* mac_txclk */
1949                                         <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
1950                                         /* mac_rxclk */
1951                                         <3 14 RK_FUNC_1 &pcfg_pull_none>,
1952                                         /* mac_mdio */
1953                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
1954                                         /* mac_txen */
1955                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1956                                         /* mac_clk */
1957                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
1958                                         /* mac_rxdv */
1959                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
1960                                         /* mac_mdc */
1961                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
1962                                         /* mac_rxd1 */
1963                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
1964                                         /* mac_rxd0 */
1965                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
1966                                         /* mac_txd1 */
1967                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1968                                         /* mac_txd0 */
1969                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
1970                                         /* mac_rxd3 */
1971                                         <3 3 RK_FUNC_1 &pcfg_pull_none>,
1972                                         /* mac_rxd2 */
1973                                         <3 2 RK_FUNC_1 &pcfg_pull_none>,
1974                                         /* mac_txd3 */
1975                                         <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
1976                                         /* mac_txd2 */
1977                                         <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
1978                         };
1979
1980                         rmii_pins: rmii-pins {
1981                                 rockchip,pins =
1982                                         /* mac_mdio */
1983                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
1984                                         /* mac_txen */
1985                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1986                                         /* mac_clk */
1987                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
1988                                         /* mac_rxer */
1989                                         <3 10 RK_FUNC_1 &pcfg_pull_none>,
1990                                         /* mac_rxdv */
1991                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
1992                                         /* mac_mdc */
1993                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
1994                                         /* mac_rxd1 */
1995                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
1996                                         /* mac_rxd0 */
1997                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
1998                                         /* mac_txd1 */
1999                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
2000                                         /* mac_txd0 */
2001                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
2002                         };
2003                 };
2004
2005                 i2c0 {
2006                         i2c0_xfer: i2c0-xfer {
2007                                 rockchip,pins =
2008                                         <1 15 RK_FUNC_2 &pcfg_pull_none>,
2009                                         <1 16 RK_FUNC_2 &pcfg_pull_none>;
2010                         };
2011                 };
2012
2013                 i2c1 {
2014                         i2c1_xfer: i2c1-xfer {
2015                                 rockchip,pins =
2016                                         <4 2 RK_FUNC_1 &pcfg_pull_none>,
2017                                         <4 1 RK_FUNC_1 &pcfg_pull_none>;
2018                         };
2019                 };
2020
2021                 i2c2 {
2022                         i2c2_xfer: i2c2-xfer {
2023                                 rockchip,pins =
2024                                         <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
2025                                         <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
2026                         };
2027                 };
2028
2029                 i2c3 {
2030                         i2c3_xfer: i2c3-xfer {
2031                                 rockchip,pins =
2032                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
2033                                         <4 16 RK_FUNC_1 &pcfg_pull_none>;
2034                         };
2035
2036                         i2c3_gpio: i2c3_gpio {
2037                                 rockchip,pins =
2038                                         <4 17 RK_FUNC_GPIO &pcfg_pull_none>,
2039                                         <4 16 RK_FUNC_GPIO &pcfg_pull_none>;
2040                         };
2041
2042                 };
2043
2044                 i2c4 {
2045                         i2c4_xfer: i2c4-xfer {
2046                                 rockchip,pins =
2047                                         <1 12 RK_FUNC_1 &pcfg_pull_none>,
2048                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
2049                         };
2050                 };
2051
2052                 i2c5 {
2053                         i2c5_xfer: i2c5-xfer {
2054                                 rockchip,pins =
2055                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
2056                                         <3 10 RK_FUNC_2 &pcfg_pull_none>;
2057                         };
2058                 };
2059
2060                 i2c6 {
2061                         i2c6_xfer: i2c6-xfer {
2062                                 rockchip,pins =
2063                                         <2 10 RK_FUNC_2 &pcfg_pull_none>,
2064                                         <2 9 RK_FUNC_2 &pcfg_pull_none>;
2065                         };
2066                 };
2067
2068                 i2c7 {
2069                         i2c7_xfer: i2c7-xfer {
2070                                 rockchip,pins =
2071                                         <2 8 RK_FUNC_2 &pcfg_pull_none>,
2072                                         <2 7 RK_FUNC_2 &pcfg_pull_none>;
2073                         };
2074                 };
2075
2076                 i2c8 {
2077                         i2c8_xfer: i2c8-xfer {
2078                                 rockchip,pins =
2079                                         <1 21 RK_FUNC_1 &pcfg_pull_none>,
2080                                         <1 20 RK_FUNC_1 &pcfg_pull_none>;
2081                         };
2082                 };
2083
2084                 i2s0 {
2085                         i2s0_8ch_bus: i2s0-8ch-bus {
2086                                 rockchip,pins =
2087                                         <3 24 RK_FUNC_1 &pcfg_pull_none>,
2088                                         <3 25 RK_FUNC_1 &pcfg_pull_none>,
2089                                         <3 26 RK_FUNC_1 &pcfg_pull_none>,
2090                                         <3 27 RK_FUNC_1 &pcfg_pull_none>,
2091                                         <3 28 RK_FUNC_1 &pcfg_pull_none>,
2092                                         <3 29 RK_FUNC_1 &pcfg_pull_none>,
2093                                         <3 30 RK_FUNC_1 &pcfg_pull_none>,
2094                                         <3 31 RK_FUNC_1 &pcfg_pull_none>,
2095                                         <4 0 RK_FUNC_1 &pcfg_pull_none>;
2096                         };
2097                 };
2098
2099                 i2s1 {
2100                         i2s1_2ch_bus: i2s1-2ch-bus {
2101                                 rockchip,pins =
2102                                         <4 3 RK_FUNC_1 &pcfg_pull_none>,
2103                                         <4 4 RK_FUNC_1 &pcfg_pull_none>,
2104                                         <4 5 RK_FUNC_1 &pcfg_pull_none>,
2105                                         <4 6 RK_FUNC_1 &pcfg_pull_none>,
2106                                         <4 7 RK_FUNC_1 &pcfg_pull_none>;
2107                         };
2108                 };
2109
2110                 sdio0 {
2111                         sdio0_bus1: sdio0-bus1 {
2112                                 rockchip,pins =
2113                                         <2 20 RK_FUNC_1 &pcfg_pull_up>;
2114                         };
2115
2116                         sdio0_bus4: sdio0-bus4 {
2117                                 rockchip,pins =
2118                                         <2 20 RK_FUNC_1 &pcfg_pull_up>,
2119                                         <2 21 RK_FUNC_1 &pcfg_pull_up>,
2120                                         <2 22 RK_FUNC_1 &pcfg_pull_up>,
2121                                         <2 23 RK_FUNC_1 &pcfg_pull_up>;
2122                         };
2123
2124                         sdio0_cmd: sdio0-cmd {
2125                                 rockchip,pins =
2126                                         <2 24 RK_FUNC_1 &pcfg_pull_up>;
2127                         };
2128
2129                         sdio0_clk: sdio0-clk {
2130                                 rockchip,pins =
2131                                         <2 25 RK_FUNC_1 &pcfg_pull_none>;
2132                         };
2133
2134                         sdio0_cd: sdio0-cd {
2135                                 rockchip,pins =
2136                                         <2 26 RK_FUNC_1 &pcfg_pull_up>;
2137                         };
2138
2139                         sdio0_pwr: sdio0-pwr {
2140                                 rockchip,pins =
2141                                         <2 27 RK_FUNC_1 &pcfg_pull_up>;
2142                         };
2143
2144                         sdio0_bkpwr: sdio0-bkpwr {
2145                                 rockchip,pins =
2146                                         <2 28 RK_FUNC_1 &pcfg_pull_up>;
2147                         };
2148
2149                         sdio0_wp: sdio0-wp {
2150                                 rockchip,pins =
2151                                         <0 3 RK_FUNC_1 &pcfg_pull_up>;
2152                         };
2153
2154                         sdio0_int: sdio0-int {
2155                                 rockchip,pins =
2156                                         <0 4 RK_FUNC_1 &pcfg_pull_up>;
2157                         };
2158                 };
2159
2160                 sdmmc {
2161                         sdmmc_bus1: sdmmc-bus1 {
2162                                 rockchip,pins =
2163                                         <4 8 RK_FUNC_1 &pcfg_pull_up>;
2164                         };
2165
2166                         sdmmc_bus4: sdmmc-bus4 {
2167                                 rockchip,pins =
2168                                         <4 8 RK_FUNC_1 &pcfg_pull_up>,
2169                                         <4 9 RK_FUNC_1 &pcfg_pull_up>,
2170                                         <4 10 RK_FUNC_1 &pcfg_pull_up>,
2171                                         <4 11 RK_FUNC_1 &pcfg_pull_up>;
2172                         };
2173
2174                         sdmmc_clk: sdmmc-clk {
2175                                 rockchip,pins =
2176                                         <4 12 RK_FUNC_1 &pcfg_pull_none>;
2177                         };
2178
2179                         sdmmc_cmd: sdmmc-cmd {
2180                                 rockchip,pins =
2181                                         <4 13 RK_FUNC_1 &pcfg_pull_up>;
2182                         };
2183
2184                         sdmmc_cd: sdmcc-cd {
2185                                 rockchip,pins =
2186                                         <0 7 RK_FUNC_1 &pcfg_pull_up>;
2187                         };
2188
2189                         sdmmc_wp: sdmmc-wp {
2190                                 rockchip,pins =
2191                                         <0 8 RK_FUNC_1 &pcfg_pull_up>;
2192                         };
2193                 };
2194
2195                 spdif {
2196                         spdif_bus: spdif-bus {
2197                                 rockchip,pins =
2198                                         <4 21 RK_FUNC_1 &pcfg_pull_none>;
2199                         };
2200
2201                         spdif_bus_1: spdif-bus-1 {
2202                                 rockchip,pins =
2203                                         <3 16 RK_FUNC_3 &pcfg_pull_none>;
2204                         };
2205                 };
2206
2207                 spi0 {
2208                         spi0_clk: spi0-clk {
2209                                 rockchip,pins =
2210                                         <3 6 RK_FUNC_2 &pcfg_pull_up>;
2211                         };
2212                         spi0_cs0: spi0-cs0 {
2213                                 rockchip,pins =
2214                                         <3 7 RK_FUNC_2 &pcfg_pull_up>;
2215                         };
2216                         spi0_cs1: spi0-cs1 {
2217                                 rockchip,pins =
2218                                         <3 8 RK_FUNC_2 &pcfg_pull_up>;
2219                         };
2220                         spi0_tx: spi0-tx {
2221                                 rockchip,pins =
2222                                         <3 5 RK_FUNC_2 &pcfg_pull_up>;
2223                         };
2224                         spi0_rx: spi0-rx {
2225                                 rockchip,pins =
2226                                         <3 4 RK_FUNC_2 &pcfg_pull_up>;
2227                         };
2228                 };
2229
2230                 spi1 {
2231                         spi1_clk: spi1-clk {
2232                                 rockchip,pins =
2233                                         <1 9 RK_FUNC_2 &pcfg_pull_up>;
2234                         };
2235                         spi1_cs0: spi1-cs0 {
2236                                 rockchip,pins =
2237                                         <1 10 RK_FUNC_2 &pcfg_pull_up>;
2238                         };
2239                         spi1_rx: spi1-rx {
2240                                 rockchip,pins =
2241                                         <1 7 RK_FUNC_2 &pcfg_pull_up>;
2242                         };
2243                         spi1_tx: spi1-tx {
2244                                 rockchip,pins =
2245                                         <1 8 RK_FUNC_2 &pcfg_pull_up>;
2246                         };
2247                 };
2248
2249                 spi2 {
2250                         spi2_clk: spi2-clk {
2251                                 rockchip,pins =
2252                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
2253                         };
2254                         spi2_cs0: spi2-cs0 {
2255                                 rockchip,pins =
2256                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
2257                         };
2258                         spi2_rx: spi2-rx {
2259                                 rockchip,pins =
2260                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
2261                         };
2262                         spi2_tx: spi2-tx {
2263                                 rockchip,pins =
2264                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
2265                         };
2266                 };
2267
2268                 spi3 {
2269                         spi3_clk: spi3-clk {
2270                                 rockchip,pins =
2271                                         <1 17 RK_FUNC_1 &pcfg_pull_up>;
2272                         };
2273                         spi3_cs0: spi3-cs0 {
2274                                 rockchip,pins =
2275                                         <1 18 RK_FUNC_1 &pcfg_pull_up>;
2276                         };
2277                         spi3_rx: spi3-rx {
2278                                 rockchip,pins =
2279                                         <1 15 RK_FUNC_1 &pcfg_pull_up>;
2280                         };
2281                         spi3_tx: spi3-tx {
2282                                 rockchip,pins =
2283                                         <1 16 RK_FUNC_1 &pcfg_pull_up>;
2284                         };
2285                 };
2286
2287                 spi4 {
2288                         spi4_clk: spi4-clk {
2289                                 rockchip,pins =
2290                                         <3 2 RK_FUNC_2 &pcfg_pull_up>;
2291                         };
2292                         spi4_cs0: spi4-cs0 {
2293                                 rockchip,pins =
2294                                         <3 3 RK_FUNC_2 &pcfg_pull_up>;
2295                         };
2296                         spi4_rx: spi4-rx {
2297                                 rockchip,pins =
2298                                         <3 0 RK_FUNC_2 &pcfg_pull_up>;
2299                         };
2300                         spi4_tx: spi4-tx {
2301                                 rockchip,pins =
2302                                         <3 1 RK_FUNC_2 &pcfg_pull_up>;
2303                         };
2304                 };
2305
2306                 spi5 {
2307                         spi5_clk: spi5-clk {
2308                                 rockchip,pins =
2309                                         <2 22 RK_FUNC_2 &pcfg_pull_up>;
2310                         };
2311                         spi5_cs0: spi5-cs0 {
2312                                 rockchip,pins =
2313                                         <2 23 RK_FUNC_2 &pcfg_pull_up>;
2314                         };
2315                         spi5_rx: spi5-rx {
2316                                 rockchip,pins =
2317                                         <2 20 RK_FUNC_2 &pcfg_pull_up>;
2318                         };
2319                         spi5_tx: spi5-tx {
2320                                 rockchip,pins =
2321                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
2322                         };
2323                 };
2324
2325                 tsadc {
2326                         otp_gpio: otp-gpio {
2327                                 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
2328                         };
2329
2330                         otp_out: otp-out {
2331                                 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
2332                         };
2333                 };
2334
2335                 uart0 {
2336                         uart0_xfer: uart0-xfer {
2337                                 rockchip,pins =
2338                                         <2 16 RK_FUNC_1 &pcfg_pull_up>,
2339                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
2340                         };
2341
2342                         uart0_cts: uart0-cts {
2343                                 rockchip,pins =
2344                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
2345                         };
2346
2347                         uart0_rts: uart0-rts {
2348                                 rockchip,pins =
2349                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
2350                         };
2351                 };
2352
2353                 uart1 {
2354                         uart1_xfer: uart1-xfer {
2355                                 rockchip,pins =
2356                                         <3 12 RK_FUNC_2 &pcfg_pull_up>,
2357                                         <3 13 RK_FUNC_2 &pcfg_pull_none>;
2358                         };
2359                 };
2360
2361                 uart2a {
2362                         uart2a_xfer: uart2a-xfer {
2363                                 rockchip,pins =
2364                                         <4 8 RK_FUNC_2 &pcfg_pull_up>,
2365                                         <4 9 RK_FUNC_2 &pcfg_pull_none>;
2366                         };
2367                 };
2368
2369                 uart2b {
2370                         uart2b_xfer: uart2b-xfer {
2371                                 rockchip,pins =
2372                                         <4 16 RK_FUNC_2 &pcfg_pull_up>,
2373                                         <4 17 RK_FUNC_2 &pcfg_pull_none>;
2374                         };
2375                 };
2376
2377                 uart2c {
2378                         uart2c_xfer: uart2c-xfer {
2379                                 rockchip,pins =
2380                                         <4 19 RK_FUNC_1 &pcfg_pull_up>,
2381                                         <4 20 RK_FUNC_1 &pcfg_pull_none>;
2382                         };
2383                 };
2384
2385                 uart3 {
2386                         uart3_xfer: uart3-xfer {
2387                                 rockchip,pins =
2388                                         <3 14 RK_FUNC_2 &pcfg_pull_up>,
2389                                         <3 15 RK_FUNC_2 &pcfg_pull_none>;
2390                         };
2391
2392                         uart3_cts: uart3-cts {
2393                                 rockchip,pins =
2394                                         <3 18 RK_FUNC_2 &pcfg_pull_none>;
2395                         };
2396
2397                         uart3_rts: uart3-rts {
2398                                 rockchip,pins =
2399                                         <3 19 RK_FUNC_2 &pcfg_pull_none>;
2400                         };
2401                 };
2402
2403                 uart4 {
2404                         uart4_xfer: uart4-xfer {
2405                                 rockchip,pins =
2406                                         <1 7 RK_FUNC_1 &pcfg_pull_up>,
2407                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
2408                         };
2409                 };
2410
2411                 uarthdcp {
2412                         uarthdcp_xfer: uarthdcp-xfer {
2413                                 rockchip,pins =
2414                                         <4 21 RK_FUNC_2 &pcfg_pull_up>,
2415                                         <4 22 RK_FUNC_2 &pcfg_pull_none>;
2416                         };
2417                 };
2418
2419                 pwm0 {
2420                         pwm0_pin: pwm0-pin {
2421                                 rockchip,pins =
2422                                         <4 18 RK_FUNC_1 &pcfg_pull_none>;
2423                         };
2424
2425                         vop0_pwm_pin: vop0-pwm-pin {
2426                                 rockchip,pins =
2427                                         <4 18 RK_FUNC_2 &pcfg_pull_none>;
2428                         };
2429                 };
2430
2431                 pwm1 {
2432                         pwm1_pin: pwm1-pin {
2433                                 rockchip,pins =
2434                                         <4 22 RK_FUNC_1 &pcfg_pull_none>;
2435                         };
2436
2437                         vop1_pwm_pin: vop1-pwm-pin {
2438                                 rockchip,pins =
2439                                         <4 18 RK_FUNC_3 &pcfg_pull_none>;
2440                         };
2441                 };
2442
2443                 pwm2 {
2444                         pwm2_pin: pwm2-pin {
2445                                 rockchip,pins =
2446                                         <1 19 RK_FUNC_1 &pcfg_pull_none>;
2447                         };
2448                 };
2449
2450                 pwm3a {
2451                         pwm3a_pin: pwm3a-pin {
2452                                 rockchip,pins =
2453                                         <0 6 RK_FUNC_1 &pcfg_pull_none>;
2454                         };
2455                 };
2456
2457                 pwm3b {
2458                         pwm3b_pin: pwm3b-pin {
2459                                 rockchip,pins =
2460                                         <1 14 RK_FUNC_1 &pcfg_pull_none>;
2461                         };
2462                 };
2463
2464                 edp {
2465                         edp_hpd: edp-hpd {
2466                                 rockchip,pins =
2467                                         <4 23 RK_FUNC_2 &pcfg_pull_none>;
2468                         };
2469                 };
2470
2471                 hdmi {
2472                         hdmi_i2c_xfer: hdmi-i2c-xfer {
2473                                 rockchip,pins =
2474                                         <4 17 RK_FUNC_3 &pcfg_pull_none>,
2475                                         <4 16 RK_FUNC_3 &pcfg_pull_none>;
2476                         };
2477
2478                         hdmi_cec: hdmi-cec {
2479                                 rockchip,pins =
2480                                         <4 23 RK_FUNC_1 &pcfg_pull_none>;
2481                         };
2482                 };
2483
2484                 pcie {
2485                         pcie_clkreqn: pci-clkreqn {
2486                                 rockchip,pins =
2487                                         <2 26 RK_FUNC_2 &pcfg_pull_none>;
2488                         };
2489
2490                         pcie_clkreqnb: pci-clkreqnb {
2491                                 rockchip,pins =
2492                                         <4 24 RK_FUNC_1 &pcfg_pull_none>;
2493                         };
2494                 };
2495         };
2496 };