2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/clock/rk3399-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/interrupt-controller/irq.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/power/rk3399-power.h>
49 #include <dt-bindings/thermal/thermal.h>
52 compatible = "rockchip,rk3399";
53 interrupt-parent = <&gic>;
75 compatible = "arm,psci-1.0";
111 compatible = "arm,cortex-a53", "arm,armv8";
113 enable-method = "psci";
114 #cooling-cells = <2>; /* min followed by max */
115 clocks = <&cru ARMCLKL>;
116 operating-points-v2 = <&cluster0_opp>;
121 compatible = "arm,cortex-a53", "arm,armv8";
123 enable-method = "psci";
124 clocks = <&cru ARMCLKL>;
125 operating-points-v2 = <&cluster0_opp>;
130 compatible = "arm,cortex-a53", "arm,armv8";
132 enable-method = "psci";
133 clocks = <&cru ARMCLKL>;
134 operating-points-v2 = <&cluster0_opp>;
139 compatible = "arm,cortex-a53", "arm,armv8";
141 enable-method = "psci";
142 clocks = <&cru ARMCLKL>;
143 operating-points-v2 = <&cluster0_opp>;
148 compatible = "arm,cortex-a72", "arm,armv8";
150 enable-method = "psci";
151 #cooling-cells = <2>; /* min followed by max */
152 clocks = <&cru ARMCLKB>;
153 operating-points-v2 = <&cluster1_opp>;
158 compatible = "arm,cortex-a72", "arm,armv8";
160 enable-method = "psci";
161 clocks = <&cru ARMCLKB>;
162 operating-points-v2 = <&cluster1_opp>;
166 cluster0_opp: opp_table0 {
167 compatible = "operating-points-v2";
171 opp-hz = /bits/ 64 <408000000>;
172 opp-microvolt = <900000>;
173 clock-latency-ns = <40000>;
176 opp-hz = /bits/ 64 <600000000>;
177 opp-microvolt = <900000>;
180 opp-hz = /bits/ 64 <816000000>;
181 opp-microvolt = <900000>;
184 opp-hz = /bits/ 64 <1008000000>;
185 opp-microvolt = <900000>;
189 cluster1_opp: opp_table1 {
190 compatible = "operating-points-v2";
194 opp-hz = /bits/ 64 <408000000>;
195 opp-microvolt = <900000>;
196 clock-latency-ns = <40000>;
199 opp-hz = /bits/ 64 <600000000>;
200 opp-microvolt = <900000>;
203 opp-hz = /bits/ 64 <816000000>;
204 opp-microvolt = <900000>;
207 opp-hz = /bits/ 64 <1008000000>;
208 opp-microvolt = <900000>;
211 opp-hz = /bits/ 64 <1200000000>;
212 opp-microvolt = <900000>;
217 compatible = "arm,armv8-timer";
218 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
219 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
220 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
221 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
225 compatible = "arm,armv8-pmuv3";
226 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
230 compatible = "fixed-clock";
232 clock-frequency = <24000000>;
233 clock-output-names = "xin24m";
237 compatible = "arm,amba-bus";
238 #address-cells = <2>;
242 dmac_bus: dma-controller@ff6d0000 {
243 compatible = "arm,pl330", "arm,primecell";
244 reg = <0x0 0xff6d0000 0x0 0x4000>;
245 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
246 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
248 clocks = <&cru ACLK_DMAC0_PERILP>;
249 clock-names = "apb_pclk";
252 dmac_peri: dma-controller@ff6e0000 {
253 compatible = "arm,pl330", "arm,primecell";
254 reg = <0x0 0xff6e0000 0x0 0x4000>;
255 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
256 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
258 clocks = <&cru ACLK_DMAC1_PERILP>;
259 clock-names = "apb_pclk";
264 compatible = "rockchip,rk3399-gmac";
265 reg = <0x0 0xfe300000 0x0 0x10000>;
266 rockchip,grf = <&grf>;
267 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
268 interrupt-names = "macirq";
269 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
270 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
271 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
273 clock-names = "stmmaceth", "mac_clk_rx",
274 "mac_clk_tx", "clk_mac_ref",
275 "clk_mac_refout", "aclk_mac",
277 resets = <&cru SRST_A_GMAC>;
278 reset-names = "stmmaceth";
283 compatible = "rockchip,rk3399-emmc-phy";
284 reg-offset = <0xf780>;
286 rockchip,grf = <&grf>;
290 sdio0: dwmmc@fe310000 {
291 compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc";
292 reg = <0x0 0xfe310000 0x0 0x4000>;
293 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
294 clock-freq-min-max = <400000 150000000>;
295 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
296 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
297 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
298 fifo-depth = <0x100>;
302 sdmmc: dwmmc@fe320000 {
303 compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc";
304 reg = <0x0 0xfe320000 0x0 0x4000>;
305 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
306 clock-freq-min-max = <400000 150000000>;
307 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
308 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
309 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
310 fifo-depth = <0x100>;
314 sdhci: sdhci@fe330000 {
315 compatible = "arasan,sdhci-5.1";
316 reg = <0x0 0xfe330000 0x0 0x10000>;
317 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
318 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
319 clock-names = "clk_xin", "clk_ahb";
321 phy-names = "phy_arasan";
326 compatible = "rockchip,rk3399-usb-phy";
327 rockchip,grf = <&grf>;
328 #address-cells = <1>;
331 usb2phy0: usb2-phy0 {
337 usb2phy1: usb2-phy1 {
344 usb_host0_echi: usb@fe380000 {
345 compatible = "generic-ehci";
346 reg = <0x0 0xfe380000 0x0 0x20000>;
347 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
348 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
349 clock-names = "hclk_host0", "hclk_host0_arb";
351 phy-names = "usb2_phy0";
355 usb_host0_ohci: usb@fe3a0000 {
356 compatible = "generic-ohci";
357 reg = <0x0 0xfe3a0000 0x0 0x20000>;
358 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
359 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
360 clock-names = "hclk_host0", "hclk_host0_arb";
364 usb_host1_echi: usb@fe3c0000 {
365 compatible = "generic-ehci";
366 reg = <0x0 0xfe3c0000 0x0 0x20000>;
367 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
368 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
369 clock-names = "hclk_host1", "hclk_host1_arb";
371 phy-names = "usb2_phy1";
375 usb_host1_ohci: usb@fe3e0000 {
376 compatible = "generic-ohci";
377 reg = <0x0 0xfe3e0000 0x0 0x20000>;
378 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
379 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
380 clock-names = "hclk_host1", "hclk_host1_arb";
384 usbdrd3_0: usb@fe800000 {
385 compatible = "rockchip,dwc3";
386 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
387 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
388 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
389 clock-names = "clk_usb3otg0_ref", "clk_usb3otg0_suspend",
390 "aclk_usb3otg0", "aclk_usb3_rksoc_axi_perf",
391 "aclk_usb3", "aclk_usb3_grf";
392 #address-cells = <2>;
396 usbdrd_dwc3_0: dwc3 {
397 compatible = "snps,dwc3";
398 reg = <0x0 0xfe800000 0x0 0x100000>;
399 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
402 snps,dis_enblslpm_quirk;
403 snps,phyif_utmi_16_bits;
404 snps,dis_u2_freeclk_exists_quirk;
405 snps,dis_del_phy_power_chg_quirk;
410 usbdrd3_1: usb@fe900000 {
411 compatible = "rockchip,dwc3";
412 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
413 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
414 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
415 clock-names = "clk_usb3otg1_ref", "clk_usb3otg1_suspend",
416 "aclk_usb3otg1", "aclk_usb3_rksoc_axi_perf",
417 "aclk_usb3", "aclk_usb3_grf";
418 #address-cells = <2>;
422 usbdrd_dwc3_1: dwc3 {
423 compatible = "snps,dwc3";
424 reg = <0x0 0xfe900000 0x0 0x100000>;
425 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
428 snps,dis_enblslpm_quirk;
429 snps,phyif_utmi_16_bits;
430 snps,dis_u2_freeclk_exists_quirk;
431 snps,dis_del_phy_power_chg_quirk;
436 gic: interrupt-controller@fee00000 {
437 compatible = "arm,gic-v3";
438 #interrupt-cells = <3>;
439 #address-cells = <2>;
442 interrupt-controller;
444 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
445 <0x0 0xfef00000 0 0xc0000>, /* GICR */
446 <0x0 0xfff00000 0 0x10000>, /* GICC */
447 <0x0 0xfff10000 0 0x10000>, /* GICH */
448 <0x0 0xfff20000 0 0x10000>; /* GICV */
449 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
450 its: interrupt-controller@fee20000 {
451 compatible = "arm,gic-v3-its";
453 reg = <0x0 0xfee20000 0x0 0x20000>;
457 saradc: saradc@ff100000 {
458 compatible = "rockchip,rk3399-saradc";
459 reg = <0x0 0xff100000 0x0 0x100>;
460 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
461 #io-channel-cells = <1>;
462 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
463 clock-names = "saradc", "apb_pclk";
468 compatible = "rockchip,rk3399-i2c";
469 reg = <0x0 0xff3c0000 0x0 0x1000>;
470 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
471 clock-names = "i2c", "pclk";
472 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
473 pinctrl-names = "default";
474 pinctrl-0 = <&i2c0_xfer>;
475 #address-cells = <1>;
481 compatible = "rockchip,rk3399-i2c";
482 reg = <0x0 0xff110000 0x0 0x1000>;
483 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
484 clock-names = "i2c", "pclk";
485 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
486 pinctrl-names = "default";
487 pinctrl-0 = <&i2c1_xfer>;
488 #address-cells = <1>;
494 compatible = "rockchip,rk3399-i2c";
495 reg = <0x0 0xff120000 0x0 0x1000>;
496 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
497 clock-names = "i2c", "pclk";
498 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
499 pinctrl-names = "default";
500 pinctrl-0 = <&i2c2_xfer>;
501 #address-cells = <1>;
507 compatible = "rockchip,rk3399-i2c";
508 reg = <0x0 0xff130000 0x0 0x1000>;
509 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
510 clock-names = "i2c", "pclk";
511 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
512 pinctrl-names = "default";
513 pinctrl-0 = <&i2c3_xfer>;
514 #address-cells = <1>;
520 compatible = "rockchip,rk3399-i2c";
521 reg = <0x0 0xff140000 0x0 0x1000>;
522 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
523 clock-names = "i2c", "pclk";
524 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
525 pinctrl-names = "default";
526 pinctrl-0 = <&i2c5_xfer>;
527 #address-cells = <1>;
533 compatible = "rockchip,rk3399-i2c";
534 reg = <0x0 0xff150000 0x0 0x1000>;
535 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
536 clock-names = "i2c", "pclk";
537 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
538 pinctrl-names = "default";
539 pinctrl-0 = <&i2c6_xfer>;
540 #address-cells = <1>;
546 compatible = "rockchip,rk3399-i2c";
547 reg = <0x0 0xff160000 0x0 0x1000>;
548 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
549 clock-names = "i2c", "pclk";
550 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
551 pinctrl-names = "default";
552 pinctrl-0 = <&i2c7_xfer>;
553 #address-cells = <1>;
558 uart0: serial@ff180000 {
559 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
560 reg = <0x0 0xff180000 0x0 0x100>;
561 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
562 clock-names = "baudclk", "apb_pclk";
563 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
566 pinctrl-names = "default";
567 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
571 uart1: serial@ff190000 {
572 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
573 reg = <0x0 0xff190000 0x0 0x100>;
574 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
575 clock-names = "baudclk", "apb_pclk";
576 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
579 pinctrl-names = "default";
580 pinctrl-0 = <&uart1_xfer>;
584 uart2: serial@ff1a0000 {
585 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
586 reg = <0x0 0xff1a0000 0x0 0x100>;
587 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
588 clock-names = "baudclk", "apb_pclk";
589 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
592 pinctrl-names = "default";
593 pinctrl-0 = <&uart2c_xfer>;
597 uart3: serial@ff1b0000 {
598 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
599 reg = <0x0 0xff1b0000 0x0 0x100>;
600 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
601 clock-names = "baudclk", "apb_pclk";
602 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
605 pinctrl-names = "default";
606 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
611 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
612 reg = <0x0 0xff1c0000 0x0 0x1000>;
613 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
614 clock-names = "spiclk", "apb_pclk";
615 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
616 pinctrl-names = "default";
617 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
618 #address-cells = <1>;
624 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
625 reg = <0x0 0xff1d0000 0x0 0x1000>;
626 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
627 clock-names = "spiclk", "apb_pclk";
628 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
629 pinctrl-names = "default";
630 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
631 #address-cells = <1>;
637 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
638 reg = <0x0 0xff1e0000 0x0 0x1000>;
639 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
640 clock-names = "spiclk", "apb_pclk";
641 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
642 pinctrl-names = "default";
643 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
644 #address-cells = <1>;
650 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
651 reg = <0x0 0xff1f0000 0x0 0x1000>;
652 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
653 clock-names = "spiclk", "apb_pclk";
654 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
655 pinctrl-names = "default";
656 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
657 #address-cells = <1>;
663 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
664 reg = <0x0 0xff200000 0x0 0x1000>;
665 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
666 clock-names = "spiclk", "apb_pclk";
667 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
668 pinctrl-names = "default";
669 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
670 #address-cells = <1>;
677 polling-delay-passive = <100>; /* milliseconds */
678 polling-delay = <1000>; /* milliseconds */
680 thermal-sensors = <&tsadc 0>;
683 cpu_alert0: cpu_alert0 {
684 temperature = <70000>; /* millicelsius */
685 hysteresis = <2000>; /* millicelsius */
688 cpu_alert1: cpu_alert1 {
689 temperature = <75000>; /* millicelsius */
690 hysteresis = <2000>; /* millicelsius */
694 temperature = <95000>; /* millicelsius */
695 hysteresis = <2000>; /* millicelsius */
702 trip = <&cpu_alert0>;
704 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
707 trip = <&cpu_alert1>;
709 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
715 polling-delay-passive = <100>; /* milliseconds */
716 polling-delay = <1000>; /* milliseconds */
718 thermal-sensors = <&tsadc 1>;
721 gpu_alert0: gpu_alert0 {
722 temperature = <75000>; /* millicelsius */
723 hysteresis = <2000>; /* millicelsius */
727 temperature = <950000>; /* millicelsius */
728 hysteresis = <2000>; /* millicelsius */
735 trip = <&gpu_alert0>;
737 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
743 tsadc: tsadc@ff260000 {
744 compatible = "rockchip,rk3399-tsadc";
745 reg = <0x0 0xff260000 0x0 0x100>;
746 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
747 rockchip,grf = <&grf>;
748 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
749 clock-names = "tsadc", "apb_pclk";
750 assigned-clocks = <&cru SCLK_TSADC>;
751 assigned-clock-rates = <750000>;
752 resets = <&cru SRST_TSADC>;
753 reset-names = "tsadc-apb";
754 pinctrl-names = "init", "default", "sleep";
755 pinctrl-0 = <&otp_gpio>;
756 pinctrl-1 = <&otp_out>;
757 pinctrl-2 = <&otp_gpio>;
758 #thermal-sensor-cells = <1>;
759 rockchip,hw-tshut-temp = <95000>;
763 pmu: power-management@ff31000 {
764 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
765 reg = <0x0 0xff310000 0x0 0x1000>;
767 power: power-controller {
769 compatible = "rockchip,rk3399-power-controller";
770 #power-domain-cells = <1>;
771 #address-cells = <1>;
775 reg = <RK3399_PD_CENTER>;
776 #address-cells = <1>;
780 reg = <RK3399_PD_VDU>;
783 reg = <RK3399_PD_VCODEC>;
786 reg = <RK3399_PD_IEP>;
789 reg = <RK3399_PD_RGA>;
793 reg = <RK3399_PD_VIO>;
794 #address-cells = <1>;
798 reg = <RK3399_PD_ISP0>;
801 reg = <RK3399_PD_ISP1>;
804 reg = <RK3399_PD_HDCP>;
807 reg = <RK3399_PD_VO>;
808 #address-cells = <1>;
812 reg = <RK3399_PD_VOPB>;
815 reg = <RK3399_PD_VOPL>;
820 reg = <RK3399_PD_GPU>;
825 pmugrf: syscon@ff320000 {
826 compatible = "rockchip,rk3399-pmugrf", "syscon";
827 reg = <0x0 0xff320000 0x0 0x1000>;
831 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
832 reg = <0x0 0xff350000 0x0 0x1000>;
833 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
834 clock-names = "spiclk", "apb_pclk";
835 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
836 pinctrl-names = "default";
837 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
838 #address-cells = <1>;
843 uart4: serial@ff370000 {
844 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
845 reg = <0x0 0xff370000 0x0 0x100>;
846 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
847 clock-names = "baudclk", "apb_pclk";
848 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
851 pinctrl-names = "default";
852 pinctrl-0 = <&uart4_xfer>;
857 compatible = "rockchip,rk3399-i2c";
858 reg = <0x0 0xff3d0000 0x0 0x1000>;
859 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
860 clock-names = "i2c", "pclk";
861 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
862 pinctrl-names = "default";
863 pinctrl-0 = <&i2c4_xfer>;
864 #address-cells = <1>;
870 compatible = "rockchip,rk3399-i2c";
871 reg = <0x0 0xff3e0000 0x0 0x1000>;
872 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
873 clock-names = "i2c", "pclk";
874 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
875 pinctrl-names = "default";
876 pinctrl-0 = <&i2c8_xfer>;
877 #address-cells = <1>;
883 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
884 reg = <0x0 0xff420000 0x0 0x10>;
886 pinctrl-names = "default";
887 pinctrl-0 = <&pwm0_pin>;
888 clocks = <&pmucru PCLK_RKPWM_PMU>;
894 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
895 reg = <0x0 0xff420010 0x0 0x10>;
897 pinctrl-names = "default";
898 pinctrl-0 = <&pwm1_pin>;
899 clocks = <&pmucru PCLK_RKPWM_PMU>;
905 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
906 reg = <0x0 0xff420020 0x0 0x10>;
908 pinctrl-names = "default";
909 pinctrl-0 = <&pwm2_pin>;
910 clocks = <&pmucru PCLK_RKPWM_PMU>;
916 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
917 reg = <0x0 0xff420030 0x0 0x10>;
919 pinctrl-names = "default";
920 pinctrl-0 = <&pwm3a_pin>;
921 clocks = <&pmucru PCLK_RKPWM_PMU>;
926 pmucru: pmu-clock-controller@ff750000 {
927 compatible = "rockchip,rk3399-pmucru";
928 reg = <0x0 0xff750000 0x0 0x1000>;
931 assigned-clocks = <&pmucru PLL_PPLL>;
932 assigned-clock-rates = <676000000>;
935 cru: clock-controller@ff760000 {
936 compatible = "rockchip,rk3399-cru";
937 reg = <0x0 0xff760000 0x0 0x1000>;
941 <&cru ACLK_VOP0>, <&cru HCLK_VOP0>,
942 <&cru ACLK_VOP1>, <&cru HCLK_VOP1>,
943 <&cru ARMCLKL>, <&cru ARMCLKB>,
944 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
946 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
948 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
950 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
951 assigned-clock-rates =
952 <400000000>, <200000000>,
953 <400000000>, <200000000>,
954 <816000000>, <1008000000>,
955 <594000000>, <800000000>,
957 <150000000>, <75000000>,
959 <100000000>, <100000000>,
961 <100000000>, <50000000>;
964 grf: syscon@ff770000 {
965 compatible = "rockchip,rk3399-grf", "syscon";
966 reg = <0x0 0xff770000 0x0 0x10000>;
969 wdt0: watchdog@ff840000 {
970 compatible = "snps,dw-wdt";
971 reg = <0x0 0xff840000 0x0 0x100>;
972 clocks = <&cru PCLK_WDT>;
973 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
977 spdif: spdif@ff870000 {
978 compatible = "rockchip,rk3399-spdif";
979 reg = <0x0 0xff870000 0x0 0x1000>;
980 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
981 dmas = <&dmac_bus 7>;
983 clock-names = "mclk", "hclk";
984 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
985 pinctrl-names = "default";
986 pinctrl-0 = <&spdif_bus>;
991 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
992 reg = <0x0 0xff880000 0x0 0x1000>;
993 rockchip,grf = <&grf>;
994 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
995 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
996 dma-names = "tx", "rx";
997 clock-names = "i2s_clk", "i2s_hclk";
998 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
999 pinctrl-names = "default";
1000 pinctrl-0 = <&i2s0_8ch_bus>;
1001 status = "disabled";
1004 i2s1: i2s@ff890000 {
1005 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1006 reg = <0x0 0xff890000 0x0 0x1000>;
1007 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1008 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1009 dma-names = "tx", "rx";
1010 clock-names = "i2s_clk", "i2s_hclk";
1011 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1012 pinctrl-names = "default";
1013 pinctrl-0 = <&i2s1_2ch_bus>;
1014 status = "disabled";
1017 i2s2: i2s@ff8a0000 {
1018 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1019 reg = <0x0 0xff8a0000 0x0 0x1000>;
1020 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1021 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1022 dma-names = "tx", "rx";
1023 clock-names = "i2s_clk", "i2s_hclk";
1024 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1025 status = "disabled";
1029 compatible = "arm,malit860",
1034 reg = <0x0 0xff9a0000 0x0 0x10000>;
1036 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
1037 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
1038 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1039 interrupt-names = "GPU", "JOB", "MMU";
1041 clocks = <&cru ACLK_GPU>;
1042 clock-names = "clk_mali";
1043 #cooling-cells = <2>; /* min followed by max */
1044 operating-points-v2 = <&gpu_opp_table>;
1045 status = "disabled";
1048 gpu_opp_table: gpu_opp_table {
1049 compatible = "operating-points-v2";
1053 opp-hz = /bits/ 64 <200000000>;
1054 opp-microvolt = <900000>;
1057 opp-hz = /bits/ 64 <300000000>;
1058 opp-microvolt = <900000>;
1061 opp-hz = /bits/ 64 <400000000>;
1062 opp-microvolt = <900000>;
1065 opp-hz = /bits/ 64 <500000000>;
1066 opp-microvolt = <900000>;
1070 vopl: vop@ff8f0000 {
1071 compatible = "rockchip,rk3399-vop-lit";
1072 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1073 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
1074 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1075 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1076 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1077 reset-names = "axi", "ahb", "dclk";
1078 iommus = <&vopl_mmu>;
1079 status = "disabled";
1082 #address-cells = <1>;
1085 vopl_out_mipi: endpoint@0 {
1087 remote-endpoint = <&mipi_in_vopl>;
1090 vopl_out_edp: endpoint@1 {
1092 remote-endpoint = <&edp_in_vopl>;
1097 vopl_mmu: iommu@ff8f3f00 {
1098 compatible = "rockchip,iommu";
1099 reg = <0x0 0xff8f3f00 0x0 0x100>;
1100 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
1101 interrupt-names = "vopl_mmu";
1103 status = "disabled";
1106 vopb: vop@ff900000 {
1107 compatible = "rockchip,rk3399-vop-big";
1108 reg = <0x0 0xff900000 0x0 0x3efc>;
1109 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1110 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1111 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1112 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1113 reset-names = "axi", "ahb", "dclk";
1114 iommus = <&vopb_mmu>;
1115 status = "disabled";
1118 #address-cells = <1>;
1121 vopb_out_edp: endpoint@0 {
1123 remote-endpoint = <&edp_in_vopb>;
1126 vopb_out_mipi: endpoint@1 {
1128 remote-endpoint = <&mipi_in_vopb>;
1133 vopb_mmu: iommu@ff903f00 {
1134 compatible = "rockchip,iommu";
1135 reg = <0x0 0xff903f00 0x0 0x100>;
1136 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1137 interrupt-names = "vopb_mmu";
1139 status = "disabled";
1142 mipi_dsi: mipi@ff960000 {
1143 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1144 reg = <0x0 0xff960000 0x0 0x8000>;
1145 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1146 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
1147 <&cru SCLK_DPHY_TX0_CFG>;
1148 clock-names = "ref", "pclk", "phy_cfg";
1149 rockchip,grf = <&grf>;
1150 #address-cells = <1>;
1152 status = "disabled";
1155 #address-cells = <1>;
1160 #address-cells = <1>;
1163 mipi_in_vopb: endpoint@0 {
1165 remote-endpoint = <&vopb_out_mipi>;
1167 mipi_in_vopl: endpoint@1 {
1169 remote-endpoint = <&vopl_out_mipi>;
1176 compatible = "rockchip,rk3399-edp";
1177 reg = <0x0 0xff970000 0x0 0x8000>;
1178 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1179 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1180 clock-names = "dp", "pclk";
1181 resets = <&cru SRST_P_EDP_CTRL>;
1183 rockchip,grf = <&grf>;
1184 status = "disabled";
1185 pinctrl-names = "default";
1186 pinctrl-0 = <&edp_hpd>;
1189 #address-cells = <1>;
1194 #address-cells = <1>;
1197 edp_in_vopb: endpoint@0 {
1199 remote-endpoint = <&vopb_out_edp>;
1202 edp_in_vopl: endpoint@1 {
1204 remote-endpoint = <&vopl_out_edp>;
1210 display_subsystem: display-subsystem {
1211 compatible = "rockchip,display-subsystem";
1212 ports = <&vopl_out>, <&vopb_out>;
1213 status = "disabled";
1217 compatible = "rockchip,rk3399-pinctrl";
1218 rockchip,grf = <&grf>;
1219 rockchip,pmu = <&pmugrf>;
1220 #address-cells = <0x2>;
1221 #size-cells = <0x2>;
1224 gpio0: gpio0@ff720000 {
1225 compatible = "rockchip,gpio-bank";
1226 reg = <0x0 0xff720000 0x0 0x100>;
1227 clocks = <&pmucru PCLK_GPIO0_PMU>;
1228 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1231 #gpio-cells = <0x2>;
1233 interrupt-controller;
1234 #interrupt-cells = <0x2>;
1237 gpio1: gpio1@ff730000 {
1238 compatible = "rockchip,gpio-bank";
1239 reg = <0x0 0xff730000 0x0 0x100>;
1240 clocks = <&pmucru PCLK_GPIO1_PMU>;
1241 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1244 #gpio-cells = <0x2>;
1246 interrupt-controller;
1247 #interrupt-cells = <0x2>;
1250 gpio2: gpio2@ff780000 {
1251 compatible = "rockchip,gpio-bank";
1252 reg = <0x0 0xff780000 0x0 0x100>;
1253 clocks = <&cru PCLK_GPIO2>;
1254 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1257 #gpio-cells = <0x2>;
1259 interrupt-controller;
1260 #interrupt-cells = <0x2>;
1263 gpio3: gpio3@ff788000 {
1264 compatible = "rockchip,gpio-bank";
1265 reg = <0x0 0xff788000 0x0 0x100>;
1266 clocks = <&cru PCLK_GPIO3>;
1267 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1270 #gpio-cells = <0x2>;
1272 interrupt-controller;
1273 #interrupt-cells = <0x2>;
1276 gpio4: gpio4@ff790000 {
1277 compatible = "rockchip,gpio-bank";
1278 reg = <0x0 0xff790000 0x0 0x100>;
1279 clocks = <&cru PCLK_GPIO4>;
1280 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1283 #gpio-cells = <0x2>;
1285 interrupt-controller;
1286 #interrupt-cells = <0x2>;
1289 pcfg_pull_up: pcfg-pull-up {
1293 pcfg_pull_down: pcfg-pull-down {
1297 pcfg_pull_none: pcfg-pull-none {
1301 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1303 drive-strength = <12>;
1306 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1308 drive-strength = <8>;
1311 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1313 drive-strength = <4>;
1316 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1318 drive-strength = <2>;
1321 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
1323 drive-strength = <12>;
1326 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
1328 drive-strength = <13>;
1332 emmc_pwr: emmc-pwr {
1334 <0 5 RK_FUNC_1 &pcfg_pull_up>;
1339 rgmii_pins: rgmii-pins {
1342 <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
1344 <3 14 RK_FUNC_1 &pcfg_pull_none>,
1346 <3 13 RK_FUNC_1 &pcfg_pull_none>,
1348 <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1350 <3 11 RK_FUNC_1 &pcfg_pull_none>,
1352 <3 9 RK_FUNC_1 &pcfg_pull_none>,
1354 <3 8 RK_FUNC_1 &pcfg_pull_none>,
1356 <3 7 RK_FUNC_1 &pcfg_pull_none>,
1358 <3 6 RK_FUNC_1 &pcfg_pull_none>,
1360 <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1362 <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
1364 <3 3 RK_FUNC_1 &pcfg_pull_none>,
1366 <3 2 RK_FUNC_1 &pcfg_pull_none>,
1368 <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
1370 <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
1373 rmii_pins: rmii-pins {
1376 <3 13 RK_FUNC_1 &pcfg_pull_none>,
1378 <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1380 <3 11 RK_FUNC_1 &pcfg_pull_none>,
1382 <3 10 RK_FUNC_1 &pcfg_pull_none>,
1384 <3 9 RK_FUNC_1 &pcfg_pull_none>,
1386 <3 8 RK_FUNC_1 &pcfg_pull_none>,
1388 <3 7 RK_FUNC_1 &pcfg_pull_none>,
1390 <3 6 RK_FUNC_1 &pcfg_pull_none>,
1392 <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1394 <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
1399 i2c0_xfer: i2c0-xfer {
1401 <1 15 RK_FUNC_2 &pcfg_pull_none>,
1402 <1 16 RK_FUNC_2 &pcfg_pull_none>;
1407 i2c1_xfer: i2c1-xfer {
1409 <4 2 RK_FUNC_1 &pcfg_pull_none>,
1410 <4 1 RK_FUNC_1 &pcfg_pull_none>;
1415 i2c2_xfer: i2c2-xfer {
1417 <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1418 <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
1423 i2c3_xfer: i2c3-xfer {
1425 <4 17 RK_FUNC_1 &pcfg_pull_none>,
1426 <4 16 RK_FUNC_1 &pcfg_pull_none>;
1431 i2c4_xfer: i2c4-xfer {
1433 <1 12 RK_FUNC_1 &pcfg_pull_none>,
1434 <1 11 RK_FUNC_1 &pcfg_pull_none>;
1439 i2c5_xfer: i2c5-xfer {
1441 <3 11 RK_FUNC_2 &pcfg_pull_none>,
1442 <3 10 RK_FUNC_2 &pcfg_pull_none>;
1447 i2c6_xfer: i2c6-xfer {
1449 <2 10 RK_FUNC_2 &pcfg_pull_none>,
1450 <2 9 RK_FUNC_2 &pcfg_pull_none>;
1455 i2c7_xfer: i2c7-xfer {
1457 <2 8 RK_FUNC_2 &pcfg_pull_none>,
1458 <2 7 RK_FUNC_2 &pcfg_pull_none>;
1463 i2c8_xfer: i2c8-xfer {
1465 <1 21 RK_FUNC_1 &pcfg_pull_none>,
1466 <1 20 RK_FUNC_1 &pcfg_pull_none>;
1471 i2s0_8ch_bus: i2s0-8ch-bus {
1473 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1474 <3 25 RK_FUNC_1 &pcfg_pull_none>,
1475 <3 26 RK_FUNC_1 &pcfg_pull_none>,
1476 <3 27 RK_FUNC_1 &pcfg_pull_none>,
1477 <3 28 RK_FUNC_1 &pcfg_pull_none>,
1478 <3 29 RK_FUNC_1 &pcfg_pull_none>,
1479 <3 30 RK_FUNC_1 &pcfg_pull_none>,
1480 <3 31 RK_FUNC_1 &pcfg_pull_none>,
1481 <4 0 RK_FUNC_1 &pcfg_pull_none>;
1486 i2s1_2ch_bus: i2s1-2ch-bus {
1488 <4 3 RK_FUNC_1 &pcfg_pull_none>,
1489 <4 4 RK_FUNC_1 &pcfg_pull_none>,
1490 <4 5 RK_FUNC_1 &pcfg_pull_none>,
1491 <4 6 RK_FUNC_1 &pcfg_pull_none>,
1492 <4 7 RK_FUNC_1 &pcfg_pull_none>;
1497 sdio0_bus1: sdio0-bus1 {
1499 <2 20 RK_FUNC_1 &pcfg_pull_up>;
1502 sdio0_bus4: sdio0-bus4 {
1504 <2 20 RK_FUNC_1 &pcfg_pull_up>,
1505 <2 21 RK_FUNC_1 &pcfg_pull_up>,
1506 <2 22 RK_FUNC_1 &pcfg_pull_up>,
1507 <2 23 RK_FUNC_1 &pcfg_pull_up>;
1510 sdio0_cmd: sdio0-cmd {
1512 <2 24 RK_FUNC_1 &pcfg_pull_up>;
1515 sdio0_clk: sdio0-clk {
1517 <2 25 RK_FUNC_1 &pcfg_pull_none>;
1520 sdio0_cd: sdio0-cd {
1522 <2 26 RK_FUNC_1 &pcfg_pull_up>;
1525 sdio0_pwr: sdio0-pwr {
1527 <2 27 RK_FUNC_1 &pcfg_pull_up>;
1530 sdio0_bkpwr: sdio0-bkpwr {
1532 <2 28 RK_FUNC_1 &pcfg_pull_up>;
1535 sdio0_wp: sdio0-wp {
1537 <0 3 RK_FUNC_1 &pcfg_pull_up>;
1540 sdio0_int: sdio0-int {
1542 <0 4 RK_FUNC_1 &pcfg_pull_up>;
1547 sdmmc_bus1: sdmmc-bus1 {
1549 <4 8 RK_FUNC_1 &pcfg_pull_up>;
1552 sdmmc_bus4: sdmmc-bus4 {
1554 <4 8 RK_FUNC_1 &pcfg_pull_up>,
1555 <4 9 RK_FUNC_1 &pcfg_pull_up>,
1556 <4 10 RK_FUNC_1 &pcfg_pull_up>,
1557 <4 11 RK_FUNC_1 &pcfg_pull_up>;
1560 sdmmc_clk: sdmmc-clk {
1562 <4 12 RK_FUNC_1 &pcfg_pull_none>;
1565 sdmmc_cmd: sdmmc-cmd {
1567 <4 13 RK_FUNC_1 &pcfg_pull_up>;
1570 sdmmc_cd: sdmcc-cd {
1572 <0 7 RK_FUNC_1 &pcfg_pull_up>;
1575 sdmmc_wp: sdmmc-wp {
1577 <0 8 RK_FUNC_1 &pcfg_pull_up>;
1582 spdif_bus: spdif-bus {
1584 <4 21 RK_FUNC_1 &pcfg_pull_none>;
1589 spi0_clk: spi0-clk {
1591 <3 6 RK_FUNC_2 &pcfg_pull_up>;
1593 spi0_cs0: spi0-cs0 {
1595 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1597 spi0_cs1: spi0-cs1 {
1599 <3 8 RK_FUNC_2 &pcfg_pull_up>;
1603 <3 5 RK_FUNC_2 &pcfg_pull_up>;
1607 <3 4 RK_FUNC_2 &pcfg_pull_up>;
1612 spi1_clk: spi1-clk {
1614 <1 9 RK_FUNC_2 &pcfg_pull_up>;
1616 spi1_cs0: spi1-cs0 {
1618 <1 10 RK_FUNC_2 &pcfg_pull_up>;
1622 <1 7 RK_FUNC_2 &pcfg_pull_up>;
1626 <1 8 RK_FUNC_2 &pcfg_pull_up>;
1631 spi2_clk: spi2-clk {
1633 <2 11 RK_FUNC_1 &pcfg_pull_up>;
1635 spi2_cs0: spi2-cs0 {
1637 <2 12 RK_FUNC_1 &pcfg_pull_up>;
1641 <2 9 RK_FUNC_1 &pcfg_pull_up>;
1645 <2 10 RK_FUNC_1 &pcfg_pull_up>;
1650 spi3_clk: spi3-clk {
1652 <1 17 RK_FUNC_1 &pcfg_pull_up>;
1654 spi3_cs0: spi3-cs0 {
1656 <1 18 RK_FUNC_1 &pcfg_pull_up>;
1660 <1 15 RK_FUNC_1 &pcfg_pull_up>;
1664 <1 16 RK_FUNC_1 &pcfg_pull_up>;
1669 spi4_clk: spi4-clk {
1671 <3 2 RK_FUNC_2 &pcfg_pull_up>;
1673 spi4_cs0: spi4-cs0 {
1675 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1679 <3 0 RK_FUNC_2 &pcfg_pull_up>;
1683 <3 1 RK_FUNC_2 &pcfg_pull_up>;
1688 spi5_clk: spi5-clk {
1690 <2 22 RK_FUNC_2 &pcfg_pull_up>;
1692 spi5_cs0: spi5-cs0 {
1694 <2 23 RK_FUNC_2 &pcfg_pull_up>;
1698 <2 20 RK_FUNC_2 &pcfg_pull_up>;
1702 <2 21 RK_FUNC_2 &pcfg_pull_up>;
1707 otp_gpio: otp-gpio {
1708 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
1712 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
1717 uart0_xfer: uart0-xfer {
1719 <2 16 RK_FUNC_1 &pcfg_pull_up>,
1720 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1723 uart0_cts: uart0-cts {
1725 <2 18 RK_FUNC_1 &pcfg_pull_none>;
1728 uart0_rts: uart0-rts {
1730 <2 19 RK_FUNC_1 &pcfg_pull_none>;
1735 uart1_xfer: uart1-xfer {
1737 <3 12 RK_FUNC_2 &pcfg_pull_up>,
1738 <3 13 RK_FUNC_2 &pcfg_pull_none>;
1743 uart2a_xfer: uart2a-xfer {
1745 <4 8 RK_FUNC_2 &pcfg_pull_up>,
1746 <4 9 RK_FUNC_2 &pcfg_pull_none>;
1751 uart2b_xfer: uart2b-xfer {
1753 <4 16 RK_FUNC_2 &pcfg_pull_up>,
1754 <4 17 RK_FUNC_2 &pcfg_pull_none>;
1759 uart2c_xfer: uart2c-xfer {
1761 <4 19 RK_FUNC_1 &pcfg_pull_up>,
1762 <4 20 RK_FUNC_1 &pcfg_pull_none>;
1767 uart3_xfer: uart3-xfer {
1769 <3 14 RK_FUNC_2 &pcfg_pull_up>,
1770 <3 15 RK_FUNC_2 &pcfg_pull_none>;
1773 uart3_cts: uart3-cts {
1775 <3 18 RK_FUNC_2 &pcfg_pull_none>;
1778 uart3_rts: uart3-rts {
1780 <3 19 RK_FUNC_2 &pcfg_pull_none>;
1785 uart4_xfer: uart4-xfer {
1787 <1 7 RK_FUNC_1 &pcfg_pull_up>,
1788 <1 8 RK_FUNC_1 &pcfg_pull_none>;
1793 uarthdcp_xfer: uarthdcp-xfer {
1795 <4 21 RK_FUNC_2 &pcfg_pull_up>,
1796 <4 22 RK_FUNC_2 &pcfg_pull_none>;
1801 pwm0_pin: pwm0-pin {
1803 <4 18 RK_FUNC_1 &pcfg_pull_none>;
1806 vop0_pwm_pin: vop0-pwm-pin {
1808 <4 18 RK_FUNC_2 &pcfg_pull_none>;
1813 pwm1_pin: pwm1-pin {
1815 <4 22 RK_FUNC_1 &pcfg_pull_none>;
1818 vop1_pwm_pin: vop1-pwm-pin {
1820 <4 18 RK_FUNC_3 &pcfg_pull_none>;
1825 pwm2_pin: pwm2-pin {
1827 <1 19 RK_FUNC_1 &pcfg_pull_none>;
1832 pwm3a_pin: pwm3a-pin {
1834 <0 6 RK_FUNC_1 &pcfg_pull_none>;
1839 pwm3b_pin: pwm3b-pin {
1841 <1 14 RK_FUNC_1 &pcfg_pull_none>;
1848 <4 23 RK_FUNC_2 &pcfg_pull_none>;