2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/clock/rk3399-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/interrupt-controller/irq.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/power/rk3399-power.h>
49 #include <dt-bindings/thermal/thermal.h>
52 compatible = "rockchip,rk3399";
53 interrupt-parent = <&gic>;
105 compatible = "arm,cortex-a53", "arm,armv8";
108 #cooling-cells = <2>; /* min followed by max */
113 compatible = "arm,cortex-a53", "arm,armv8";
119 compatible = "arm,cortex-a53", "arm,armv8";
125 compatible = "arm,cortex-a53", "arm,armv8";
131 compatible = "arm,cortex-a72", "arm,armv8";
134 #cooling-cells = <2>; /* min followed by max */
139 compatible = "arm,cortex-a72", "arm,armv8";
145 compatible = "arm,armv8-timer";
146 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
147 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
148 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
149 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
153 compatible = "fixed-clock";
155 clock-frequency = <24000000>;
156 clock-output-names = "xin24m";
160 compatible = "arm,amba-bus";
161 #address-cells = <2>;
165 dmac_bus: dma-controller@ff6d0000 {
166 compatible = "arm,pl330", "arm,primecell";
167 reg = <0x0 0xff6d0000 0x0 0x4000>;
168 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
169 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
171 clocks = <&cru ACLK_DMAC0_PERILP>;
172 clock-names = "apb_pclk";
175 dmac_peri: dma-controller@ff6e0000 {
176 compatible = "arm,pl330", "arm,primecell";
177 reg = <0x0 0xff6e0000 0x0 0x4000>;
178 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
179 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
181 clocks = <&cru ACLK_DMAC1_PERILP>;
182 clock-names = "apb_pclk";
187 compatible = "rockchip,rk3399-emmc-phy";
188 reg-offset = <0xf780>;
190 rockchip,grf = <&grf>;
194 sdio0: dwmmc@fe310000 {
195 compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc";
196 reg = <0x0 0xfe310000 0x0 0x4000>;
197 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
198 clock-freq-min-max = <400000 150000000>;
199 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
200 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
201 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
202 fifo-depth = <0x100>;
206 sdmmc: dwmmc@fe320000 {
207 compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc";
208 reg = <0x0 0xfe320000 0x0 0x4000>;
209 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
210 clock-freq-min-max = <400000 150000000>;
211 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
212 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
213 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
214 fifo-depth = <0x100>;
218 sdhci: sdhci@fe330000 {
219 compatible = "arasan,sdhci-5.1";
220 reg = <0x0 0xfe330000 0x0 0x10000>;
221 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
222 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
223 clock-names = "clk_xin", "clk_ahb";
225 phy-names = "phy_arasan";
229 usb_host0_echi: usb@fe380000 {
230 compatible = "generic-ehci";
231 reg = <0x0 0xfe380000 0x0 0x20000>;
232 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
233 clocks = <&cru HCLK_HOST0>;
234 clock-names = "hclk_host0";
238 usb_host0_ohci: usb@fe3a0000 {
239 compatible = "generic-ohci";
240 reg = <0x0 0xfe3a0000 0x0 0x20000>;
241 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
242 clocks = <&cru HCLK_HOST0>;
243 clock-names = "hclk_host0";
247 usb_host1_echi: usb@fe3c0000 {
248 compatible = "generic-ehci";
249 reg = <0x0 0xfe3c0000 0x0 0x20000>;
250 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
251 clocks = <&cru HCLK_HOST1>;
252 clock-names = "hclk_host1";
256 usb_host1_ohci: usb@fe3e0000 {
257 compatible = "generic-ohci";
258 reg = <0x0 0xfe3e0000 0x0 0x20000>;
259 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
260 clocks = <&cru HCLK_HOST1>;
261 clock-names = "hclk_host1";
265 gic: interrupt-controller@fee00000 {
266 compatible = "arm,gic-v3";
267 #interrupt-cells = <3>;
268 #address-cells = <2>;
271 interrupt-controller;
273 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
274 <0x0 0xfef00000 0 0xc0000>, /* GICR */
275 <0x0 0xfff00000 0 0x10000>, /* GICC */
276 <0x0 0xfff10000 0 0x10000>, /* GICH */
277 <0x0 0xfff20000 0 0x10000>; /* GICV */
278 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
279 its: interrupt-controller@fee20000 {
280 compatible = "arm,gic-v3-its";
282 reg = <0x0 0xfee20000 0x0 0x20000>;
286 saradc: saradc@ff100000 {
287 compatible = "rockchip,rk3399-saradc";
288 reg = <0x0 0xff100000 0x0 0x100>;
289 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
290 #io-channel-cells = <1>;
291 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
292 clock-names = "saradc", "apb_pclk";
297 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
298 reg = <0x0 0xff3c0000 0x0 0x1000>;
299 clocks = <&cru PCLK_I2C0_PMU>, <&cru SCLK_I2C0_PMU>;
300 clock-names = "i2c", "i2c_sclk";
301 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
302 pinctrl-names = "default";
303 pinctrl-0 = <&i2c0_xfer>;
304 #address-cells = <1>;
310 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
311 reg = <0x0 0xff110000 0x0 0x1000>;
312 clocks = <&cru PCLK_I2C1>, <&cru SCLK_I2C1>;
313 clock-names = "i2c", "i2c_sclk";
314 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
315 pinctrl-names = "default";
316 pinctrl-0 = <&i2c1_xfer>;
317 #address-cells = <1>;
323 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
324 reg = <0x0 0xff120000 0x0 0x1000>;
325 clocks = <&cru PCLK_I2C2>, <&cru SCLK_I2C2>;
326 clock-names = "i2c", "i2c_sclk";
327 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
328 pinctrl-names = "default";
329 pinctrl-0 = <&i2c2_xfer>;
330 #address-cells = <1>;
336 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
337 reg = <0x0 0xff130000 0x0 0x1000>;
338 clocks = <&cru PCLK_I2C3>, <&cru SCLK_I2C3>;
339 clock-names = "i2c", "i2c_sclk";
340 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
341 pinctrl-names = "default";
342 pinctrl-0 = <&i2c3_xfer>;
343 #address-cells = <1>;
349 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
350 reg = <0x0 0xff140000 0x0 0x1000>;
351 clocks = <&cru PCLK_I2C5>, <&cru SCLK_I2C5>;
352 clock-names = "i2c", "i2c_sclk";
353 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
354 pinctrl-names = "default";
355 pinctrl-0 = <&i2c5_xfer>;
356 #address-cells = <1>;
362 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
363 reg = <0x0 0xff150000 0x0 0x1000>;
364 clocks = <&cru PCLK_I2C6>, <&cru SCLK_I2C6>;
365 clock-names = "i2c", "i2c_sclk";
366 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
367 pinctrl-names = "default";
368 pinctrl-0 = <&i2c6_xfer>;
369 #address-cells = <1>;
375 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
376 reg = <0x0 0xff160000 0x0 0x1000>;
377 clocks = <&cru PCLK_I2C7>, <&cru SCLK_I2C7>;
378 clock-names = "i2c", "i2c_sclk";
379 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
380 pinctrl-names = "default";
381 pinctrl-0 = <&i2c7_xfer>;
382 #address-cells = <1>;
387 uart0: serial@ff180000 {
388 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
389 reg = <0x0 0xff180000 0x0 0x100>;
390 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
391 clock-names = "baudclk", "apb_pclk";
392 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
398 uart1: serial@ff190000 {
399 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
400 reg = <0x0 0xff190000 0x0 0x100>;
401 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
402 clock-names = "baudclk", "apb_pclk";
403 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
409 uart2: serial@ff1a0000 {
410 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
411 reg = <0x0 0xff1a0000 0x0 0x100>;
412 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
413 clock-names = "baudclk", "apb_pclk";
414 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
420 uart3: serial@ff1b0000 {
421 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
422 reg = <0x0 0xff1b0000 0x0 0x100>;
423 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
424 clock-names = "baudclk", "apb_pclk";
425 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
432 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
433 reg = <0x0 0xff1c0000 0x0 0x1000>;
434 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
435 clock-names = "spiclk", "apb_pclk";
436 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
437 pinctrl-names = "default";
438 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
439 #address-cells = <1>;
445 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
446 reg = <0x0 0xff1d0000 0x0 0x1000>;
447 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
448 clock-names = "spiclk", "apb_pclk";
449 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
450 pinctrl-names = "default";
451 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
452 #address-cells = <1>;
458 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
459 reg = <0x0 0xff1e0000 0x0 0x1000>;
460 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
461 clock-names = "spiclk", "apb_pclk";
462 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
463 pinctrl-names = "default";
464 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
465 #address-cells = <1>;
471 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
472 reg = <0x0 0xff1f0000 0x0 0x1000>;
473 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
474 clock-names = "spiclk", "apb_pclk";
475 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
476 pinctrl-names = "default";
477 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
478 #address-cells = <1>;
484 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
485 reg = <0x0 0xff200000 0x0 0x1000>;
486 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
487 clock-names = "spiclk", "apb_pclk";
488 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
489 pinctrl-names = "default";
490 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
491 #address-cells = <1>;
497 #include "rk3368-thermal.dtsi"
500 tsadc: tsadc@ff260000 {
501 compatible = "rockchip,rk3399-tsadc";
502 reg = <0x0 0xff260000 0x0 0x100>;
503 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
504 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
505 clock-names = "tsadc", "apb_pclk";
506 resets = <&cru SRST_TSADC>;
507 reset-names = "tsadc-apb";
508 pinctrl-names = "init", "default", "sleep";
509 pinctrl-0 = <&otp_gpio>;
510 pinctrl-1 = <&otp_out>;
511 pinctrl-2 = <&otp_gpio>;
512 #thermal-sensor-cells = <1>;
513 rockchip,hw-tshut-temp = <95000>;
517 pmu: power-management@ff31000 {
518 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
519 reg = <0x0 0xff310000 0x0 0x1000>;
521 power: power-controller {
523 compatible = "rockchip,rk3399-power-controller";
524 #power-domain-cells = <1>;
525 #address-cells = <1>;
529 reg = <RK3399_PD_CENTER>;
530 #address-cells = <1>;
534 reg = <RK3399_PD_VDU>;
537 reg = <RK3399_PD_VCODEC>;
540 reg = <RK3399_PD_IEP>;
543 reg = <RK3399_PD_RGA>;
547 reg = <RK3399_PD_VIO>;
548 #address-cells = <1>;
552 reg = <RK3399_PD_ISP0>;
555 reg = <RK3399_PD_ISP1>;
558 reg = <RK3399_PD_HDCP>;
561 reg = <RK3399_PD_VO>;
562 #address-cells = <1>;
566 reg = <RK3399_PD_VOPB>;
569 reg = <RK3399_PD_VOPL>;
574 reg = <RK3399_PD_GPU>;
579 pmugrf: syscon@ff320000 {
580 compatible = "rockchip,rk3399-pmugrf", "syscon";
581 reg = <0x0 0xff320000 0x0 0x1000>;
585 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
586 reg = <0x0 0xff350000 0x0 0x1000>;
587 clocks = <&cru SCLK_SPI3_PMU>, <&cru PCLK_SPI3_PMU>;
588 clock-names = "spiclk", "apb_pclk";
589 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
590 pinctrl-names = "default";
591 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
592 #address-cells = <1>;
597 uart4: serial@ff370000 {
598 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
599 reg = <0x0 0xff370000 0x0 0x100>;
600 clocks = <&cru SCLK_UART4_PMU>, <&cru PCLK_UART4_PMU>;
601 clock-names = "baudclk", "apb_pclk";
602 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
609 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
610 reg = <0x0 0xff3d0000 0x0 0x1000>;
611 clocks = <&cru PCLK_I2C4_PMU>, <&cru SCLK_I2C4_PMU>;
612 clock-names = "i2c", "i2c_sclk";
613 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
614 pinctrl-names = "default";
615 pinctrl-0 = <&i2c4_xfer>;
616 #address-cells = <1>;
622 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
623 reg = <0x0 0xff3e0000 0x0 0x1000>;
624 clocks = <&cru PCLK_I2C8_PMU>, <&cru SCLK_I2C8_PMU>;
625 clock-names = "i2c", "i2c_sclk";
626 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
627 pinctrl-names = "default";
628 pinctrl-0 = <&i2c8_xfer>;
629 #address-cells = <1>;
635 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
636 reg = <0x0 0xff420000 0x0 0x10>;
638 pinctrl-names = "default";
639 pinctrl-0 = <&pwm0_pin>;
640 clocks = <&cru PCLK_RKPWM_PMU>;
646 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
647 reg = <0x0 0xff420010 0x0 0x10>;
649 pinctrl-names = "default";
650 pinctrl-0 = <&pwm1_pin>;
651 clocks = <&cru PCLK_RKPWM_PMU>;
657 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
658 reg = <0x0 0xff420020 0x0 0x10>;
660 pinctrl-names = "default";
661 pinctrl-0 = <&pwm2_pin>;
662 clocks = <&cru PCLK_RKPWM_PMU>;
668 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
669 reg = <0x0 0xff420030 0x0 0x10>;
671 pinctrl-names = "default";
672 pinctrl-0 = <&pwm3a_pin>;
673 clocks = <&cru PCLK_RKPWM_PMU>;
678 pmucru: pmu-clock-controller@ff750000 {
679 compatible = "rockchip,rk3399-pmucru";
680 reg = <0x0 0xff750000 0x0 0x1000>;
681 rockchip,grf = <&pmugrf>;
686 cru: clock-controller@ff760000 {
687 compatible = "rockchip,rk3399-cru";
688 reg = <0x0 0xff760000 0x0 0x1000>;
689 rockchip,grf = <&grf>;
694 grf: syscon@ff770000 {
695 compatible = "rockchip,rk3399-grf", "syscon";
696 reg = <0x0 0xff770000 0x0 0x10000>;
699 spdif: spdif@ff870000 {
700 compatible = "rockchip,rk3399-spdif";
701 reg = <0x0 0xff870000 0x0 0x1000>;
702 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
703 dmas = <&dmac_bus 7>;
705 clock-names = "hclk", "mclk";
706 clocks = <&cru HCLK_SPDIF>, <&cru SCLK_SPDIF_8CH>;
707 pinctrl-names = "default";
708 pinctrl-0 = <&spdif_bus>;
713 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
714 reg = <0x0 0xff880000 0x0 0x1000>;
715 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
716 #address-cells = <1>;
718 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
719 dma-names = "tx", "rx";
720 clock-names = "i2s_hclk", "i2s_clk";
721 clocks = <&cru HCLK_I2S0_8CH>, <&cru SCLK_I2S0_8CH>;
722 pinctrl-names = "default";
723 pinctrl-0 = <&i2s0_8ch_bus>;
728 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
729 reg = <0x0 0xff890000 0x0 0x1000>;
730 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
731 #address-cells = <1>;
733 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
734 dma-names = "tx", "rx";
735 clock-names = "i2s_hclk", "i2s_clk";
736 clocks = <&cru HCLK_I2S1_8CH>, <&cru SCLK_I2S1_8CH>;
737 pinctrl-names = "default";
738 pinctrl-0 = <&i2s1_2ch_bus>;
743 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
744 reg = <0x0 0xff8a0000 0x0 0x1000>;
745 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
746 #address-cells = <1>;
748 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
749 dma-names = "tx", "rx";
750 clock-names = "i2s_hclk", "i2s_clk";
751 clocks = <&cru HCLK_I2S2_8CH>, <&cru SCLK_I2S2_8CH>;
756 compatible = "rockchip,rk3399-pinctrl";
757 rockchip,grf = <&grf>;
758 rockchip,pmu = <&pmugrf>;
759 #address-cells = <0x2>;
763 gpio0: gpio0@ff720000 {
764 compatible = "rockchip,gpio-bank";
765 reg = <0x0 0xff720000 0x0 0x100>;
767 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
772 interrupt-controller;
773 #interrupt-cells = <0x2>;
776 gpio1: gpio1@ff730000 {
777 compatible = "rockchip,gpio-bank";
778 reg = <0x0 0xff730000 0x0 0x100>;
780 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
785 interrupt-controller;
786 #interrupt-cells = <0x2>;
789 gpio2: gpio2@ff780000 {
790 compatible = "rockchip,gpio-bank";
791 reg = <0x0 0xff780000 0x0 0x100>;
793 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
798 interrupt-controller;
799 #interrupt-cells = <0x2>;
802 gpio3: gpio3@ff788000 {
803 compatible = "rockchip,gpio-bank";
804 reg = <0x0 0xff788000 0x0 0x100>;
806 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
811 interrupt-controller;
812 #interrupt-cells = <0x2>;
815 gpio4: gpio4@ff790000 {
816 compatible = "rockchip,gpio-bank";
817 reg = <0x0 0xff790000 0x0 0x100>;
819 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
824 interrupt-controller;
825 #interrupt-cells = <0x2>;
828 pcfg_pull_up: pcfg-pull-up {
832 pcfg_pull_down: pcfg-pull-down {
836 pcfg_pull_none: pcfg-pull-none {
840 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
842 drive-strength = <12>;
845 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
847 drive-strength = <8>;
850 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
852 drive-strength = <4>;
855 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
857 drive-strength = <2>;
860 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
862 drive-strength = <12>;
868 <0 5 RK_FUNC_1 &pcfg_pull_up>;
873 rgmii_pins: rgmii-pins {
875 <3 11 RK_FUNC_1 &pcfg_pull_none>,
876 <3 13 RK_FUNC_1 &pcfg_pull_none>,
877 <3 8 RK_FUNC_1 &pcfg_pull_none>,
878 <3 4 RK_FUNC_1 &pcfg_pull_none_12ma>,
879 <3 5 RK_FUNC_1 &pcfg_pull_none_12ma>,
880 <3 0 RK_FUNC_1 &pcfg_pull_none_12ma>,
881 <3 1 RK_FUNC_1 &pcfg_pull_none_12ma>,
882 <3 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
883 <3 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
884 <3 6 RK_FUNC_1 &pcfg_pull_none>,
885 <3 7 RK_FUNC_1 &pcfg_pull_none>,
886 <3 2 RK_FUNC_1 &pcfg_pull_none>,
887 <3 3 RK_FUNC_1 &pcfg_pull_none>,
888 <3 14 RK_FUNC_1 &pcfg_pull_none>,
889 <3 9 RK_FUNC_1 &pcfg_pull_none>;
892 rmii_pins: rmii-pins {
894 <3 11 RK_FUNC_1 &pcfg_pull_none>,
895 <3 13 RK_FUNC_1 &pcfg_pull_none>,
896 <3 8 RK_FUNC_1 &pcfg_pull_none>,
897 <3 4 RK_FUNC_1 &pcfg_pull_none_12ma>,
898 <3 5 RK_FUNC_1 &pcfg_pull_none_12ma>,
899 <3 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
900 <3 6 RK_FUNC_1 &pcfg_pull_none>,
901 <3 7 RK_FUNC_1 &pcfg_pull_none>,
902 <3 9 RK_FUNC_1 &pcfg_pull_none>,
903 <3 10 RK_FUNC_1 &pcfg_pull_none>;
908 i2c0_xfer: i2c0-xfer {
910 <1 15 RK_FUNC_2 &pcfg_pull_none>,
911 <1 16 RK_FUNC_2 &pcfg_pull_none>;
916 i2c1_xfer: i2c1-xfer {
918 <4 2 RK_FUNC_1 &pcfg_pull_none>,
919 <4 1 RK_FUNC_1 &pcfg_pull_none>;
924 i2c2_xfer: i2c2-xfer {
926 <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
927 <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
932 i2c3_xfer: i2c3-xfer {
934 <4 17 RK_FUNC_1 &pcfg_pull_none>,
935 <4 16 RK_FUNC_1 &pcfg_pull_none>;
940 i2c4_xfer: i2c4-xfer {
942 <1 12 RK_FUNC_1 &pcfg_pull_none>,
943 <1 11 RK_FUNC_1 &pcfg_pull_none>;
948 i2c5_xfer: i2c5-xfer {
950 <3 11 RK_FUNC_2 &pcfg_pull_none>,
951 <3 10 RK_FUNC_2 &pcfg_pull_none>;
956 i2c6_xfer: i2c6-xfer {
958 <2 10 RK_FUNC_2 &pcfg_pull_none>,
959 <2 9 RK_FUNC_2 &pcfg_pull_none>;
964 i2c7_xfer: i2c7-xfer {
966 <2 8 RK_FUNC_2 &pcfg_pull_none>,
967 <2 7 RK_FUNC_2 &pcfg_pull_none>;
972 i2c8_xfer: i2c8-xfer {
974 <1 21 RK_FUNC_1 &pcfg_pull_none>,
975 <1 20 RK_FUNC_1 &pcfg_pull_none>;
980 i2s0_8ch_bus: i2s0-8ch-bus {
982 <3 24 RK_FUNC_1 &pcfg_pull_none>,
983 <3 25 RK_FUNC_1 &pcfg_pull_none>,
984 <3 26 RK_FUNC_1 &pcfg_pull_none>,
985 <3 27 RK_FUNC_1 &pcfg_pull_none>,
986 <3 28 RK_FUNC_1 &pcfg_pull_none>,
987 <3 29 RK_FUNC_1 &pcfg_pull_none>,
988 <3 30 RK_FUNC_1 &pcfg_pull_none>,
989 <3 31 RK_FUNC_1 &pcfg_pull_none>,
990 <4 0 RK_FUNC_1 &pcfg_pull_none>;
995 i2s1_2ch_bus: i2s1-2ch-bus {
997 <4 3 RK_FUNC_1 &pcfg_pull_none>,
998 <4 4 RK_FUNC_1 &pcfg_pull_none>,
999 <4 5 RK_FUNC_1 &pcfg_pull_none>,
1000 <4 6 RK_FUNC_1 &pcfg_pull_none>,
1001 <4 7 RK_FUNC_1 &pcfg_pull_none>;
1006 sdio0_bus1: sdio0-bus1 {
1008 <2 20 RK_FUNC_1 &pcfg_pull_up>;
1011 sdio0_bus4: sdio0-bus4 {
1013 <2 20 RK_FUNC_1 &pcfg_pull_up>,
1014 <2 21 RK_FUNC_1 &pcfg_pull_up>,
1015 <2 22 RK_FUNC_1 &pcfg_pull_up>,
1016 <2 23 RK_FUNC_1 &pcfg_pull_up>;
1019 sdio0_cmd: sdio0-cmd {
1021 <2 24 RK_FUNC_1 &pcfg_pull_up>;
1024 sdio0_clk: sdio0-clk {
1026 <2 25 RK_FUNC_1 &pcfg_pull_none>;
1029 sdio0_cd: sdio0-cd {
1031 <2 26 RK_FUNC_1 &pcfg_pull_up>;
1034 sdio0_pwr: sdio0-pwr {
1036 <2 27 RK_FUNC_1 &pcfg_pull_up>;
1039 sdio0_bkpwr: sdio0-bkpwr {
1041 <2 28 RK_FUNC_1 &pcfg_pull_up>;
1044 sdio0_wp: sdio0-wp {
1046 <0 3 RK_FUNC_1 &pcfg_pull_up>;
1049 sdio0_int: sdio0-int {
1051 <0 4 RK_FUNC_1 &pcfg_pull_up>;
1056 sdmmc_bus1: sdmmc-bus1 {
1058 <4 8 RK_FUNC_1 &pcfg_pull_up>;
1061 sdmmc_bus4: sdmmc-bus4 {
1063 <4 8 RK_FUNC_1 &pcfg_pull_up>,
1064 <4 9 RK_FUNC_1 &pcfg_pull_up>,
1065 <4 10 RK_FUNC_1 &pcfg_pull_up>,
1066 <4 11 RK_FUNC_1 &pcfg_pull_up>;
1069 sdmmc_clk: sdmmc-clk {
1071 <4 12 RK_FUNC_1 &pcfg_pull_none>;
1074 sdmmc_cmd: sdmmc-cmd {
1076 <4 13 RK_FUNC_1 &pcfg_pull_up>;
1079 sdmmc_cd: sdmcc-cd {
1081 <0 7 RK_FUNC_1 &pcfg_pull_up>;
1084 sdmmc_wp: sdmmc-wp {
1086 <0 8 RK_FUNC_1 &pcfg_pull_up>;
1091 spdif_bus: spdif-bus {
1093 <4 21 RK_FUNC_1 &pcfg_pull_none>;
1098 spi0_clk: spi0-clk {
1100 <3 6 RK_FUNC_2 &pcfg_pull_up>;
1102 spi0_cs0: spi0-cs0 {
1104 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1106 spi0_cs1: spi0-cs1 {
1108 <3 8 RK_FUNC_2 &pcfg_pull_up>;
1112 <3 5 RK_FUNC_2 &pcfg_pull_up>;
1116 <3 4 RK_FUNC_2 &pcfg_pull_up>;
1121 spi1_clk: spi1-clk {
1123 <1 9 RK_FUNC_2 &pcfg_pull_up>;
1125 spi1_cs0: spi1-cs0 {
1127 <1 10 RK_FUNC_2 &pcfg_pull_up>;
1131 <1 7 RK_FUNC_2 &pcfg_pull_up>;
1135 <1 8 RK_FUNC_2 &pcfg_pull_up>;
1140 spi2_clk: spi2-clk {
1142 <2 11 RK_FUNC_1 &pcfg_pull_up>;
1144 spi2_cs0: spi2-cs0 {
1146 <2 12 RK_FUNC_1 &pcfg_pull_up>;
1150 <2 9 RK_FUNC_1 &pcfg_pull_up>;
1154 <2 10 RK_FUNC_1 &pcfg_pull_up>;
1159 spi3_clk: spi3-clk {
1161 <1 17 RK_FUNC_1 &pcfg_pull_up>;
1163 spi3_cs0: spi3-cs0 {
1165 <1 18 RK_FUNC_1 &pcfg_pull_up>;
1169 <1 15 RK_FUNC_1 &pcfg_pull_up>;
1173 <1 16 RK_FUNC_1 &pcfg_pull_up>;
1178 spi4_clk: spi4-clk {
1180 <3 2 RK_FUNC_2 &pcfg_pull_up>;
1182 spi4_cs0: spi4-cs0 {
1184 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1188 <3 0 RK_FUNC_2 &pcfg_pull_up>;
1192 <3 1 RK_FUNC_2 &pcfg_pull_up>;
1197 spi5_clk: spi5-clk {
1199 <2 22 RK_FUNC_2 &pcfg_pull_up>;
1201 spi5_cs0: spi5-cs0 {
1203 <2 23 RK_FUNC_2 &pcfg_pull_up>;
1207 <2 20 RK_FUNC_2 &pcfg_pull_up>;
1211 <2 21 RK_FUNC_2 &pcfg_pull_up>;
1216 otp_gpio: otp-gpio {
1217 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
1221 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
1226 uart0_xfer: uart0-xfer {
1228 <2 16 RK_FUNC_1 &pcfg_pull_up>,
1229 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1232 uart0_cts: uart0-cts {
1234 <2 18 RK_FUNC_1 &pcfg_pull_none>;
1237 uart0_rts: uart0-rts {
1239 <2 19 RK_FUNC_1 &pcfg_pull_none>;
1244 uart1_xfer: uart1-xfer {
1246 <3 12 RK_FUNC_2 &pcfg_pull_up>,
1247 <3 13 RK_FUNC_2 &pcfg_pull_none>;
1252 uart2a_xfer: uart2a-xfer {
1254 <4 8 RK_FUNC_2 &pcfg_pull_up>,
1255 <4 9 RK_FUNC_2 &pcfg_pull_none>;
1260 uart2b_xfer: uart2b-xfer {
1262 <4 16 RK_FUNC_2 &pcfg_pull_up>,
1263 <4 17 RK_FUNC_2 &pcfg_pull_none>;
1268 uart2c_xfer: uart2c-xfer {
1270 <4 19 RK_FUNC_1 &pcfg_pull_up>,
1271 <4 20 RK_FUNC_1 &pcfg_pull_none>;
1276 uart3_xfer: uart3-xfer {
1278 <3 14 RK_FUNC_2 &pcfg_pull_up>,
1279 <3 15 RK_FUNC_2 &pcfg_pull_none>;
1282 uart3_cts: uart3-cts {
1284 <3 18 RK_FUNC_2 &pcfg_pull_none>;
1287 uart3_rts: uart3-rts {
1289 <3 19 RK_FUNC_2 &pcfg_pull_none>;
1294 uart4_xfer: uart4-xfer {
1296 <1 7 RK_FUNC_1 &pcfg_pull_up>,
1297 <1 8 RK_FUNC_1 &pcfg_pull_none>;
1302 uarthdcp_xfer: uarthdcp-xfer {
1304 <4 21 RK_FUNC_2 &pcfg_pull_up>,
1305 <4 22 RK_FUNC_2 &pcfg_pull_none>;
1310 pwm0_pin: pwm0-pin {
1312 <4 18 RK_FUNC_1 &pcfg_pull_none>;
1315 vop0_pwm_pin: vop0-pwm-pin {
1317 <4 18 RK_FUNC_2 &pcfg_pull_none>;
1322 pwm1_pin: pwm1-pin {
1324 <4 22 RK_FUNC_1 &pcfg_pull_none>;
1327 vop1_pwm_pin: vop1-pwm-pin {
1329 <4 18 RK_FUNC_3 &pcfg_pull_none>;
1334 pwm2_pin: pwm2-pin {
1336 <1 19 RK_FUNC_1 &pcfg_pull_none>;
1341 pwm3a_pin: pwm3a-pin {
1343 <0 6 RK_FUNC_1 &pcfg_pull_none>;
1348 pwm3b_pin: pwm3b-pin {
1350 <1 14 RK_FUNC_1 &pcfg_pull_none>;
1355 pmic_int_l: pmic-int-l {
1357 <1 21 RK_FUNC_GPIO &pcfg_pull_up>;