2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
42 #include <dt-bindings/clock/rk3399-cru.h>
43 #include <dt-bindings/interrupt-controller/arm-gic.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/pinctrl/rockchip.h>
48 compatible = "rockchip,rk3399";
49 interrupt-parent = <&gic>;
61 compatible = "arm,psci";
96 entry-method = "psci";
98 cpu_sleep: cpu-sleep-0 {
99 compatible = "arm,idle-state";
105 compatible = "arm,cortex-a53", "arm,armv8";
107 cpu-idle-states = <&cpu_sleep>;
108 enable-method = "psci";
113 compatible = "arm,cortex-a53", "arm,armv8";
115 cpu-idle-states = <&cpu_sleep>;
116 enable-method = "psci";
121 compatible = "arm,cortex-a53", "arm,armv8";
123 cpu-idle-states = <&cpu_sleep>;
124 enable-method = "psci";
129 compatible = "arm,cortex-a53", "arm,armv8";
131 cpu-idle-states = <&cpu_sleep>;
132 enable-method = "psci";
137 compatible = "arm,cortex-a72", "arm,armv8";
139 cpu-idle-states = <&cpu_sleep>;
140 enable-method = "psci";
145 compatible = "arm,cortex-a72", "arm,armv8";
147 cpu-idle-states = <&cpu_sleep>;
148 enable-method = "psci";
153 compatible = "arm,armv8-pmuv3";
154 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
155 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
156 <&cpu_l3>, <&cpu_b0>, <&cpu_b1>;
160 compatible = "arm,armv8-timer";
163 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
165 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
167 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
169 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
170 clock-frequency = <24000000>;
174 compatible = "fixed-clock";
176 clock-frequency = <24000000>;
177 clock-output-names = "xin24m";
180 gic: interrupt-controller@fee00000 {
181 compatible = "arm,gic-v3";
182 #interrupt-cells = <3>;
183 #address-cells = <2>;
186 interrupt-controller;
188 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
189 <0x0 0xfef00000 0 0xc0000>, /* GICR */
190 <0x0 0xfff00000 0 0x10000>, /* GICC */
191 <0x0 0xfff10000 0 0x10000>, /* GICH */
192 <0x0 0xfff20000 0 0x10000>; /* GICV */
195 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
196 its: interrupt-controller@fee20000 {
197 compatible = "arm,gic-v3-its";
199 reg = <0x0 0xfee20000 0x0 0x20000>;
204 compatible = "arm,amba-bus";
205 #address-cells = <2>;
209 dmac_bus: dma-controller@ff6d0000 {
210 compatible = "arm,pl330", "arm,primecell";
211 reg = <0x0 0xff6d0000 0x0 0x4000>;
212 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
213 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
215 clocks = <&cru ACLK_DMAC0_PERILP>;
216 clock-names = "apb_pclk";
219 dmac_peri: dma-controller@ff6e0000 {
220 compatible = "arm,pl330", "arm,primecell";
221 reg = <0x0 0xff6e0000 0x0 0x4000>;
222 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
223 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
225 clocks = <&cru ACLK_DMAC1_PERILP>;
226 clock-names = "apb_pclk";
230 uart0: serial@ff180000 {
231 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
232 reg = <0x0 0xff180000 0x0 0x100>;
233 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
234 clock-names = "baudclk", "apb_pclk";
235 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
241 uart1: serial@ff190000 {
242 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
243 reg = <0x0 0xff190000 0x0 0x100>;
244 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
245 clock-names = "baudclk", "apb_pclk";
246 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
252 uart2: serial@ff1a0000 {
253 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
254 reg = <0x0 0xff1a0000 0x0 0x100>;
255 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
256 clock-names = "baudclk", "apb_pclk";
257 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
263 uart3: serial@ff1b0000 {
264 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
265 reg = <0x0 0xff1b0000 0x0 0x100>;
266 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
267 clock-names = "baudclk", "apb_pclk";
268 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
274 pmugrf: syscon@ff320000 {
275 compatible = "rockchip,rk3399-pmugrf", "syscon";
276 reg = <0x0 0xff320000 0x0 0x1000>;
279 uart4: serial@ff370000 {
280 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
281 reg = <0x0 0xff370000 0x0 0x100>;
282 clocks = <&cru SCLK_UART4_PMU>, <&cru PCLK_UART4_PMU>;
283 clock-names = "baudclk", "apb_pclk";
284 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
290 cru_pmu: pmu-clock-controller@ff750000 {
291 compatible = "rockchip,rk3399-pmu-cru";
292 reg = <0x0 0xff750000 0x0 0x1000>;
297 cru: clock-controller@ff760000 {
298 compatible = "rockchip,rk3399-cru";
299 reg = <0x0 0xff760000 0x0 0x1000>;
300 rockchip,grf = <&grf>;
305 grf: syscon@ff770000 {
306 compatible = "rockchip,rk3399-grf", "syscon";
307 reg = <0x0 0xff770000 0x0 0x10000>;
311 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
312 reg = <0x0 0xff880000 0x0 0x1000>;
313 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
314 #address-cells = <1>;
316 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
317 dma-names = "tx", "rx";
318 clock-names = "i2s_hclk", "i2s_clk";
319 clocks = <&cru HCLK_I2S0_8CH>, <&cru SCLK_I2S0_8CH>;
324 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
325 reg = <0x0 0xff890000 0x0 0x1000>;
326 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
327 #address-cells = <1>;
329 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
330 dma-names = "tx", "rx";
331 clock-names = "i2s_hclk", "i2s_clk";
332 clocks = <&cru HCLK_I2S1_8CH>, <&cru SCLK_I2S1_8CH>;
337 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
338 reg = <0x0 0xff8a0000 0x0 0x1000>;
339 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
340 #address-cells = <1>;
342 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
343 dma-names = "tx", "rx";
344 clock-names = "i2s_hclk", "i2s_clk";
345 clocks = <&cru HCLK_I2S2_8CH>, <&cru SCLK_I2S2_8CH>;
350 compatible = "rockchip,rk3399-pinctrl";
351 rockchip,grf = <&grf>;
352 rockchip,pmu = <&pmugrf>;
353 #address-cells = <0x2>;
357 gpio0: gpio0@ff720000 {
358 compatible = "rockchip,gpio-bank";
359 reg = <0x0 0xff720000 0x0 0x100>;
361 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
366 interrupt-controller;
367 #interrupt-cells = <0x2>;
370 gpio1: gpio1@ff730000 {
371 compatible = "rockchip,gpio-bank";
372 reg = <0x0 0xff730000 0x0 0x100>;
374 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
379 interrupt-controller;
380 #interrupt-cells = <0x2>;
383 gpio2: gpio2@ff780000 {
384 compatible = "rockchip,gpio-bank";
385 reg = <0x0 0xff780000 0x0 0x100>;
387 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
392 interrupt-controller;
393 #interrupt-cells = <0x2>;
396 gpio3: gpio3@ff788000 {
397 compatible = "rockchip,gpio-bank";
398 reg = <0x0 0xff788000 0x0 0x100>;
400 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
405 interrupt-controller;
406 #interrupt-cells = <0x2>;
409 gpio4: gpio4@ff790000 {
410 compatible = "rockchip,gpio-bank";
411 reg = <0x0 0xff790000 0x0 0x100>;
413 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
418 interrupt-controller;
419 #interrupt-cells = <0x2>;
422 pcfg_pull_up: pcfg-pull-up {
426 pcfg_pull_down: pcfg-pull-down {
430 pcfg_pull_none: pcfg-pull-none {
434 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
436 drive-strength = <12>;
439 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
441 drive-strength = <8>;
444 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
446 drive-strength = <4>;
449 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
451 drive-strength = <2>;
454 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
456 drive-strength = <12>;
462 <0 5 RK_FUNC_1 &pcfg_pull_up>;
467 rgmii_pins: rgmii-pins {
469 <3 11 RK_FUNC_1 &pcfg_pull_none>,
470 <3 13 RK_FUNC_1 &pcfg_pull_none>,
471 <3 8 RK_FUNC_1 &pcfg_pull_none>,
472 <3 4 RK_FUNC_1 &pcfg_pull_none_12ma>,
473 <3 5 RK_FUNC_1 &pcfg_pull_none_12ma>,
474 <3 0 RK_FUNC_1 &pcfg_pull_none_12ma>,
475 <3 1 RK_FUNC_1 &pcfg_pull_none_12ma>,
476 <3 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
477 <3 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
478 <3 6 RK_FUNC_1 &pcfg_pull_none>,
479 <3 7 RK_FUNC_1 &pcfg_pull_none>,
480 <3 2 RK_FUNC_1 &pcfg_pull_none>,
481 <3 3 RK_FUNC_1 &pcfg_pull_none>,
482 <3 14 RK_FUNC_1 &pcfg_pull_none>,
483 <3 9 RK_FUNC_1 &pcfg_pull_none>;
486 rmii_pins: rmii-pins {
488 <3 11 RK_FUNC_1 &pcfg_pull_none>,
489 <3 13 RK_FUNC_1 &pcfg_pull_none>,
490 <3 8 RK_FUNC_1 &pcfg_pull_none>,
491 <3 4 RK_FUNC_1 &pcfg_pull_none_12ma>,
492 <3 5 RK_FUNC_1 &pcfg_pull_none_12ma>,
493 <3 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
494 <3 6 RK_FUNC_1 &pcfg_pull_none>,
495 <3 7 RK_FUNC_1 &pcfg_pull_none>,
496 <3 9 RK_FUNC_1 &pcfg_pull_none>,
497 <3 10 RK_FUNC_1 &pcfg_pull_none>;
502 i2c0_xfer: i2c0-xfer {
504 <1 15 RK_FUNC_2 &pcfg_pull_none>,
505 <1 16 RK_FUNC_2 &pcfg_pull_none>;
510 i2c1_xfer: i2c1-xfer {
512 <4 2 RK_FUNC_1 &pcfg_pull_none>,
513 <4 1 RK_FUNC_1 &pcfg_pull_none>;
518 i2c2_xfer: i2c2-xfer {
520 <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
521 <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
526 i2c3_xfer: i2c3-xfer {
528 <4 17 RK_FUNC_1 &pcfg_pull_none>,
529 <4 16 RK_FUNC_1 &pcfg_pull_none>;
534 i2c4_xfer: i2c4-xfer {
536 <1 12 RK_FUNC_1 &pcfg_pull_none>,
537 <1 11 RK_FUNC_1 &pcfg_pull_none>;
542 i2c5_xfer: i2c5-xfer {
544 <3 11 RK_FUNC_2 &pcfg_pull_none>,
545 <3 10 RK_FUNC_2 &pcfg_pull_none>;
550 i2c6_xfer: i2c6-xfer {
552 <2 10 RK_FUNC_2 &pcfg_pull_none>,
553 <2 9 RK_FUNC_2 &pcfg_pull_none>;
558 i2c7_xfer: i2c7-xfer {
560 <2 8 RK_FUNC_2 &pcfg_pull_none>,
561 <2 7 RK_FUNC_2 &pcfg_pull_none>;
566 i2c8_xfer: i2c8-xfer {
568 <1 21 RK_FUNC_1 &pcfg_pull_none>,
569 <1 20 RK_FUNC_1 &pcfg_pull_none>;
574 i2s0_8ch_bus: i2s0-8ch-bus {
576 <3 24 RK_FUNC_1 &pcfg_pull_none>,
577 <3 25 RK_FUNC_1 &pcfg_pull_none>,
578 <3 26 RK_FUNC_1 &pcfg_pull_none>,
579 <3 27 RK_FUNC_1 &pcfg_pull_none>,
580 <3 28 RK_FUNC_1 &pcfg_pull_none>,
581 <3 29 RK_FUNC_1 &pcfg_pull_none>,
582 <3 30 RK_FUNC_1 &pcfg_pull_none>,
583 <3 31 RK_FUNC_1 &pcfg_pull_none>,
584 <4 0 RK_FUNC_1 &pcfg_pull_none>;
589 i2s1_2ch_bus: i2s1-2ch-bus {
591 <4 3 RK_FUNC_1 &pcfg_pull_none>,
592 <4 4 RK_FUNC_1 &pcfg_pull_none>,
593 <4 5 RK_FUNC_1 &pcfg_pull_none>,
594 <4 6 RK_FUNC_1 &pcfg_pull_none>,
595 <4 7 RK_FUNC_1 &pcfg_pull_none>;
600 sdio0_bus1: sdio0-bus1 {
602 <2 20 RK_FUNC_1 &pcfg_pull_up>;
605 sdio0_bus4: sdio0-bus4 {
607 <2 20 RK_FUNC_1 &pcfg_pull_up>,
608 <2 21 RK_FUNC_1 &pcfg_pull_up>,
609 <2 22 RK_FUNC_1 &pcfg_pull_up>,
610 <2 23 RK_FUNC_1 &pcfg_pull_up>;
613 sdio0_cmd: sdio0-cmd {
615 <2 24 RK_FUNC_1 &pcfg_pull_up>;
618 sdio0_clk: sdio0-clk {
620 <2 25 RK_FUNC_1 &pcfg_pull_none>;
625 <2 26 RK_FUNC_1 &pcfg_pull_up>;
628 sdio0_pwr: sdio0-pwr {
630 <2 27 RK_FUNC_1 &pcfg_pull_up>;
633 sdio0_bkpwr: sdio0-bkpwr {
635 <2 28 RK_FUNC_1 &pcfg_pull_up>;
640 <0 3 RK_FUNC_1 &pcfg_pull_up>;
643 sdio0_int: sdio0-int {
645 <0 4 RK_FUNC_1 &pcfg_pull_up>;
650 sdmmc_bus1: sdmmc-bus1 {
652 <4 8 RK_FUNC_1 &pcfg_pull_up>;
655 sdmmc_bus4: sdmmc-bus4 {
657 <4 8 RK_FUNC_1 &pcfg_pull_up>,
658 <4 9 RK_FUNC_1 &pcfg_pull_up>,
659 <4 10 RK_FUNC_1 &pcfg_pull_up>,
660 <4 11 RK_FUNC_1 &pcfg_pull_up>;
663 sdmmc_clk: sdmmc-clk {
665 <4 12 RK_FUNC_1 &pcfg_pull_none>;
668 sdmmc_cmd: sdmmc-cmd {
670 <4 13 RK_FUNC_1 &pcfg_pull_up>;
675 <0 7 RK_FUNC_1 &pcfg_pull_up>;
680 <0 8 RK_FUNC_1 &pcfg_pull_up>;
687 <3 6 RK_FUNC_2 &pcfg_pull_up>;
691 <3 7 RK_FUNC_2 &pcfg_pull_up>;
695 <3 8 RK_FUNC_2 &pcfg_pull_up>;
699 <3 5 RK_FUNC_2 &pcfg_pull_up>;
703 <3 4 RK_FUNC_2 &pcfg_pull_up>;
710 <1 9 RK_FUNC_2 &pcfg_pull_up>;
714 <1 10 RK_FUNC_2 &pcfg_pull_up>;
718 <1 7 RK_FUNC_2 &pcfg_pull_up>;
722 <1 8 RK_FUNC_2 &pcfg_pull_up>;
729 <2 11 RK_FUNC_1 &pcfg_pull_up>;
733 <2 12 RK_FUNC_1 &pcfg_pull_up>;
737 <2 9 RK_FUNC_1 &pcfg_pull_up>;
741 <2 10 RK_FUNC_1 &pcfg_pull_up>;
748 <1 17 RK_FUNC_1 &pcfg_pull_up>;
752 <1 18 RK_FUNC_1 &pcfg_pull_up>;
756 <1 15 RK_FUNC_1 &pcfg_pull_up>;
760 <1 16 RK_FUNC_1 &pcfg_pull_up>;
767 <3 2 RK_FUNC_2 &pcfg_pull_up>;
771 <3 3 RK_FUNC_2 &pcfg_pull_up>;
775 <3 0 RK_FUNC_2 &pcfg_pull_up>;
779 <3 1 RK_FUNC_2 &pcfg_pull_up>;
786 <2 22 RK_FUNC_2 &pcfg_pull_up>;
790 <2 23 RK_FUNC_2 &pcfg_pull_up>;
794 <2 20 RK_FUNC_2 &pcfg_pull_up>;
798 <2 21 RK_FUNC_2 &pcfg_pull_up>;
803 uart0_xfer: uart0-xfer {
805 <2 16 RK_FUNC_1 &pcfg_pull_up>,
806 <2 17 RK_FUNC_1 &pcfg_pull_none>;
809 uart0_cts: uart0-cts {
811 <2 18 RK_FUNC_1 &pcfg_pull_none>;
814 uart0_rts: uart0-rts {
816 <2 19 RK_FUNC_1 &pcfg_pull_none>;
821 uart1_xfer: uart1-xfer {
823 <3 12 RK_FUNC_2 &pcfg_pull_up>,
824 <3 13 RK_FUNC_2 &pcfg_pull_none>;
829 uart2a_xfer: uart2a-xfer {
831 <4 8 RK_FUNC_2 &pcfg_pull_up>,
832 <4 9 RK_FUNC_2 &pcfg_pull_none>;
837 uart2b_xfer: uart2b-xfer {
839 <4 16 RK_FUNC_2 &pcfg_pull_up>,
840 <4 17 RK_FUNC_2 &pcfg_pull_none>;
845 uart2c_xfer: uart2c-xfer {
847 <4 19 RK_FUNC_1 &pcfg_pull_up>,
848 <4 20 RK_FUNC_1 &pcfg_pull_none>;
853 uart3_xfer: uart3-xfer {
855 <3 14 RK_FUNC_2 &pcfg_pull_up>,
856 <3 15 RK_FUNC_2 &pcfg_pull_none>;
859 uart3_cts: uart3-cts {
861 <3 18 RK_FUNC_2 &pcfg_pull_none>;
864 uart3_rts: uart3-rts {
866 <3 19 RK_FUNC_2 &pcfg_pull_none>;
871 uart4_xfer: uart4-xfer {
873 <1 7 RK_FUNC_1 &pcfg_pull_up>,
874 <1 8 RK_FUNC_1 &pcfg_pull_none>;
879 uarthdcp_xfer: uarthdcp-xfer {
881 <4 21 RK_FUNC_2 &pcfg_pull_up>,
882 <4 22 RK_FUNC_2 &pcfg_pull_none>;
889 <4 18 RK_FUNC_1 &pcfg_pull_none>;
892 vop0_pwm_pin: vop0-pwm-pin {
894 <4 18 RK_FUNC_2 &pcfg_pull_none>;
901 <4 22 RK_FUNC_1 &pcfg_pull_none>;
904 vop1_pwm_pin: vop1-pwm-pin {
906 <4 18 RK_FUNC_3 &pcfg_pull_none>;