2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/clock/rk3399-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/interrupt-controller/irq.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/power/rk3399-power.h>
49 #include <dt-bindings/soc/rockchip,boot-mode.h>
50 #include <dt-bindings/suspend/rockchip-rk3399.h>
51 #include <dt-bindings/thermal/thermal.h>
53 #include "rk3399-dram-default-timing.dtsi"
56 compatible = "rockchip,rk3399";
58 interrupt-parent = <&gic>;
111 compatible = "arm,cortex-a53", "arm,armv8";
113 enable-method = "psci";
114 #cooling-cells = <2>; /* min followed by max */
115 dynamic-power-coefficient = <100>;
116 clocks = <&cru ARMCLKL>;
117 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
122 compatible = "arm,cortex-a53", "arm,armv8";
124 enable-method = "psci";
125 clocks = <&cru ARMCLKL>;
126 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
131 compatible = "arm,cortex-a53", "arm,armv8";
133 enable-method = "psci";
134 clocks = <&cru ARMCLKL>;
135 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
140 compatible = "arm,cortex-a53", "arm,armv8";
142 enable-method = "psci";
143 clocks = <&cru ARMCLKL>;
144 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
149 compatible = "arm,cortex-a72", "arm,armv8";
151 enable-method = "psci";
152 #cooling-cells = <2>; /* min followed by max */
153 dynamic-power-coefficient = <436>;
154 clocks = <&cru ARMCLKB>;
155 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
160 compatible = "arm,cortex-a72", "arm,armv8";
162 enable-method = "psci";
163 clocks = <&cru ARMCLKB>;
164 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
168 entry-method = "psci";
170 CPU_SLEEP: cpu-sleep {
171 compatible = "arm,idle-state";
173 arm,psci-suspend-param = <0x0010000>;
174 entry-latency-us = <120>;
175 exit-latency-us = <250>;
176 min-residency-us = <900>;
179 CLUSTER_SLEEP: cluster-sleep {
180 compatible = "arm,idle-state";
182 arm,psci-suspend-param = <0x1010000>;
183 entry-latency-us = <400>;
184 exit-latency-us = <500>;
185 min-residency-us = <2000>;
193 min-volt = <800000>; /* uV */
194 min-freq = <408000>; /* KHz */
195 leakage-adjust-volt = <
199 nvmem-cells = <&cpul_leakage>;
200 nvmem-cell-names = "cpu_leakage";
204 min-volt = <800000>; /* uV */
205 min-freq = <408000>; /* KHz */
206 leakage-adjust-volt = <
210 nvmem-cells = <&cpub_leakage>;
211 nvmem-cell-names = "cpu_leakage";
216 compatible = "arm,cortex-a53-pmu";
217 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
221 compatible = "arm,cortex-a72-pmu";
222 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;
226 compatible = "arm,psci-1.0";
231 compatible = "arm,armv8-timer";
232 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
233 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
234 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
235 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
239 compatible = "fixed-clock";
240 clock-frequency = <24000000>;
241 clock-output-names = "xin24m";
246 compatible = "arm,amba-bus";
247 #address-cells = <2>;
251 dmac_bus: dma-controller@ff6d0000 {
252 compatible = "arm,pl330", "arm,primecell";
253 reg = <0x0 0xff6d0000 0x0 0x4000>;
254 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
255 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
257 clocks = <&cru ACLK_DMAC0_PERILP>;
258 clock-names = "apb_pclk";
259 peripherals-req-type-burst;
262 dmac_peri: dma-controller@ff6e0000 {
263 compatible = "arm,pl330", "arm,primecell";
264 reg = <0x0 0xff6e0000 0x0 0x4000>;
265 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
266 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>;
268 clocks = <&cru ACLK_DMAC1_PERILP>;
269 clock-names = "apb_pclk";
270 peripherals-req-type-burst;
274 gmac: ethernet@fe300000 {
275 compatible = "rockchip,rk3399-gmac";
276 reg = <0x0 0xfe300000 0x0 0x10000>;
277 rockchip,grf = <&grf>;
278 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
279 interrupt-names = "macirq";
280 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
281 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
282 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
284 clock-names = "stmmaceth", "mac_clk_rx",
285 "mac_clk_tx", "clk_mac_ref",
286 "clk_mac_refout", "aclk_mac",
288 resets = <&cru SRST_A_GMAC>;
289 reset-names = "stmmaceth";
290 power-domains = <&power RK3399_PD_GMAC>;
294 sdio0: dwmmc@fe310000 {
295 compatible = "rockchip,rk3399-dw-mshc",
296 "rockchip,rk3288-dw-mshc";
297 reg = <0x0 0xfe310000 0x0 0x4000>;
298 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>;
299 clock-freq-min-max = <400000 150000000>;
300 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
301 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
302 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
303 fifo-depth = <0x100>;
304 power-domains = <&power RK3399_PD_SDIOAUDIO>;
308 sdmmc: dwmmc@fe320000 {
309 compatible = "rockchip,rk3399-dw-mshc",
310 "rockchip,rk3288-dw-mshc";
311 reg = <0x0 0xfe320000 0x0 0x4000>;
312 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
313 clock-freq-min-max = <400000 150000000>;
314 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
315 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
316 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
317 fifo-depth = <0x100>;
318 power-domains = <&power RK3399_PD_SD>;
322 sdhci: sdhci@fe330000 {
323 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
324 reg = <0x0 0xfe330000 0x0 0x10000>;
325 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
326 arasan,soc-ctl-syscon = <&grf>;
327 assigned-clocks = <&cru SCLK_EMMC>;
328 assigned-clock-rates = <200000000>;
329 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
330 clock-names = "clk_xin", "clk_ahb";
331 clock-output-names = "emmc_cardclock";
334 phy-names = "phy_arasan";
335 power-domains = <&power RK3399_PD_EMMC>;
339 usb_host0_ehci: usb@fe380000 {
340 compatible = "generic-ehci";
341 reg = <0x0 0xfe380000 0x0 0x20000>;
342 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
343 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
344 <&cru SCLK_USBPHY0_480M_SRC>;
345 clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m";
346 phys = <&u2phy0_host>;
348 power-domains = <&power RK3399_PD_PERIHP>;
352 usb_host0_ohci: usb@fe3a0000 {
353 compatible = "generic-ohci";
354 reg = <0x0 0xfe3a0000 0x0 0x20000>;
355 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
356 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
357 <&cru SCLK_USBPHY0_480M_SRC>;
358 clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m";
359 phys = <&u2phy0_host>;
361 power-domains = <&power RK3399_PD_PERIHP>;
365 usb_host1_ehci: usb@fe3c0000 {
366 compatible = "generic-ehci";
367 reg = <0x0 0xfe3c0000 0x0 0x20000>;
368 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
369 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
370 <&cru SCLK_USBPHY1_480M_SRC>;
371 clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m";
372 phys = <&u2phy1_host>;
374 power-domains = <&power RK3399_PD_PERIHP>;
378 usb_host1_ohci: usb@fe3e0000 {
379 compatible = "generic-ohci";
380 reg = <0x0 0xfe3e0000 0x0 0x20000>;
381 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
382 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
383 <&cru SCLK_USBPHY1_480M_SRC>;
384 clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m";
385 phys = <&u2phy1_host>;
387 power-domains = <&power RK3399_PD_PERIHP>;
391 usbdrd3_0: usb@fe800000 {
392 compatible = "rockchip,rk3399-dwc3";
393 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
394 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_GRF>;
395 clock-names = "ref_clk", "suspend_clk",
396 "bus_clk", "grf_clk";
397 power-domains = <&power RK3399_PD_USB3>;
398 resets = <&cru SRST_A_USB3_OTG0>;
399 reset-names = "usb3-otg";
400 #address-cells = <2>;
404 usbdrd_dwc3_0: dwc3@fe800000 {
405 compatible = "snps,dwc3";
406 reg = <0x0 0xfe800000 0x0 0x100000>;
407 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
409 phys = <&u2phy0_otg>, <&tcphy0_usb3>;
410 phy-names = "usb2-phy", "usb3-phy";
411 phy_type = "utmi_wide";
412 snps,dis_enblslpm_quirk;
413 snps,dis-u2-freeclk-exists-quirk;
414 snps,dis_u2_susphy_quirk;
415 snps,dis-del-phy-power-chg-quirk;
416 snps,xhci-slow-suspend-quirk;
421 usbdrd3_1: usb@fe900000 {
422 compatible = "rockchip,rk3399-dwc3";
423 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
424 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_GRF>;
425 clock-names = "ref_clk", "suspend_clk",
426 "bus_clk", "grf_clk";
427 power-domains = <&power RK3399_PD_USB3>;
428 resets = <&cru SRST_A_USB3_OTG1>;
429 reset-names = "usb3-otg";
430 #address-cells = <2>;
434 usbdrd_dwc3_1: dwc3@fe900000 {
435 compatible = "snps,dwc3";
436 reg = <0x0 0xfe900000 0x0 0x100000>;
437 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
439 phys = <&u2phy1_otg>, <&tcphy1_usb3>;
440 phy-names = "usb2-phy", "usb3-phy";
441 phy_type = "utmi_wide";
442 snps,dis_enblslpm_quirk;
443 snps,dis-u2-freeclk-exists-quirk;
444 snps,dis_u2_susphy_quirk;
445 snps,dis-del-phy-power-chg-quirk;
446 snps,xhci-slow-suspend-quirk;
451 cdn_dp: dp@fec00000 {
452 compatible = "rockchip,rk3399-cdn-dp";
453 reg = <0x0 0xfec00000 0x0 0x100000>;
454 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
455 clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
456 <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
457 clock-names = "core-clk", "pclk", "spdif", "grf";
458 assigned-clocks = <&cru SCLK_DP_CORE>;
459 assigned-clock-rates = <100000000>;
460 power-domains = <&power RK3399_PD_HDCP>;
461 phys = <&tcphy0_dp>, <&tcphy1_dp>;
462 resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>,
463 <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>;
464 reset-names = "spdif", "dptx", "apb", "core";
465 rockchip,grf = <&grf>;
466 #address-cells = <1>;
468 #sound-dai-cells = <1>;
472 #address-cells = <1>;
476 #address-cells = <1>;
478 dp_in_vopb: endpoint@0 {
480 remote-endpoint = <&vopb_out_dp>;
483 dp_in_vopl: endpoint@1 {
485 remote-endpoint = <&vopl_out_dp>;
491 gic: interrupt-controller@fee00000 {
492 compatible = "arm,gic-v3";
493 #interrupt-cells = <4>;
494 #address-cells = <2>;
497 interrupt-controller;
499 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
500 <0x0 0xfef00000 0 0xc0000>, /* GICR */
501 <0x0 0xfff00000 0 0x10000>, /* GICC */
502 <0x0 0xfff10000 0 0x10000>, /* GICH */
503 <0x0 0xfff20000 0 0x10000>; /* GICV */
504 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
505 its: interrupt-controller@fee20000 {
506 compatible = "arm,gic-v3-its";
508 reg = <0x0 0xfee20000 0x0 0x20000>;
512 ppi_cluster0: interrupt-partition-0 {
513 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
516 ppi_cluster1: interrupt-partition-1 {
517 affinity = <&cpu_b0 &cpu_b1>;
522 saradc: saradc@ff100000 {
523 compatible = "rockchip,rk3399-saradc";
524 reg = <0x0 0xff100000 0x0 0x100>;
525 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>;
526 #io-channel-cells = <1>;
527 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
528 clock-names = "saradc", "apb_pclk";
529 resets = <&cru SRST_P_SARADC>;
530 reset-names = "saradc-apb";
535 compatible = "rockchip,rk3399-i2c";
536 reg = <0x0 0xff3c0000 0x0 0x1000>;
537 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
538 clock-names = "i2c", "pclk";
539 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
540 pinctrl-names = "default";
541 pinctrl-0 = <&i2c0_xfer>;
542 #address-cells = <1>;
548 compatible = "rockchip,rk3399-i2c";
549 reg = <0x0 0xff110000 0x0 0x1000>;
550 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
551 clock-names = "i2c", "pclk";
552 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>;
553 pinctrl-names = "default";
554 pinctrl-0 = <&i2c1_xfer>;
555 #address-cells = <1>;
561 compatible = "rockchip,rk3399-i2c";
562 reg = <0x0 0xff120000 0x0 0x1000>;
563 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
564 clock-names = "i2c", "pclk";
565 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>;
566 pinctrl-names = "default";
567 pinctrl-0 = <&i2c2_xfer>;
568 #address-cells = <1>;
574 compatible = "rockchip,rk3399-i2c";
575 reg = <0x0 0xff130000 0x0 0x1000>;
576 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
577 clock-names = "i2c", "pclk";
578 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>;
579 pinctrl-names = "default";
580 pinctrl-0 = <&i2c3_xfer>;
581 #address-cells = <1>;
587 compatible = "rockchip,rk3399-i2c";
588 reg = <0x0 0xff140000 0x0 0x1000>;
589 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
590 clock-names = "i2c", "pclk";
591 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>;
592 pinctrl-names = "default";
593 pinctrl-0 = <&i2c5_xfer>;
594 #address-cells = <1>;
600 compatible = "rockchip,rk3399-i2c";
601 reg = <0x0 0xff150000 0x0 0x1000>;
602 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
603 clock-names = "i2c", "pclk";
604 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>;
605 pinctrl-names = "default";
606 pinctrl-0 = <&i2c6_xfer>;
607 #address-cells = <1>;
613 compatible = "rockchip,rk3399-i2c";
614 reg = <0x0 0xff160000 0x0 0x1000>;
615 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
616 clock-names = "i2c", "pclk";
617 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>;
618 pinctrl-names = "default";
619 pinctrl-0 = <&i2c7_xfer>;
620 #address-cells = <1>;
625 uart0: serial@ff180000 {
626 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
627 reg = <0x0 0xff180000 0x0 0x100>;
628 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
629 clock-names = "baudclk", "apb_pclk";
630 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
633 pinctrl-names = "default";
634 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
638 uart1: serial@ff190000 {
639 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
640 reg = <0x0 0xff190000 0x0 0x100>;
641 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
642 clock-names = "baudclk", "apb_pclk";
643 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>;
646 pinctrl-names = "default";
647 pinctrl-0 = <&uart1_xfer>;
651 uart2: serial@ff1a0000 {
652 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
653 reg = <0x0 0xff1a0000 0x0 0x100>;
654 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
655 clock-names = "baudclk", "apb_pclk";
656 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
659 pinctrl-names = "default";
660 pinctrl-0 = <&uart2c_xfer>;
664 uart3: serial@ff1b0000 {
665 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
666 reg = <0x0 0xff1b0000 0x0 0x100>;
667 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
668 clock-names = "baudclk", "apb_pclk";
669 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
672 pinctrl-names = "default";
673 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
678 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
679 reg = <0x0 0xff1c0000 0x0 0x1000>;
680 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
681 clock-names = "spiclk", "apb_pclk";
682 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>;
683 pinctrl-names = "default";
684 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
685 #address-cells = <1>;
691 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
692 reg = <0x0 0xff1d0000 0x0 0x1000>;
693 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
694 clock-names = "spiclk", "apb_pclk";
695 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>;
696 pinctrl-names = "default";
697 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
698 #address-cells = <1>;
704 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
705 reg = <0x0 0xff1e0000 0x0 0x1000>;
706 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
707 clock-names = "spiclk", "apb_pclk";
708 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>;
709 pinctrl-names = "default";
710 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
711 #address-cells = <1>;
717 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
718 reg = <0x0 0xff1f0000 0x0 0x1000>;
719 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
720 clock-names = "spiclk", "apb_pclk";
721 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>;
722 pinctrl-names = "default";
723 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
724 #address-cells = <1>;
730 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
731 reg = <0x0 0xff200000 0x0 0x1000>;
732 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
733 clock-names = "spiclk", "apb_pclk";
734 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
735 pinctrl-names = "default";
736 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
737 #address-cells = <1>;
742 thermal_zones: thermal-zones {
743 soc_thermal: soc-thermal {
744 polling-delay-passive = <20>; /* milliseconds */
745 polling-delay = <1000>; /* milliseconds */
746 sustainable-power = <1000>; /* milliwatts */
748 thermal-sensors = <&tsadc 0>;
751 threshold: trip-point@0 {
752 temperature = <70000>; /* millicelsius */
753 hysteresis = <2000>; /* millicelsius */
756 target: trip-point@1 {
757 temperature = <85000>; /* millicelsius */
758 hysteresis = <2000>; /* millicelsius */
762 temperature = <95000>; /* millicelsius */
763 hysteresis = <2000>; /* millicelsius */
772 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
773 contribution = <4096>;
778 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
779 contribution = <1024>;
784 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
785 contribution = <4096>;
790 gpu_thermal: gpu-thermal {
791 polling-delay-passive = <100>; /* milliseconds */
792 polling-delay = <1000>; /* milliseconds */
794 thermal-sensors = <&tsadc 1>;
798 tsadc: tsadc@ff260000 {
799 compatible = "rockchip,rk3399-tsadc";
800 reg = <0x0 0xff260000 0x0 0x100>;
801 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
802 rockchip,grf = <&grf>;
803 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
804 clock-names = "tsadc", "apb_pclk";
805 assigned-clocks = <&cru SCLK_TSADC>;
806 assigned-clock-rates = <750000>;
807 resets = <&cru SRST_TSADC>;
808 reset-names = "tsadc-apb";
809 pinctrl-names = "init", "default", "sleep";
810 pinctrl-0 = <&otp_gpio>;
811 pinctrl-1 = <&otp_out>;
812 pinctrl-2 = <&otp_gpio>;
813 #thermal-sensor-cells = <1>;
814 rockchip,hw-tshut-temp = <95000>;
818 qos_emmc: qos@ffa58000 {
819 compatible = "syscon";
820 reg = <0x0 0xffa58000 0x0 0x20>;
823 qos_gmac: qos@ffa5c000 {
824 compatible = "syscon";
825 reg = <0x0 0xffa5c000 0x0 0x20>;
828 qos_pcie: qos@ffa60080 {
829 compatible = "syscon";
830 reg = <0x0 0xffa60080 0x0 0x20>;
833 qos_usb_host0: qos@ffa60100 {
834 compatible = "syscon";
835 reg = <0x0 0xffa60100 0x0 0x20>;
838 qos_usb_host1: qos@ffa60180 {
839 compatible = "syscon";
840 reg = <0x0 0xffa60180 0x0 0x20>;
843 qos_usb_otg0: qos@ffa70000 {
844 compatible = "syscon";
845 reg = <0x0 0xffa70000 0x0 0x20>;
848 qos_usb_otg1: qos@ffa70080 {
849 compatible = "syscon";
850 reg = <0x0 0xffa70080 0x0 0x20>;
853 qos_sd: qos@ffa74000 {
854 compatible = "syscon";
855 reg = <0x0 0xffa74000 0x0 0x20>;
858 qos_sdioaudio: qos@ffa76000 {
859 compatible = "syscon";
860 reg = <0x0 0xffa76000 0x0 0x20>;
863 qos_hdcp: qos@ffa90000 {
864 compatible = "syscon";
865 reg = <0x0 0xffa90000 0x0 0x20>;
868 qos_iep: qos@ffa98000 {
869 compatible = "syscon";
870 reg = <0x0 0xffa98000 0x0 0x20>;
873 qos_isp0_m0: qos@ffaa0000 {
874 compatible = "syscon";
875 reg = <0x0 0xffaa0000 0x0 0x20>;
878 qos_isp0_m1: qos@ffaa0080 {
879 compatible = "syscon";
880 reg = <0x0 0xffaa0080 0x0 0x20>;
883 qos_isp1_m0: qos@ffaa8000 {
884 compatible = "syscon";
885 reg = <0x0 0xffaa8000 0x0 0x20>;
888 qos_isp1_m1: qos@ffaa8080 {
889 compatible = "syscon";
890 reg = <0x0 0xffaa8080 0x0 0x20>;
893 qos_rga_r: qos@ffab0000 {
894 compatible = "syscon";
895 reg = <0x0 0xffab0000 0x0 0x20>;
898 qos_rga_w: qos@ffab0080 {
899 compatible = "syscon";
900 reg = <0x0 0xffab0080 0x0 0x20>;
903 qos_video_m0: qos@ffab8000 {
904 compatible = "syscon";
905 reg = <0x0 0xffab8000 0x0 0x20>;
908 qos_video_m1_r: qos@ffac0000 {
909 compatible = "syscon";
910 reg = <0x0 0xffac0000 0x0 0x20>;
913 qos_video_m1_w: qos@ffac0080 {
914 compatible = "syscon";
915 reg = <0x0 0xffac0080 0x0 0x20>;
918 qos_vop_big_r: qos@ffac8000 {
919 compatible = "syscon";
920 reg = <0x0 0xffac8000 0x0 0x20>;
923 qos_vop_big_w: qos@ffac8080 {
924 compatible = "syscon";
925 reg = <0x0 0xffac8080 0x0 0x20>;
928 qos_vop_little: qos@ffad0000 {
929 compatible = "syscon";
930 reg = <0x0 0xffad0000 0x0 0x20>;
933 qos_perihp: qos@ffad8080 {
934 compatible = "syscon";
935 reg = <0x0 0xffad8080 0x0 0x20>;
938 qos_gpu: qos@ffae0000 {
939 compatible = "syscon";
940 reg = <0x0 0xffae0000 0x0 0x20>;
943 pmu: power-management@ff310000 {
944 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
945 reg = <0x0 0xff310000 0x0 0x1000>;
948 * Note: RK3399 supports 6 voltage domains including VD_CORE_L,
949 * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
950 * Some of the power domains are grouped together for every
952 * The detail contents as below.
954 power: power-controller {
955 compatible = "rockchip,rk3399-power-controller";
956 #power-domain-cells = <1>;
957 #address-cells = <1>;
960 /* These power domains are grouped by VD_CENTER */
961 pd_iep@RK3399_PD_IEP {
962 reg = <RK3399_PD_IEP>;
963 clocks = <&cru ACLK_IEP>,
967 pd_rga@RK3399_PD_RGA {
968 reg = <RK3399_PD_RGA>;
969 clocks = <&cru ACLK_RGA>,
971 pm_qos = <&qos_rga_r>,
974 pd_vcodec@RK3399_PD_VCODEC {
975 reg = <RK3399_PD_VCODEC>;
976 clocks = <&cru ACLK_VCODEC>,
978 pm_qos = <&qos_video_m0>;
980 pd_vdu@RK3399_PD_VDU {
981 reg = <RK3399_PD_VDU>;
982 clocks = <&cru ACLK_VDU>,
984 pm_qos = <&qos_video_m1_r>,
988 /* These power domains are grouped by VD_GPU */
989 pd_gpu@RK3399_PD_GPU {
990 reg = <RK3399_PD_GPU>;
991 clocks = <&cru ACLK_GPU>;
995 /* These power domains are grouped by VD_LOGIC */
996 pd_edp@RK3399_PD_EDP {
997 reg = <RK3399_PD_EDP>;
998 clocks = <&cru PCLK_EDP_CTRL>;
1000 pd_emmc@RK3399_PD_EMMC {
1001 reg = <RK3399_PD_EMMC>;
1002 clocks = <&cru ACLK_EMMC>;
1003 pm_qos = <&qos_emmc>;
1005 pd_gmac@RK3399_PD_GMAC {
1006 reg = <RK3399_PD_GMAC>;
1007 clocks = <&cru ACLK_GMAC>,
1009 pm_qos = <&qos_gmac>;
1011 pd_perihp@RK3399_PD_PERIHP {
1012 reg = <RK3399_PD_PERIHP>;
1013 #address-cells = <1>;
1015 clocks = <&cru ACLK_PERIHP>;
1016 pm_qos = <&qos_perihp>,
1021 pd_sd@RK3399_PD_SD {
1022 reg = <RK3399_PD_SD>;
1023 clocks = <&cru HCLK_SDMMC>,
1028 pd_sdioaudio@RK3399_PD_SDIOAUDIO {
1029 reg = <RK3399_PD_SDIOAUDIO>;
1030 clocks = <&cru HCLK_SDIO>;
1031 pm_qos = <&qos_sdioaudio>;
1033 pd_usb3@RK3399_PD_USB3 {
1034 reg = <RK3399_PD_USB3>;
1035 clocks = <&cru ACLK_USB3>;
1036 pm_qos = <&qos_usb_otg0>,
1039 pd_vio@RK3399_PD_VIO {
1040 reg = <RK3399_PD_VIO>;
1041 #address-cells = <1>;
1044 pd_hdcp@RK3399_PD_HDCP {
1045 reg = <RK3399_PD_HDCP>;
1046 clocks = <&cru ACLK_HDCP>,
1049 pm_qos = <&qos_hdcp>;
1051 pd_isp0@RK3399_PD_ISP0 {
1052 reg = <RK3399_PD_ISP0>;
1053 clocks = <&cru ACLK_ISP0>,
1055 pm_qos = <&qos_isp0_m0>,
1058 pd_isp1@RK3399_PD_ISP1 {
1059 reg = <RK3399_PD_ISP1>;
1060 clocks = <&cru ACLK_ISP1>,
1062 pm_qos = <&qos_isp1_m0>,
1065 pd_tcpc0@RK3399_PD_TCPC0 {
1066 reg = <RK3399_PD_TCPD0>;
1067 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1068 <&cru SCLK_UPHY0_TCPDPHY_REF>;
1070 pd_tcpc1@RK3399_PD_TCPC1 {
1071 reg = <RK3399_PD_TCPD1>;
1072 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1073 <&cru SCLK_UPHY1_TCPDPHY_REF>;
1075 pd_vo@RK3399_PD_VO {
1076 reg = <RK3399_PD_VO>;
1077 #address-cells = <1>;
1080 pd_vopb@RK3399_PD_VOPB {
1081 reg = <RK3399_PD_VOPB>;
1082 clocks = <&cru ACLK_VOP0>,
1084 pm_qos = <&qos_vop_big_r>,
1087 pd_vopl@RK3399_PD_VOPL {
1088 reg = <RK3399_PD_VOPL>;
1089 clocks = <&cru ACLK_VOP1>,
1091 pm_qos = <&qos_vop_little>;
1098 pmugrf: syscon@ff320000 {
1099 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
1100 reg = <0x0 0xff320000 0x0 0x1000>;
1101 #address-cells = <1>;
1104 pmu_io_domains: io-domains {
1105 compatible = "rockchip,rk3399-pmu-io-voltage-domain";
1106 status = "disabled";
1110 compatible = "syscon-reboot-mode";
1112 mode-bootloader = <BOOT_BL_DOWNLOAD>;
1113 mode-charge = <BOOT_CHARGING>;
1114 mode-fastboot = <BOOT_FASTBOOT>;
1115 mode-loader = <BOOT_BL_DOWNLOAD>;
1116 mode-normal = <BOOT_NORMAL>;
1117 mode-recovery = <BOOT_RECOVERY>;
1118 mode-ums = <BOOT_UMS>;
1121 pmu_pvtm: pmu-pvtm {
1122 compatible = "rockchip,rk3399-pmu-pvtm";
1123 clocks = <&pmucru SCLK_PVTM_PMU>;
1124 clock-names = "pmu";
1125 status = "disabled";
1129 spi3: spi@ff350000 {
1130 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
1131 reg = <0x0 0xff350000 0x0 0x1000>;
1132 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
1133 clock-names = "spiclk", "apb_pclk";
1134 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>;
1135 pinctrl-names = "default";
1136 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
1137 #address-cells = <1>;
1139 status = "disabled";
1142 uart4: serial@ff370000 {
1143 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
1144 reg = <0x0 0xff370000 0x0 0x100>;
1145 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
1146 clock-names = "baudclk", "apb_pclk";
1147 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>;
1150 pinctrl-names = "default";
1151 pinctrl-0 = <&uart4_xfer>;
1152 status = "disabled";
1155 i2c4: i2c@ff3d0000 {
1156 compatible = "rockchip,rk3399-i2c";
1157 reg = <0x0 0xff3d0000 0x0 0x1000>;
1158 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
1159 clock-names = "i2c", "pclk";
1160 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>;
1161 pinctrl-names = "default";
1162 pinctrl-0 = <&i2c4_xfer>;
1163 #address-cells = <1>;
1165 status = "disabled";
1168 i2c8: i2c@ff3e0000 {
1169 compatible = "rockchip,rk3399-i2c";
1170 reg = <0x0 0xff3e0000 0x0 0x1000>;
1171 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
1172 clock-names = "i2c", "pclk";
1173 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
1174 pinctrl-names = "default";
1175 pinctrl-0 = <&i2c8_xfer>;
1176 #address-cells = <1>;
1178 status = "disabled";
1181 pcie_phy: phy@e220 {
1182 compatible = "rockchip,rk3399-pcie-phy";
1184 rockchip,grf = <&grf>;
1185 clocks = <&cru SCLK_PCIEPHY_REF>;
1186 clock-names = "refclk";
1187 resets = <&cru SRST_PCIEPHY>;
1188 reset-names = "phy";
1189 status = "disabled";
1192 pcie0: pcie@f8000000 {
1193 compatible = "rockchip,rk3399-pcie";
1194 #address-cells = <3>;
1197 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
1198 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
1199 clock-names = "aclk", "aclk-perf",
1201 bus-range = <0x0 0x1>;
1202 max-link-speed = <1>;
1203 msi-map = <0x0 &its 0x0 0x1000>;
1204 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
1205 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
1206 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
1207 interrupt-names = "sys", "legacy", "client";
1208 #interrupt-cells = <1>;
1209 interrupt-map-mask = <0 0 0 7>;
1210 interrupt-map = <0 0 0 1 &pcie0_intc 0>,
1211 <0 0 0 2 &pcie0_intc 1>,
1212 <0 0 0 3 &pcie0_intc 2>,
1213 <0 0 0 4 &pcie0_intc 3>;
1215 phy-names = "pcie-phy";
1216 ranges = <0x82000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000
1217 0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>;
1218 reg = <0x0 0xf8000000 0x0 0x2000000>,
1219 <0x0 0xfd000000 0x0 0x1000000>;
1220 reg-names = "axi-base", "apb-base";
1221 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
1222 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>,
1223 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>,
1225 reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
1226 "pm", "pclk", "aclk";
1227 status = "disabled";
1228 pcie0_intc: interrupt-controller {
1229 interrupt-controller;
1230 #address-cells = <0>;
1231 #interrupt-cells = <1>;
1235 pwm0: pwm@ff420000 {
1236 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1237 reg = <0x0 0xff420000 0x0 0x10>;
1239 pinctrl-names = "default";
1240 pinctrl-0 = <&pwm0_pin>;
1241 clocks = <&pmucru PCLK_RKPWM_PMU>;
1242 clock-names = "pwm";
1243 status = "disabled";
1246 pwm1: pwm@ff420010 {
1247 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1248 reg = <0x0 0xff420010 0x0 0x10>;
1250 pinctrl-names = "default";
1251 pinctrl-0 = <&pwm1_pin>;
1252 clocks = <&pmucru PCLK_RKPWM_PMU>;
1253 clock-names = "pwm";
1254 status = "disabled";
1257 pwm2: pwm@ff420020 {
1258 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1259 reg = <0x0 0xff420020 0x0 0x10>;
1261 pinctrl-names = "default";
1262 pinctrl-0 = <&pwm2_pin>;
1263 clocks = <&pmucru PCLK_RKPWM_PMU>;
1264 clock-names = "pwm";
1265 status = "disabled";
1268 pwm3: pwm@ff420030 {
1269 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1270 reg = <0x0 0xff420030 0x0 0x10>;
1272 pinctrl-names = "default";
1273 pinctrl-0 = <&pwm3a_pin>;
1274 clocks = <&pmucru PCLK_RKPWM_PMU>;
1275 clock-names = "pwm";
1276 status = "disabled";
1280 reg = <0x00 0xff630000 0x00 0x4000>;
1281 compatible = "rockchip,rk3399-dfi";
1282 rockchip,pmu = <&pmugrf>;
1283 clocks = <&cru PCLK_DDR_MON>;
1284 clock-names = "pclk_ddr_mon";
1285 status = "disabled";
1289 compatible = "rockchip,rk3399-dmc";
1290 devfreq-events = <&dfi>;
1291 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>;
1292 clocks = <&cru SCLK_DDRCLK>;
1293 clock-names = "dmc_clk";
1294 ddr_timing = <&ddr_timing>;
1295 status = "disabled";
1298 vpu: vpu_service@ff650000 {
1299 compatible = "rockchip,vpu_service";
1300 rockchip,grf = <&grf>;
1301 iommus = <&vpu_mmu>;
1302 iommu_enabled = <1>;
1303 reg = <0x0 0xff650000 0x0 0x800>;
1304 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>,
1305 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>;
1306 interrupt-names = "irq_dec", "irq_enc";
1307 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1308 clock-names = "aclk_vcodec", "hclk_vcodec";
1309 resets = <&cru SRST_H_VCODEC>, <&cru SRST_A_VCODEC>;
1310 reset-names = "video_h", "video_a";
1311 power-domains = <&power RK3399_PD_VCODEC>;
1312 name = "vpu_service";
1314 /* 0 means ion, 1 means drm */
1316 status = "disabled";
1319 vpu_mmu: iommu@ff650800 {
1320 compatible = "rockchip,iommu";
1321 reg = <0x0 0xff650800 0x0 0x40>;
1322 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
1323 interrupt-names = "vpu_mmu";
1324 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1325 clock-names = "aclk", "hclk";
1326 power-domains = <&power RK3399_PD_VCODEC>;
1330 rkvdec: rkvdec@ff660000 {
1331 compatible = "rockchip,rkvdec";
1332 rockchip,grf = <&grf>;
1333 iommus = <&vdec_mmu>;
1334 iommu_enabled = <1>;
1335 reg = <0x0 0xff660000 0x0 0x400>;
1336 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
1337 interrupt-names = "irq_dec";
1338 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>,
1339 <&cru SCLK_VDU_CA>, <&cru SCLK_VDU_CORE>;
1340 clock-names = "aclk_vcodec", "hclk_vcodec",
1341 "clk_cabac", "clk_core";
1342 resets = <&cru SRST_H_VDU>, <&cru SRST_A_VDU>;
1343 reset-names = "video_h", "video_a";
1344 power-domains = <&power RK3399_PD_VDU>;
1347 /* 0 means ion, 1 means drm */
1349 status = "disabled";
1352 vdec_mmu: iommu@ff660480 {
1353 compatible = "rockchip,iommu";
1354 reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>;
1355 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
1356 interrupt-names = "vdec_mmu";
1357 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>;
1358 clock-names = "aclk", "hclk";
1359 power-domains = <&power RK3399_PD_VDU>;
1364 compatible = "rockchip,rk3399-rga";
1365 reg = <0x0 0xff680000 0x0 0x10000>;
1366 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
1367 interrupt-names = "rga";
1368 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
1369 clock-names = "aclk", "hclk", "sclk";
1370 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
1371 reset-names = "core", "axi", "ahb";
1372 power-domains = <&power RK3399_PD_RGA>;
1373 status = "disabled";
1376 efuse0: efuse@ff690000 {
1377 compatible = "rockchip,rk3399-efuse";
1378 reg = <0x0 0xff690000 0x0 0x80>;
1379 #address-cells = <1>;
1381 clocks = <&cru PCLK_EFUSE1024NS>;
1382 clock-names = "pclk_efuse";
1385 cpul_leakage: cpul-leakage {
1388 cpub_leakage: cpub-leakage {
1391 gpu_leakage: gpu-leakage {
1394 center_leakage: center-leakage {
1397 logic_leakage: logic-leakage {
1400 wafer_info: wafer-info {
1405 pmucru: pmu-clock-controller@ff750000 {
1406 compatible = "rockchip,rk3399-pmucru";
1407 reg = <0x0 0xff750000 0x0 0x1000>;
1410 assigned-clocks = <&pmucru PLL_PPLL>;
1411 assigned-clock-rates = <676000000>;
1414 cru: clock-controller@ff760000 {
1415 compatible = "rockchip,rk3399-cru";
1416 reg = <0x0 0xff760000 0x0 0x1000>;
1420 <&cru ACLK_VOP0>, <&cru HCLK_VOP0>,
1421 <&cru ACLK_VOP1>, <&cru HCLK_VOP1>,
1422 <&cru ARMCLKL>, <&cru ARMCLKB>,
1423 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1424 <&cru ACLK_GPU>, <&cru PLL_NPLL>,
1425 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1427 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1428 <&cru PCLK_PERILP0>,
1429 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
1430 assigned-clock-rates =
1431 <400000000>, <200000000>,
1432 <400000000>, <200000000>,
1433 <816000000>, <816000000>,
1434 <594000000>, <800000000>,
1435 <200000000>, <1000000000>,
1436 <150000000>, <75000000>,
1438 <100000000>, <100000000>,
1440 <100000000>, <50000000>;
1443 grf: syscon@ff770000 {
1444 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
1445 reg = <0x0 0xff770000 0x0 0x10000>;
1446 #address-cells = <1>;
1449 io_domains: io-domains {
1450 compatible = "rockchip,rk3399-io-voltage-domain";
1451 status = "disabled";
1454 emmc_phy: phy@f780 {
1455 compatible = "rockchip,rk3399-emmc-phy";
1456 reg = <0xf780 0x24>;
1458 clock-names = "emmcclk";
1460 status = "disabled";
1463 u2phy0: usb2-phy@e450 {
1464 compatible = "rockchip,rk3399-usb2phy";
1465 reg = <0xe450 0x10>;
1466 clocks = <&cru SCLK_USB2PHY0_REF>;
1467 clock-names = "phyclk";
1469 clock-output-names = "clk_usbphy0_480m";
1470 status = "disabled";
1472 u2phy0_otg: otg-port {
1474 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
1475 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
1476 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
1477 interrupt-names = "otg-bvalid", "otg-id",
1479 status = "disabled";
1482 u2phy0_host: host-port {
1484 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
1485 interrupt-names = "linestate";
1486 status = "disabled";
1490 u2phy1: usb2-phy@e460 {
1491 compatible = "rockchip,rk3399-usb2phy";
1492 reg = <0xe460 0x10>;
1493 clocks = <&cru SCLK_USB2PHY1_REF>;
1494 clock-names = "phyclk";
1496 clock-output-names = "clk_usbphy1_480m";
1497 status = "disabled";
1499 u2phy1_otg: otg-port {
1501 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
1502 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
1503 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
1504 interrupt-names = "otg-bvalid", "otg-id",
1506 status = "disabled";
1509 u2phy1_host: host-port {
1511 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
1512 interrupt-names = "linestate";
1513 status = "disabled";
1518 compatible = "rockchip,rk3399-pvtm";
1519 clocks = <&cru SCLK_PVTM_CORE_L>,
1520 <&cru SCLK_PVTM_CORE_B>,
1521 <&cru SCLK_PVTM_GPU>,
1522 <&cru SCLK_PVTM_DDR>;
1523 clock-names = "core_l", "core_b", "gpu", "ddr";
1524 status = "disabled";
1528 tcphy0: phy@ff7c0000 {
1529 compatible = "rockchip,rk3399-typec-phy";
1530 reg = <0x0 0xff7c0000 0x0 0x40000>;
1531 rockchip,grf = <&grf>;
1533 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1534 <&cru SCLK_UPHY0_TCPDPHY_REF>;
1535 clock-names = "tcpdcore", "tcpdphy-ref";
1536 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
1537 assigned-clock-rates = <50000000>;
1538 power-domains = <&power RK3399_PD_TCPD0>;
1539 resets = <&cru SRST_UPHY0>,
1540 <&cru SRST_UPHY0_PIPE_L00>,
1541 <&cru SRST_P_UPHY0_TCPHY>;
1542 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1543 rockchip,typec-conn-dir = <0xe580 0 16>;
1544 rockchip,usb3tousb2-en = <0xe580 3 19>;
1545 rockchip,usb3-host-disable = <0x2434 0 16>;
1546 rockchip,usb3-host-port = <0x2434 12 28>;
1547 rockchip,external-psm = <0xe588 14 30>;
1548 rockchip,pipe-status = <0xe5c0 0 0>;
1549 rockchip,uphy-dp-sel = <0x6268 19 19>;
1550 status = "disabled";
1552 tcphy0_dp: dp-port {
1556 tcphy0_usb3: usb3-port {
1561 tcphy1: phy@ff800000 {
1562 compatible = "rockchip,rk3399-typec-phy";
1563 reg = <0x0 0xff800000 0x0 0x40000>;
1564 rockchip,grf = <&grf>;
1566 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1567 <&cru SCLK_UPHY1_TCPDPHY_REF>;
1568 clock-names = "tcpdcore", "tcpdphy-ref";
1569 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
1570 assigned-clock-rates = <50000000>;
1571 power-domains = <&power RK3399_PD_TCPD1>;
1572 resets = <&cru SRST_UPHY1>,
1573 <&cru SRST_UPHY1_PIPE_L00>,
1574 <&cru SRST_P_UPHY1_TCPHY>;
1575 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1576 rockchip,typec-conn-dir = <0xe58c 0 16>;
1577 rockchip,usb3tousb2-en = <0xe58c 3 19>;
1578 rockchip,usb3-host-disable = <0x2444 0 16>;
1579 rockchip,usb3-host-port = <0x2444 12 28>;
1580 rockchip,external-psm = <0xe594 14 30>;
1581 rockchip,pipe-status = <0xe5c0 16 16>;
1582 rockchip,uphy-dp-sel = <0x6268 3 19>;
1583 status = "disabled";
1585 tcphy1_dp: dp-port {
1589 tcphy1_usb3: usb3-port {
1595 compatible = "snps,dw-wdt";
1596 reg = <0x0 0xff848000 0x0 0x100>;
1597 clocks = <&cru PCLK_WDT>;
1598 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
1601 rktimer: rktimer@ff850000 {
1602 compatible = "rockchip,rk3399-timer";
1603 reg = <0x0 0xff850000 0x0 0x1000>;
1604 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
1605 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1606 clock-names = "pclk", "timer";
1609 spdif: spdif@ff870000 {
1610 compatible = "rockchip,rk3399-spdif";
1611 reg = <0x0 0xff870000 0x0 0x1000>;
1612 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
1613 dmas = <&dmac_bus 7>;
1615 clock-names = "mclk", "hclk";
1616 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1617 pinctrl-names = "default";
1618 pinctrl-0 = <&spdif_bus>;
1619 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1620 status = "disabled";
1623 i2s0: i2s@ff880000 {
1624 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1625 reg = <0x0 0xff880000 0x0 0x1000>;
1626 rockchip,grf = <&grf>;
1627 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>;
1628 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1629 dma-names = "tx", "rx";
1630 clock-names = "i2s_clk", "i2s_hclk";
1631 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1632 pinctrl-names = "default";
1633 pinctrl-0 = <&i2s0_8ch_bus>;
1634 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1635 status = "disabled";
1638 i2s1: i2s@ff890000 {
1639 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1640 reg = <0x0 0xff890000 0x0 0x1000>;
1641 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>;
1642 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1643 dma-names = "tx", "rx";
1644 clock-names = "i2s_clk", "i2s_hclk";
1645 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1646 pinctrl-names = "default";
1647 pinctrl-0 = <&i2s1_2ch_bus>;
1648 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1649 status = "disabled";
1652 i2s2: i2s@ff8a0000 {
1653 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1654 reg = <0x0 0xff8a0000 0x0 0x1000>;
1655 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>;
1656 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1657 dma-names = "tx", "rx";
1658 clock-names = "i2s_clk", "i2s_hclk";
1659 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1660 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1661 status = "disabled";
1665 compatible = "arm,malit860",
1670 reg = <0x0 0xff9a0000 0x0 0x10000>;
1672 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>,
1673 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
1674 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>;
1675 interrupt-names = "GPU", "JOB", "MMU";
1677 clocks = <&cru ACLK_GPU>;
1678 clock-names = "clk_mali";
1679 #cooling-cells = <2>; /* min followed by max */
1680 power-domains = <&power RK3399_PD_GPU>;
1681 power-off-delay-ms = <200>;
1682 status = "disabled";
1684 gpu_power_model: power_model {
1685 compatible = "arm,mali-simple-power-model";
1688 static-power = <300>;
1689 dynamic-power = <396>;
1690 ts = <32000 4700 (-80) 2>;
1691 thermal-zone = "gpu-thermal";
1695 vopl: vop@ff8f0000 {
1696 compatible = "rockchip,rk3399-vop-lit";
1697 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1698 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1699 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1700 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1701 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1702 reset-names = "axi", "ahb", "dclk";
1703 power-domains = <&power RK3399_PD_VOPL>;
1704 iommus = <&vopl_mmu>;
1705 status = "disabled";
1708 #address-cells = <1>;
1711 vopl_out_mipi: endpoint@0 {
1713 remote-endpoint = <&mipi_in_vopl>;
1716 vopl_out_edp: endpoint@1 {
1718 remote-endpoint = <&edp_in_vopl>;
1721 vopl_out_hdmi: endpoint@2 {
1723 remote-endpoint = <&hdmi_in_vopl>;
1726 vopl_out_dp: endpoint@3 {
1728 remote-endpoint = <&dp_in_vopl>;
1733 vop1_pwm: voppwm@ff8f01a0 {
1734 compatible = "rockchip,vop-pwm";
1735 reg = <0x0 0xff8f01a0 0x0 0x10>;
1737 pinctrl-names = "default";
1738 pinctrl-0 = <&vop1_pwm_pin>;
1739 clocks = <&cru SCLK_VOP1_PWM>;
1740 clock-names = "pwm";
1741 status = "disabled";
1744 vopl_mmu: iommu@ff8f3f00 {
1745 compatible = "rockchip,iommu";
1746 reg = <0x0 0xff8f3f00 0x0 0x100>;
1747 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1748 interrupt-names = "vopl_mmu";
1749 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1750 clock-names = "aclk", "hclk";
1751 power-domains = <&power RK3399_PD_VOPL>;
1753 status = "disabled";
1756 vopb: vop@ff900000 {
1757 compatible = "rockchip,rk3399-vop-big";
1758 reg = <0x0 0xff900000 0x0 0x3efc>;
1759 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1760 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1761 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1762 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1763 reset-names = "axi", "ahb", "dclk";
1764 power-domains = <&power RK3399_PD_VOPB>;
1765 iommus = <&vopb_mmu>;
1766 status = "disabled";
1769 #address-cells = <1>;
1772 vopb_out_edp: endpoint@0 {
1774 remote-endpoint = <&edp_in_vopb>;
1777 vopb_out_mipi: endpoint@1 {
1779 remote-endpoint = <&mipi_in_vopb>;
1782 vopb_out_hdmi: endpoint@2 {
1784 remote-endpoint = <&hdmi_in_vopb>;
1787 vopb_out_dp: endpoint@3 {
1789 remote-endpoint = <&dp_in_vopb>;
1794 vop0_pwm: voppwm@ff9001a0 {
1795 compatible = "rockchip,vop-pwm";
1796 reg = <0x0 0xff9001a0 0x0 0x10>;
1798 pinctrl-names = "default";
1799 pinctrl-0 = <&vop0_pwm_pin>;
1800 clocks = <&cru SCLK_VOP0_PWM>;
1801 clock-names = "pwm";
1802 status = "disabled";
1805 vopb_mmu: iommu@ff903f00 {
1806 compatible = "rockchip,iommu";
1807 reg = <0x0 0xff903f00 0x0 0x100>;
1808 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1809 interrupt-names = "vopb_mmu";
1810 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1811 clock-names = "aclk", "hclk";
1812 power-domains = <&power RK3399_PD_VOPB>;
1814 status = "disabled";
1817 isp0_mmu: iommu@ff914000 {
1818 compatible = "rockchip,iommu";
1819 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
1820 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
1821 interrupt-names = "isp0_mmu";
1823 clocks = <&cru ACLK_ISP0_NOC>, <&cru HCLK_ISP0_NOC>;
1824 clock-names = "aclk", "hclk";
1825 power-domains = <&power RK3399_PD_ISP0>;
1826 rk_iommu,disable_reset_quirk;
1827 status = "disabled";
1830 isp1_mmu: iommu@ff924000 {
1831 compatible = "rockchip,iommu";
1832 reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>;
1833 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
1834 interrupt-names = "isp1_mmu";
1836 clocks = <&cru ACLK_ISP1_NOC>, <&cru HCLK_ISP1_NOC>;
1837 clock-names = "aclk", "hclk";
1838 power-domains = <&power RK3399_PD_ISP1>;
1839 rk_iommu,disable_reset_quirk;
1840 status = "disabled";
1843 hdmi: hdmi@ff940000 {
1844 compatible = "rockchip,rk3399-dw-hdmi";
1845 reg = <0x0 0xff940000 0x0 0x20000>;
1847 rockchip,grf = <&grf>;
1848 pinctrl-names = "default";
1849 pinctrl-0 = <&hdmi_i2c_xfer>;
1850 power-domains = <&power RK3399_PD_HDCP>;
1851 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
1852 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_SFR>, <&cru PLL_VPLL>, <&cru PCLK_VIO_GRF>;
1853 clock-names = "iahb", "isfr", "vpll", "grf";
1854 status = "disabled";
1858 #address-cells = <1>;
1860 hdmi_in_vopb: endpoint@0 {
1862 remote-endpoint = <&vopb_out_hdmi>;
1864 hdmi_in_vopl: endpoint@1 {
1866 remote-endpoint = <&vopl_out_hdmi>;
1872 mipi_dsi: mipi@ff960000 {
1873 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1874 reg = <0x0 0xff960000 0x0 0x8000>;
1875 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
1876 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
1877 <&cru SCLK_DPHY_TX0_CFG>;
1878 clock-names = "ref", "pclk", "phy_cfg";
1879 power-domains = <&power RK3399_PD_VIO>;
1880 rockchip,grf = <&grf>;
1881 #address-cells = <1>;
1883 status = "disabled";
1886 #address-cells = <1>;
1891 #address-cells = <1>;
1894 mipi_in_vopb: endpoint@0 {
1896 remote-endpoint = <&vopb_out_mipi>;
1898 mipi_in_vopl: endpoint@1 {
1900 remote-endpoint = <&vopl_out_mipi>;
1907 compatible = "rockchip,rk3399-edp";
1908 reg = <0x0 0xff970000 0x0 0x8000>;
1909 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
1910 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1911 clock-names = "dp", "pclk";
1912 power-domains = <&power RK3399_PD_EDP>;
1913 resets = <&cru SRST_P_EDP_CTRL>;
1915 rockchip,grf = <&grf>;
1916 status = "disabled";
1917 pinctrl-names = "default";
1918 pinctrl-0 = <&edp_hpd>;
1921 #address-cells = <1>;
1926 #address-cells = <1>;
1929 edp_in_vopb: endpoint@0 {
1931 remote-endpoint = <&vopb_out_edp>;
1934 edp_in_vopl: endpoint@1 {
1936 remote-endpoint = <&vopl_out_edp>;
1942 display_subsystem: display-subsystem {
1943 compatible = "rockchip,display-subsystem";
1944 ports = <&vopl_out>, <&vopb_out>;
1945 status = "disabled";
1949 compatible = "rockchip,rk3399-pinctrl";
1950 rockchip,grf = <&grf>;
1951 rockchip,pmu = <&pmugrf>;
1952 #address-cells = <0x2>;
1953 #size-cells = <0x2>;
1956 gpio0: gpio0@ff720000 {
1957 compatible = "rockchip,gpio-bank";
1958 reg = <0x0 0xff720000 0x0 0x100>;
1959 clocks = <&pmucru PCLK_GPIO0_PMU>;
1960 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
1963 #gpio-cells = <0x2>;
1965 interrupt-controller;
1966 #interrupt-cells = <0x2>;
1969 gpio1: gpio1@ff730000 {
1970 compatible = "rockchip,gpio-bank";
1971 reg = <0x0 0xff730000 0x0 0x100>;
1972 clocks = <&pmucru PCLK_GPIO1_PMU>;
1973 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
1976 #gpio-cells = <0x2>;
1978 interrupt-controller;
1979 #interrupt-cells = <0x2>;
1982 gpio2: gpio2@ff780000 {
1983 compatible = "rockchip,gpio-bank";
1984 reg = <0x0 0xff780000 0x0 0x100>;
1985 clocks = <&cru PCLK_GPIO2>;
1986 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>;
1989 #gpio-cells = <0x2>;
1991 interrupt-controller;
1992 #interrupt-cells = <0x2>;
1995 gpio3: gpio3@ff788000 {
1996 compatible = "rockchip,gpio-bank";
1997 reg = <0x0 0xff788000 0x0 0x100>;
1998 clocks = <&cru PCLK_GPIO3>;
1999 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
2002 #gpio-cells = <0x2>;
2004 interrupt-controller;
2005 #interrupt-cells = <0x2>;
2008 gpio4: gpio4@ff790000 {
2009 compatible = "rockchip,gpio-bank";
2010 reg = <0x0 0xff790000 0x0 0x100>;
2011 clocks = <&cru PCLK_GPIO4>;
2012 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
2015 #gpio-cells = <0x2>;
2017 interrupt-controller;
2018 #interrupt-cells = <0x2>;
2021 pcfg_pull_up: pcfg-pull-up {
2025 pcfg_pull_down: pcfg-pull-down {
2029 pcfg_pull_none: pcfg-pull-none {
2033 pcfg_pull_up_20ma: pcfg-pull-up-20ma {
2035 drive-strength = <20>;
2038 pcfg_pull_none_20ma: pcfg-pull-none-20ma {
2040 drive-strength = <20>;
2043 pcfg_pull_none_18ma: pcfg-pull-none-18ma {
2045 drive-strength = <18>;
2048 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
2050 drive-strength = <12>;
2053 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
2055 drive-strength = <8>;
2058 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
2060 drive-strength = <4>;
2063 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
2065 drive-strength = <2>;
2068 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
2070 drive-strength = <12>;
2073 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
2075 drive-strength = <13>;
2078 pcfg_output_high: pcfg-output-high {
2082 pcfg_output_low: pcfg-output-low {
2086 pcfg_input: pcfg-input {
2091 emmc_pwr: emmc-pwr {
2093 <0 5 RK_FUNC_1 &pcfg_pull_up>;
2098 rgmii_pins: rgmii-pins {
2101 <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
2103 <3 14 RK_FUNC_1 &pcfg_pull_none>,
2105 <3 13 RK_FUNC_1 &pcfg_pull_none>,
2107 <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
2109 <3 11 RK_FUNC_1 &pcfg_pull_none>,
2111 <3 9 RK_FUNC_1 &pcfg_pull_none>,
2113 <3 8 RK_FUNC_1 &pcfg_pull_none>,
2115 <3 7 RK_FUNC_1 &pcfg_pull_none>,
2117 <3 6 RK_FUNC_1 &pcfg_pull_none>,
2119 <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
2121 <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
2123 <3 3 RK_FUNC_1 &pcfg_pull_none>,
2125 <3 2 RK_FUNC_1 &pcfg_pull_none>,
2127 <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
2129 <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
2132 rmii_pins: rmii-pins {
2135 <3 13 RK_FUNC_1 &pcfg_pull_none>,
2137 <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
2139 <3 11 RK_FUNC_1 &pcfg_pull_none>,
2141 <3 10 RK_FUNC_1 &pcfg_pull_none>,
2143 <3 9 RK_FUNC_1 &pcfg_pull_none>,
2145 <3 8 RK_FUNC_1 &pcfg_pull_none>,
2147 <3 7 RK_FUNC_1 &pcfg_pull_none>,
2149 <3 6 RK_FUNC_1 &pcfg_pull_none>,
2151 <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
2153 <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
2158 i2c0_xfer: i2c0-xfer {
2160 <1 15 RK_FUNC_2 &pcfg_pull_none>,
2161 <1 16 RK_FUNC_2 &pcfg_pull_none>;
2166 i2c1_xfer: i2c1-xfer {
2168 <4 2 RK_FUNC_1 &pcfg_pull_none>,
2169 <4 1 RK_FUNC_1 &pcfg_pull_none>;
2174 i2c2_xfer: i2c2-xfer {
2176 <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
2177 <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
2182 i2c3_xfer: i2c3-xfer {
2184 <4 17 RK_FUNC_1 &pcfg_pull_none>,
2185 <4 16 RK_FUNC_1 &pcfg_pull_none>;
2188 i2c3_gpio: i2c3_gpio {
2190 <4 17 RK_FUNC_GPIO &pcfg_pull_none>,
2191 <4 16 RK_FUNC_GPIO &pcfg_pull_none>;
2197 i2c4_xfer: i2c4-xfer {
2199 <1 12 RK_FUNC_1 &pcfg_pull_none>,
2200 <1 11 RK_FUNC_1 &pcfg_pull_none>;
2205 i2c5_xfer: i2c5-xfer {
2207 <3 11 RK_FUNC_2 &pcfg_pull_none>,
2208 <3 10 RK_FUNC_2 &pcfg_pull_none>;
2213 i2c6_xfer: i2c6-xfer {
2215 <2 10 RK_FUNC_2 &pcfg_pull_none>,
2216 <2 9 RK_FUNC_2 &pcfg_pull_none>;
2221 i2c7_xfer: i2c7-xfer {
2223 <2 8 RK_FUNC_2 &pcfg_pull_none>,
2224 <2 7 RK_FUNC_2 &pcfg_pull_none>;
2229 i2c8_xfer: i2c8-xfer {
2231 <1 21 RK_FUNC_1 &pcfg_pull_none>,
2232 <1 20 RK_FUNC_1 &pcfg_pull_none>;
2237 i2s0_8ch_bus: i2s0-8ch-bus {
2239 <3 24 RK_FUNC_1 &pcfg_pull_none>,
2240 <3 25 RK_FUNC_1 &pcfg_pull_none>,
2241 <3 26 RK_FUNC_1 &pcfg_pull_none>,
2242 <3 27 RK_FUNC_1 &pcfg_pull_none>,
2243 <3 28 RK_FUNC_1 &pcfg_pull_none>,
2244 <3 29 RK_FUNC_1 &pcfg_pull_none>,
2245 <3 30 RK_FUNC_1 &pcfg_pull_none>,
2246 <3 31 RK_FUNC_1 &pcfg_pull_none>,
2247 <4 0 RK_FUNC_1 &pcfg_pull_none>;
2252 i2s1_2ch_bus: i2s1-2ch-bus {
2254 <4 3 RK_FUNC_1 &pcfg_pull_none>,
2255 <4 4 RK_FUNC_1 &pcfg_pull_none>,
2256 <4 5 RK_FUNC_1 &pcfg_pull_none>,
2257 <4 6 RK_FUNC_1 &pcfg_pull_none>,
2258 <4 7 RK_FUNC_1 &pcfg_pull_none>;
2263 sdio0_bus1: sdio0-bus1 {
2265 <2 20 RK_FUNC_1 &pcfg_pull_up>;
2268 sdio0_bus4: sdio0-bus4 {
2270 <2 20 RK_FUNC_1 &pcfg_pull_up>,
2271 <2 21 RK_FUNC_1 &pcfg_pull_up>,
2272 <2 22 RK_FUNC_1 &pcfg_pull_up>,
2273 <2 23 RK_FUNC_1 &pcfg_pull_up>;
2276 sdio0_cmd: sdio0-cmd {
2278 <2 24 RK_FUNC_1 &pcfg_pull_up>;
2281 sdio0_clk: sdio0-clk {
2283 <2 25 RK_FUNC_1 &pcfg_pull_none>;
2286 sdio0_cd: sdio0-cd {
2288 <2 26 RK_FUNC_1 &pcfg_pull_up>;
2291 sdio0_pwr: sdio0-pwr {
2293 <2 27 RK_FUNC_1 &pcfg_pull_up>;
2296 sdio0_bkpwr: sdio0-bkpwr {
2298 <2 28 RK_FUNC_1 &pcfg_pull_up>;
2301 sdio0_wp: sdio0-wp {
2303 <0 3 RK_FUNC_1 &pcfg_pull_up>;
2306 sdio0_int: sdio0-int {
2308 <0 4 RK_FUNC_1 &pcfg_pull_up>;
2313 sdmmc_bus1: sdmmc-bus1 {
2315 <4 8 RK_FUNC_1 &pcfg_pull_up>;
2318 sdmmc_bus4: sdmmc-bus4 {
2320 <4 8 RK_FUNC_1 &pcfg_pull_up>,
2321 <4 9 RK_FUNC_1 &pcfg_pull_up>,
2322 <4 10 RK_FUNC_1 &pcfg_pull_up>,
2323 <4 11 RK_FUNC_1 &pcfg_pull_up>;
2326 sdmmc_clk: sdmmc-clk {
2328 <4 12 RK_FUNC_1 &pcfg_pull_none>;
2331 sdmmc_cmd: sdmmc-cmd {
2333 <4 13 RK_FUNC_1 &pcfg_pull_up>;
2336 sdmmc_cd: sdmcc-cd {
2338 <0 7 RK_FUNC_1 &pcfg_pull_up>;
2341 sdmmc_wp: sdmmc-wp {
2343 <0 8 RK_FUNC_1 &pcfg_pull_up>;
2348 spdif_bus: spdif-bus {
2350 <4 21 RK_FUNC_1 &pcfg_pull_none>;
2353 spdif_bus_1: spdif-bus-1 {
2355 <3 16 RK_FUNC_3 &pcfg_pull_none>;
2360 spi0_clk: spi0-clk {
2362 <3 6 RK_FUNC_2 &pcfg_pull_up>;
2364 spi0_cs0: spi0-cs0 {
2366 <3 7 RK_FUNC_2 &pcfg_pull_up>;
2368 spi0_cs1: spi0-cs1 {
2370 <3 8 RK_FUNC_2 &pcfg_pull_up>;
2374 <3 5 RK_FUNC_2 &pcfg_pull_up>;
2378 <3 4 RK_FUNC_2 &pcfg_pull_up>;
2383 spi1_clk: spi1-clk {
2385 <1 9 RK_FUNC_2 &pcfg_pull_up>;
2387 spi1_cs0: spi1-cs0 {
2389 <1 10 RK_FUNC_2 &pcfg_pull_up>;
2393 <1 7 RK_FUNC_2 &pcfg_pull_up>;
2397 <1 8 RK_FUNC_2 &pcfg_pull_up>;
2402 spi2_clk: spi2-clk {
2404 <2 11 RK_FUNC_1 &pcfg_pull_up>;
2406 spi2_cs0: spi2-cs0 {
2408 <2 12 RK_FUNC_1 &pcfg_pull_up>;
2412 <2 9 RK_FUNC_1 &pcfg_pull_up>;
2416 <2 10 RK_FUNC_1 &pcfg_pull_up>;
2421 spi3_clk: spi3-clk {
2423 <1 17 RK_FUNC_1 &pcfg_pull_up>;
2425 spi3_cs0: spi3-cs0 {
2427 <1 18 RK_FUNC_1 &pcfg_pull_up>;
2431 <1 15 RK_FUNC_1 &pcfg_pull_up>;
2435 <1 16 RK_FUNC_1 &pcfg_pull_up>;
2440 spi4_clk: spi4-clk {
2442 <3 2 RK_FUNC_2 &pcfg_pull_up>;
2444 spi4_cs0: spi4-cs0 {
2446 <3 3 RK_FUNC_2 &pcfg_pull_up>;
2450 <3 0 RK_FUNC_2 &pcfg_pull_up>;
2454 <3 1 RK_FUNC_2 &pcfg_pull_up>;
2459 spi5_clk: spi5-clk {
2461 <2 22 RK_FUNC_2 &pcfg_pull_up>;
2463 spi5_cs0: spi5-cs0 {
2465 <2 23 RK_FUNC_2 &pcfg_pull_up>;
2469 <2 20 RK_FUNC_2 &pcfg_pull_up>;
2473 <2 21 RK_FUNC_2 &pcfg_pull_up>;
2478 otp_gpio: otp-gpio {
2479 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
2483 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
2488 uart0_xfer: uart0-xfer {
2490 <2 16 RK_FUNC_1 &pcfg_pull_up>,
2491 <2 17 RK_FUNC_1 &pcfg_pull_none>;
2494 uart0_cts: uart0-cts {
2496 <2 18 RK_FUNC_1 &pcfg_pull_none>;
2499 uart0_rts: uart0-rts {
2501 <2 19 RK_FUNC_1 &pcfg_pull_none>;
2506 uart1_xfer: uart1-xfer {
2508 <3 12 RK_FUNC_2 &pcfg_pull_up>,
2509 <3 13 RK_FUNC_2 &pcfg_pull_none>;
2514 uart2a_xfer: uart2a-xfer {
2516 <4 8 RK_FUNC_2 &pcfg_pull_up>,
2517 <4 9 RK_FUNC_2 &pcfg_pull_none>;
2522 uart2b_xfer: uart2b-xfer {
2524 <4 16 RK_FUNC_2 &pcfg_pull_up>,
2525 <4 17 RK_FUNC_2 &pcfg_pull_none>;
2530 uart2c_xfer: uart2c-xfer {
2532 <4 19 RK_FUNC_1 &pcfg_pull_up>,
2533 <4 20 RK_FUNC_1 &pcfg_pull_none>;
2538 uart3_xfer: uart3-xfer {
2540 <3 14 RK_FUNC_2 &pcfg_pull_up>,
2541 <3 15 RK_FUNC_2 &pcfg_pull_none>;
2544 uart3_cts: uart3-cts {
2546 <3 18 RK_FUNC_2 &pcfg_pull_none>;
2549 uart3_rts: uart3-rts {
2551 <3 19 RK_FUNC_2 &pcfg_pull_none>;
2556 uart4_xfer: uart4-xfer {
2558 <1 7 RK_FUNC_1 &pcfg_pull_up>,
2559 <1 8 RK_FUNC_1 &pcfg_pull_none>;
2564 uarthdcp_xfer: uarthdcp-xfer {
2566 <4 21 RK_FUNC_2 &pcfg_pull_up>,
2567 <4 22 RK_FUNC_2 &pcfg_pull_none>;
2572 pwm0_pin: pwm0-pin {
2574 <4 18 RK_FUNC_1 &pcfg_pull_none>;
2577 vop0_pwm_pin: vop0-pwm-pin {
2579 <4 18 RK_FUNC_2 &pcfg_pull_none>;
2584 pwm1_pin: pwm1-pin {
2586 <4 22 RK_FUNC_1 &pcfg_pull_none>;
2589 vop1_pwm_pin: vop1-pwm-pin {
2591 <4 18 RK_FUNC_3 &pcfg_pull_none>;
2596 pwm2_pin: pwm2-pin {
2598 <1 19 RK_FUNC_1 &pcfg_pull_none>;
2603 pwm3a_pin: pwm3a-pin {
2605 <0 6 RK_FUNC_1 &pcfg_pull_none>;
2610 pwm3b_pin: pwm3b-pin {
2612 <1 14 RK_FUNC_1 &pcfg_pull_none>;
2619 <4 23 RK_FUNC_2 &pcfg_pull_none>;
2624 hdmi_i2c_xfer: hdmi-i2c-xfer {
2626 <4 17 RK_FUNC_3 &pcfg_pull_none>,
2627 <4 16 RK_FUNC_3 &pcfg_pull_none>;
2630 hdmi_cec: hdmi-cec {
2632 <4 23 RK_FUNC_1 &pcfg_pull_none>;
2637 pcie_clkreqn: pci-clkreqn {
2639 <2 26 RK_FUNC_2 &pcfg_pull_none>;
2642 pcie_clkreqnb: pci-clkreqnb {
2644 <4 24 RK_FUNC_1 &pcfg_pull_none>;
2647 pcie_clkreqn_cpm: pci-clkreqn-cpm {
2649 * Since our pcie doesn't support
2650 * ClockPM(CPM), we want to hack this as
2651 * gpio, so the EP could be able to
2652 * de-assert it along and make ClockPM(CPM)
2656 <2 26 RK_FUNC_GPIO &pcfg_pull_none>;
2659 pcie_clkreqnb_cpm: pci-clkreqnb-cpm {
2661 <4 24 RK_FUNC_GPIO &pcfg_pull_none>;
2666 rockchip_suspend: rockchip-suspend {
2667 compatible = "rockchip,pm-rk3399";
2668 status = "disabled";
2669 rockchip,sleep-debug-en = <0>;
2670 rockchip,virtual-poweroff = <0>;
2671 rockchip,sleep-mode-config = <
2678 | RKPM_SLP_CENTER_PD
2679 | RKPM_SLP_AP_PWROFF
2682 rockchip,wakeup-config = <