2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/clock/rk3399-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/interrupt-controller/irq.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/power/rk3399-power.h>
49 #include <dt-bindings/soc/rockchip_boot-mode.h>
50 #include <dt-bindings/thermal/thermal.h>
53 compatible = "rockchip,rk3399";
55 interrupt-parent = <&gic>;
77 compatible = "arm,psci-1.0";
113 compatible = "arm,cortex-a53", "arm,armv8";
115 enable-method = "psci";
116 #cooling-cells = <2>; /* min followed by max */
117 dynamic-power-coefficient = <100>;
118 clocks = <&cru ARMCLKL>;
119 cpu-idle-states = <&cpu_sleep>;
120 operating-points-v2 = <&cluster0_opp>;
121 sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
126 compatible = "arm,cortex-a53", "arm,armv8";
128 enable-method = "psci";
129 clocks = <&cru ARMCLKL>;
130 cpu-idle-states = <&cpu_sleep>;
131 operating-points-v2 = <&cluster0_opp>;
132 sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
137 compatible = "arm,cortex-a53", "arm,armv8";
139 enable-method = "psci";
140 clocks = <&cru ARMCLKL>;
141 cpu-idle-states = <&cpu_sleep>;
142 operating-points-v2 = <&cluster0_opp>;
143 sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
148 compatible = "arm,cortex-a53", "arm,armv8";
150 enable-method = "psci";
151 clocks = <&cru ARMCLKL>;
152 cpu-idle-states = <&cpu_sleep>;
153 operating-points-v2 = <&cluster0_opp>;
154 sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
159 compatible = "arm,cortex-a72", "arm,armv8";
161 enable-method = "psci";
162 #cooling-cells = <2>; /* min followed by max */
163 dynamic-power-coefficient = <436>;
164 clocks = <&cru ARMCLKB>;
165 cpu-idle-states = <&cpu_sleep>;
166 operating-points-v2 = <&cluster1_opp>;
167 sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>;
172 compatible = "arm,cortex-a72", "arm,armv8";
174 enable-method = "psci";
175 clocks = <&cru ARMCLKB>;
176 cpu-idle-states = <&cpu_sleep>;
177 operating-points-v2 = <&cluster1_opp>;
178 sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>;
182 entry-method = "psci";
183 cpu_sleep: cpu-sleep-0 {
184 compatible = "arm,idle-state";
186 arm,psci-suspend-param = <0x0010000>;
187 entry-latency-us = <350>;
188 exit-latency-us = <600>;
189 min-residency-us = <1150>;
193 /include/ "rk3399-sched-energy.dtsi"
197 cluster0_opp: opp_table0 {
198 compatible = "operating-points-v2";
202 opp-hz = /bits/ 64 <408000000>;
203 opp-microvolt = <800000>;
204 clock-latency-ns = <40000>;
207 opp-hz = /bits/ 64 <600000000>;
208 opp-microvolt = <800000>;
211 opp-hz = /bits/ 64 <816000000>;
212 opp-microvolt = <800000>;
215 opp-hz = /bits/ 64 <1008000000>;
216 opp-microvolt = <875000>;
219 opp-hz = /bits/ 64 <1200000000>;
220 opp-microvolt = <925000>;
223 opp-hz = /bits/ 64 <1416000000>;
224 opp-microvolt = <1025000>;
228 cluster1_opp: opp_table1 {
229 compatible = "operating-points-v2";
233 opp-hz = /bits/ 64 <408000000>;
234 opp-microvolt = <800000>;
235 clock-latency-ns = <40000>;
238 opp-hz = /bits/ 64 <600000000>;
239 opp-microvolt = <800000>;
242 opp-hz = /bits/ 64 <816000000>;
243 opp-microvolt = <800000>;
246 opp-hz = /bits/ 64 <1008000000>;
247 opp-microvolt = <850000>;
250 opp-hz = /bits/ 64 <1200000000>;
251 opp-microvolt = <925000>;
256 compatible = "arm,armv8-timer";
257 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
258 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
259 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
260 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
264 compatible = "arm,cortex-a53-pmu";
265 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &part0>;
269 compatible = "arm,cortex-a72-pmu";
270 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &part1>;
274 compatible = "fixed-clock";
276 clock-frequency = <24000000>;
277 clock-output-names = "xin24m";
281 compatible = "arm,amba-bus";
282 #address-cells = <2>;
286 dmac_bus: dma-controller@ff6d0000 {
287 compatible = "arm,pl330", "arm,primecell";
288 reg = <0x0 0xff6d0000 0x0 0x4000>;
289 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
290 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
292 clocks = <&cru ACLK_DMAC0_PERILP>;
293 clock-names = "apb_pclk";
294 peripherals-req-type-burst;
297 dmac_peri: dma-controller@ff6e0000 {
298 compatible = "arm,pl330", "arm,primecell";
299 reg = <0x0 0xff6e0000 0x0 0x4000>;
300 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
301 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>;
303 clocks = <&cru ACLK_DMAC1_PERILP>;
304 clock-names = "apb_pclk";
305 peripherals-req-type-burst;
310 compatible = "rockchip,rk3399-gmac";
311 reg = <0x0 0xfe300000 0x0 0x10000>;
312 rockchip,grf = <&grf>;
313 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
314 interrupt-names = "macirq";
315 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
316 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
317 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
319 clock-names = "stmmaceth", "mac_clk_rx",
320 "mac_clk_tx", "clk_mac_ref",
321 "clk_mac_refout", "aclk_mac",
323 resets = <&cru SRST_A_GMAC>;
324 reset-names = "stmmaceth";
329 compatible = "rockchip,rk3399-emmc-phy";
330 reg-offset = <0xf780>;
332 rockchip,grf = <&grf>;
333 ctrl-base = <0xfe330000>;
337 sdio0: dwmmc@fe310000 {
338 compatible = "rockchip,rk3399-dw-mshc",
339 "rockchip,rk3288-dw-mshc";
340 reg = <0x0 0xfe310000 0x0 0x4000>;
341 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>;
342 clock-freq-min-max = <400000 150000000>;
343 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
344 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
345 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
346 fifo-depth = <0x100>;
350 sdmmc: dwmmc@fe320000 {
351 compatible = "rockchip,rk3399-dw-mshc",
352 "rockchip,rk3288-dw-mshc";
353 reg = <0x0 0xfe320000 0x0 0x4000>;
354 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
355 clock-freq-min-max = <400000 150000000>;
356 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
357 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
358 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
359 fifo-depth = <0x100>;
363 sdhci: sdhci@fe330000 {
364 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
365 reg = <0x0 0xfe330000 0x0 0x10000>;
366 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
367 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
368 clock-names = "clk_xin", "clk_ahb";
369 assigned-clocks = <&cru SCLK_EMMC>;
370 assigned-clock-parents = <&cru PLL_CPLL>;
371 assigned-clock-rates = <200000000>;
373 phy-names = "phy_arasan";
377 usb_host0_ehci: usb@fe380000 {
378 compatible = "generic-ehci";
379 reg = <0x0 0xfe380000 0x0 0x20000>;
380 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
381 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
382 <&cru SCLK_USBPHY0_480M_SRC>;
383 clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m";
384 phys = <&u2phy0_host>;
389 usb_host0_ohci: usb@fe3a0000 {
390 compatible = "generic-ohci";
391 reg = <0x0 0xfe3a0000 0x0 0x20000>;
392 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
393 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
394 <&cru SCLK_USBPHY0_480M_SRC>;
395 clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m";
396 phys = <&u2phy0_host>;
401 usb_host1_ehci: usb@fe3c0000 {
402 compatible = "generic-ehci";
403 reg = <0x0 0xfe3c0000 0x0 0x20000>;
404 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
405 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
406 <&cru SCLK_USBPHY1_480M_SRC>;
407 clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m";
408 phys = <&u2phy1_host>;
413 usb_host1_ohci: usb@fe3e0000 {
414 compatible = "generic-ohci";
415 reg = <0x0 0xfe3e0000 0x0 0x20000>;
416 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
417 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
418 <&cru SCLK_USBPHY1_480M_SRC>;
419 clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m";
420 phys = <&u2phy1_host>;
425 usbdrd3_0: usb@fe800000 {
426 compatible = "rockchip,dwc3";
427 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
428 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
429 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
430 clock-names = "clk_usb3otg0_ref", "clk_usb3otg0_suspend",
431 "aclk_usb3otg0", "aclk_usb3_rksoc_axi_perf",
432 "aclk_usb3", "aclk_usb3_grf";
433 #address-cells = <2>;
437 usbdrd_dwc3_0: dwc3@fe800000 {
438 compatible = "snps,dwc3";
439 reg = <0x0 0xfe800000 0x0 0x100000>;
440 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
442 phys = <&u2phy0_otg>;
443 phy-names = "usb2-phy";
444 snps,dis_enblslpm_quirk;
445 snps,phyif_utmi_16_bits;
446 snps,dis_u2_freeclk_exists_quirk;
447 snps,dis_del_phy_power_chg_quirk;
448 snps,xhci_slow_suspend_quirk;
453 usbdrd3_1: usb@fe900000 {
454 compatible = "rockchip,dwc3";
455 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
456 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
457 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
458 clock-names = "clk_usb3otg1_ref", "clk_usb3otg1_suspend",
459 "aclk_usb3otg1", "aclk_usb3_rksoc_axi_perf",
460 "aclk_usb3", "aclk_usb3_grf";
461 #address-cells = <2>;
465 usbdrd_dwc3_1: dwc3@fe900000 {
466 compatible = "snps,dwc3";
467 reg = <0x0 0xfe900000 0x0 0x100000>;
468 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
470 phys = <&u2phy1_otg>;
471 phy-names = "usb2-phy";
472 snps,dis_enblslpm_quirk;
473 snps,phyif_utmi_16_bits;
474 snps,dis_u2_freeclk_exists_quirk;
475 snps,dis_del_phy_power_chg_quirk;
476 snps,xhci_slow_suspend_quirk;
481 gic: interrupt-controller@fee00000 {
482 compatible = "arm,gic-v3";
483 #interrupt-cells = <4>;
484 #address-cells = <2>;
487 interrupt-controller;
489 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
490 <0x0 0xfef00000 0 0xc0000>, /* GICR */
491 <0x0 0xfff00000 0 0x10000>, /* GICC */
492 <0x0 0xfff10000 0 0x10000>, /* GICH */
493 <0x0 0xfff20000 0 0x10000>; /* GICV */
494 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
495 its: interrupt-controller@fee20000 {
496 compatible = "arm,gic-v3-its";
498 reg = <0x0 0xfee20000 0x0 0x20000>;
502 part0: interrupt-partition-0 {
503 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
506 part1: interrupt-partition-1 {
507 affinity = <&cpu_b0 &cpu_b1>;
512 saradc: saradc@ff100000 {
513 compatible = "rockchip,rk3399-saradc";
514 reg = <0x0 0xff100000 0x0 0x100>;
515 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>;
516 #io-channel-cells = <1>;
517 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
518 clock-names = "saradc", "apb_pclk";
523 compatible = "rockchip,rk3399-i2c";
524 reg = <0x0 0xff3c0000 0x0 0x1000>;
525 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
526 clock-names = "i2c", "pclk";
527 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
528 pinctrl-names = "default";
529 pinctrl-0 = <&i2c0_xfer>;
530 #address-cells = <1>;
536 compatible = "rockchip,rk3399-i2c";
537 reg = <0x0 0xff110000 0x0 0x1000>;
538 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
539 clock-names = "i2c", "pclk";
540 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>;
541 pinctrl-names = "default";
542 pinctrl-0 = <&i2c1_xfer>;
543 #address-cells = <1>;
549 compatible = "rockchip,rk3399-i2c";
550 reg = <0x0 0xff120000 0x0 0x1000>;
551 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
552 clock-names = "i2c", "pclk";
553 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>;
554 pinctrl-names = "default";
555 pinctrl-0 = <&i2c2_xfer>;
556 #address-cells = <1>;
562 compatible = "rockchip,rk3399-i2c";
563 reg = <0x0 0xff130000 0x0 0x1000>;
564 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
565 clock-names = "i2c", "pclk";
566 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>;
567 pinctrl-names = "default";
568 pinctrl-0 = <&i2c3_xfer>;
569 #address-cells = <1>;
575 compatible = "rockchip,rk3399-i2c";
576 reg = <0x0 0xff140000 0x0 0x1000>;
577 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
578 clock-names = "i2c", "pclk";
579 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>;
580 pinctrl-names = "default";
581 pinctrl-0 = <&i2c5_xfer>;
582 #address-cells = <1>;
588 compatible = "rockchip,rk3399-i2c";
589 reg = <0x0 0xff150000 0x0 0x1000>;
590 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
591 clock-names = "i2c", "pclk";
592 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>;
593 pinctrl-names = "default";
594 pinctrl-0 = <&i2c6_xfer>;
595 #address-cells = <1>;
601 compatible = "rockchip,rk3399-i2c";
602 reg = <0x0 0xff160000 0x0 0x1000>;
603 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
604 clock-names = "i2c", "pclk";
605 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>;
606 pinctrl-names = "default";
607 pinctrl-0 = <&i2c7_xfer>;
608 #address-cells = <1>;
613 uart0: serial@ff180000 {
614 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
615 reg = <0x0 0xff180000 0x0 0x100>;
616 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
617 clock-names = "baudclk", "apb_pclk";
618 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
621 pinctrl-names = "default";
622 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
626 uart1: serial@ff190000 {
627 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
628 reg = <0x0 0xff190000 0x0 0x100>;
629 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
630 clock-names = "baudclk", "apb_pclk";
631 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>;
634 pinctrl-names = "default";
635 pinctrl-0 = <&uart1_xfer>;
639 uart2: serial@ff1a0000 {
640 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
641 reg = <0x0 0xff1a0000 0x0 0x100>;
642 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
643 clock-names = "baudclk", "apb_pclk";
644 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
647 pinctrl-names = "default";
648 pinctrl-0 = <&uart2c_xfer>;
652 uart3: serial@ff1b0000 {
653 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
654 reg = <0x0 0xff1b0000 0x0 0x100>;
655 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
656 clock-names = "baudclk", "apb_pclk";
657 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
660 pinctrl-names = "default";
661 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
666 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
667 reg = <0x0 0xff1c0000 0x0 0x1000>;
668 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
669 clock-names = "spiclk", "apb_pclk";
670 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>;
671 pinctrl-names = "default";
672 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
673 #address-cells = <1>;
679 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
680 reg = <0x0 0xff1d0000 0x0 0x1000>;
681 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
682 clock-names = "spiclk", "apb_pclk";
683 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>;
684 pinctrl-names = "default";
685 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
686 #address-cells = <1>;
692 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
693 reg = <0x0 0xff1e0000 0x0 0x1000>;
694 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
695 clock-names = "spiclk", "apb_pclk";
696 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>;
697 pinctrl-names = "default";
698 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
699 #address-cells = <1>;
705 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
706 reg = <0x0 0xff1f0000 0x0 0x1000>;
707 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
708 clock-names = "spiclk", "apb_pclk";
709 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>;
710 pinctrl-names = "default";
711 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
712 #address-cells = <1>;
718 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
719 reg = <0x0 0xff200000 0x0 0x1000>;
720 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
721 clock-names = "spiclk", "apb_pclk";
722 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
723 pinctrl-names = "default";
724 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
725 #address-cells = <1>;
731 soc_thermal: soc-thermal {
732 polling-delay-passive = <20>; /* milliseconds */
733 polling-delay = <1000>; /* milliseconds */
734 sustainable-power = <1000>; /* milliwatts */
736 thermal-sensors = <&tsadc 0>;
739 threshold: trip-point@0 {
740 temperature = <70000>; /* millicelsius */
741 hysteresis = <2000>; /* millicelsius */
744 target: trip-point@1 {
745 temperature = <85000>; /* millicelsius */
746 hysteresis = <2000>; /* millicelsius */
750 temperature = <95000>; /* millicelsius */
751 hysteresis = <2000>; /* millicelsius */
760 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
761 contribution = <4096>;
766 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
767 contribution = <1024>;
772 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
773 contribution = <4096>;
778 gpu_thermal: gpu-thermal {
779 polling-delay-passive = <100>; /* milliseconds */
780 polling-delay = <1000>; /* milliseconds */
782 thermal-sensors = <&tsadc 1>;
786 tsadc: tsadc@ff260000 {
787 compatible = "rockchip,rk3399-tsadc";
788 reg = <0x0 0xff260000 0x0 0x100>;
789 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
790 rockchip,grf = <&grf>;
791 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
792 clock-names = "tsadc", "apb_pclk";
793 assigned-clocks = <&cru SCLK_TSADC>;
794 assigned-clock-rates = <750000>;
795 resets = <&cru SRST_TSADC>;
796 reset-names = "tsadc-apb";
797 pinctrl-names = "init", "default", "sleep";
798 pinctrl-0 = <&otp_gpio>;
799 pinctrl-1 = <&otp_out>;
800 pinctrl-2 = <&otp_gpio>;
801 #thermal-sensor-cells = <1>;
802 rockchip,hw-tshut-temp = <95000>;
806 qos_hdcp: qos@ffa90000 {
807 compatible = "syscon";
808 reg = <0x0 0xffa90000 0x0 0x20>;
811 qos_iep: qos@ffa98000 {
812 compatible = "syscon";
813 reg = <0x0 0xffa98000 0x0 0x20>;
816 qos_isp0_m0: qos@ffaa0000 {
817 compatible = "syscon";
818 reg = <0x0 0xffaa0000 0x0 0x20>;
821 qos_isp0_m1: qos@ffaa0080 {
822 compatible = "syscon";
823 reg = <0x0 0xffaa0080 0x0 0x20>;
826 qos_isp1_m0: qos@ffaa8000 {
827 compatible = "syscon";
828 reg = <0x0 0xffaa8000 0x0 0x20>;
831 qos_isp1_m1: qos@ffaa8080 {
832 compatible = "syscon";
833 reg = <0x0 0xffaa8080 0x0 0x20>;
836 qos_rga_r: qos@ffab0000 {
837 compatible = "syscon";
838 reg = <0x0 0xffab0000 0x0 0x20>;
841 qos_rga_w: qos@ffab0080 {
842 compatible = "syscon";
843 reg = <0x0 0xffab0080 0x0 0x20>;
846 qos_video_m0: qos@ffab8000 {
847 compatible = "syscon";
848 reg = <0x0 0xffab8000 0x0 0x20>;
851 qos_video_m1_r: qos@ffac0000 {
852 compatible = "syscon";
853 reg = <0x0 0xffac0000 0x0 0x20>;
856 qos_video_m1_w: qos@ffac0080 {
857 compatible = "syscon";
858 reg = <0x0 0xffac0080 0x0 0x20>;
861 qos_vop_big_r: qos@ffac8000 {
862 compatible = "syscon";
863 reg = <0x0 0xffac8000 0x0 0x20>;
866 qos_vop_big_w: qos@ffac8080 {
867 compatible = "syscon";
868 reg = <0x0 0xffac8080 0x0 0x20>;
871 qos_vop_little: qos@ffad0000 {
872 compatible = "syscon";
873 reg = <0x0 0xffad0000 0x0 0x20>;
876 qos_gpu: qos@ffae0000 {
877 compatible = "syscon";
878 reg = <0x0 0xffae0000 0x0 0x20>;
881 pmu: power-management@ff310000 {
882 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
883 reg = <0x0 0xff310000 0x0 0x1000>;
886 * Note: RK3399 supports 6 voltage domains including VD_CORE_L,
887 * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
888 * Some of the power domains are grouped together for every
890 * The detail contents as below.
892 power: power-controller {
893 compatible = "rockchip,rk3399-power-controller";
894 #power-domain-cells = <1>;
895 #address-cells = <1>;
898 /* These power domains are grouped by VD_CENTER */
899 pd_iep@RK3399_PD_IEP {
900 reg = <RK3399_PD_IEP>;
901 clocks = <&cru ACLK_IEP>,
905 pd_rga@RK3399_PD_RGA {
906 reg = <RK3399_PD_RGA>;
907 clocks = <&cru ACLK_RGA>,
909 pm_qos = <&qos_rga_r>,
912 pd_vcodec@RK3399_PD_VCODEC {
913 reg = <RK3399_PD_VCODEC>;
914 clocks = <&cru ACLK_VCODEC>,
916 pm_qos = <&qos_video_m0>;
918 pd_vdu@RK3399_PD_VDU {
919 reg = <RK3399_PD_VDU>;
920 clocks = <&cru ACLK_VDU>,
922 pm_qos = <&qos_video_m1_r>,
926 /* These power domains are grouped by VD_GPU */
927 pd_gpu@RK3399_PD_GPU {
928 reg = <RK3399_PD_GPU>;
929 clocks = <&cru ACLK_GPU>;
933 /* These power domains are grouped by VD_LOGIC */
934 pd_vio@RK3399_PD_VIO {
935 reg = <RK3399_PD_VIO>;
936 #address-cells = <1>;
939 pd_hdcp@RK3399_PD_HDCP {
940 reg = <RK3399_PD_HDCP>;
941 clocks = <&cru ACLK_HDCP>,
944 pm_qos = <&qos_hdcp>;
946 pd_isp0@RK3399_PD_ISP0 {
947 reg = <RK3399_PD_ISP0>;
948 clocks = <&cru ACLK_ISP0>,
950 pm_qos = <&qos_isp0_m0>,
953 pd_isp1@RK3399_PD_ISP1 {
954 reg = <RK3399_PD_ISP1>;
955 clocks = <&cru ACLK_ISP1>,
957 pm_qos = <&qos_isp1_m0>,
961 reg = <RK3399_PD_VO>;
962 #address-cells = <1>;
965 pd_vopb@RK3399_PD_VOPB {
966 reg = <RK3399_PD_VOPB>;
967 clocks = <&cru ACLK_VOP0>,
969 pm_qos = <&qos_vop_big_r>,
972 pd_vopl@RK3399_PD_VOPL {
973 reg = <RK3399_PD_VOPL>;
974 clocks = <&cru ACLK_VOP1>,
976 pm_qos = <&qos_vop_little>;
983 pmugrf: syscon@ff320000 {
984 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
985 reg = <0x0 0xff320000 0x0 0x1000>;
988 compatible = "syscon-reboot-mode";
990 mode-bootloader = <BOOT_LOADER>;
991 mode-charge = <BOOT_CHARGING>;
992 mode-fastboot = <BOOT_FASTBOOT>;
993 mode-loader = <BOOT_LOADER>;
994 mode-normal = <BOOT_NORMAL>;
995 mode-recovery = <BOOT_RECOVERY>;
1000 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
1001 reg = <0x0 0xff350000 0x0 0x1000>;
1002 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
1003 clock-names = "spiclk", "apb_pclk";
1004 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>;
1005 pinctrl-names = "default";
1006 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
1007 #address-cells = <1>;
1009 status = "disabled";
1012 uart4: serial@ff370000 {
1013 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
1014 reg = <0x0 0xff370000 0x0 0x100>;
1015 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
1016 clock-names = "baudclk", "apb_pclk";
1017 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>;
1020 pinctrl-names = "default";
1021 pinctrl-0 = <&uart4_xfer>;
1022 status = "disabled";
1025 i2c4: i2c@ff3d0000 {
1026 compatible = "rockchip,rk3399-i2c";
1027 reg = <0x0 0xff3d0000 0x0 0x1000>;
1028 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
1029 clock-names = "i2c", "pclk";
1030 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>;
1031 pinctrl-names = "default";
1032 pinctrl-0 = <&i2c4_xfer>;
1033 #address-cells = <1>;
1035 status = "disabled";
1038 i2c8: i2c@ff3e0000 {
1039 compatible = "rockchip,rk3399-i2c";
1040 reg = <0x0 0xff3e0000 0x0 0x1000>;
1041 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
1042 clock-names = "i2c", "pclk";
1043 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
1044 pinctrl-names = "default";
1045 pinctrl-0 = <&i2c8_xfer>;
1046 #address-cells = <1>;
1048 status = "disabled";
1051 pcie0: pcie@f8000000 {
1052 compatible = "rockchip,rk3399-pcie";
1053 #address-cells = <3>;
1055 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
1056 <&cru PCLK_PCIE>, <&cru SCLK_PCIEPHY_REF>;
1057 clock-names = "aclk_pcie", "aclk_perf_pcie",
1058 "hclk_pcie", "clk_pciephy_ref";
1059 bus-range = <0x0 0x1>;
1060 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
1061 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
1062 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
1063 interrupt-names = "pcie-sys", "pcie-legacy", "pcie-client";
1064 ranges = < 0x82000000 0 0xfa000000 0x0 0xfa000000 0 0x600000
1065 0x81000000 0 0xfa600000 0x0 0xfa600000 0 0x100000 >;
1066 reg = < 0x0 0xf8000000 0x0 0x2000000 >,
1067 < 0x0 0xfd000000 0x0 0x1000000 >;
1068 reg-name = "axi-base", "apb-base";
1069 resets = <&cru SRST_PCIEPHY>, <&cru SRST_PCIE_CORE>,
1070 <&cru SRST_PCIE_MGMT>, <&cru SRST_PCIE_MGMT_STICKY>,
1071 <&cru SRST_PCIE_PIPE>;
1072 reset-names = "phy-rst", "core-rst", "mgmt-rst",
1073 "mgmt-sticky-rst", "pipe-rst";
1074 rockchip,grf = <&grf>;
1075 pcie-conf = <0xe220>;
1076 pcie-status = <0xe2a4>;
1077 pcie-laneoff = <0xe214>;
1078 msi-parent = <&its>;
1079 #interrupt-cells = <1>;
1080 interrupt-map-mask = <0 0 0 7>;
1081 interrupt-map = <0 0 0 1 &pcie0 1>,
1085 status = "disabled";
1086 pcie_intc: interrupt-controller {
1087 interrupt-controller;
1088 #address-cells = <0>;
1089 #interrupt-cells = <1>;
1093 pwm0: pwm@ff420000 {
1094 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1095 reg = <0x0 0xff420000 0x0 0x10>;
1097 pinctrl-names = "default";
1098 pinctrl-0 = <&pwm0_pin>;
1099 clocks = <&pmucru PCLK_RKPWM_PMU>;
1100 clock-names = "pwm";
1101 status = "disabled";
1104 pwm1: pwm@ff420010 {
1105 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1106 reg = <0x0 0xff420010 0x0 0x10>;
1108 pinctrl-names = "default";
1109 pinctrl-0 = <&pwm1_pin>;
1110 clocks = <&pmucru PCLK_RKPWM_PMU>;
1111 clock-names = "pwm";
1112 status = "disabled";
1115 pwm2: pwm@ff420020 {
1116 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1117 reg = <0x0 0xff420020 0x0 0x10>;
1119 pinctrl-names = "default";
1120 pinctrl-0 = <&pwm2_pin>;
1121 clocks = <&pmucru PCLK_RKPWM_PMU>;
1122 clock-names = "pwm";
1123 status = "disabled";
1126 pwm3: pwm@ff420030 {
1127 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1128 reg = <0x0 0xff420030 0x0 0x10>;
1130 pinctrl-names = "default";
1131 pinctrl-0 = <&pwm3a_pin>;
1132 clocks = <&pmucru PCLK_RKPWM_PMU>;
1133 clock-names = "pwm";
1134 status = "disabled";
1138 compatible = "rockchip,rk3399-rga";
1139 reg = <0x0 0xff680000 0x0 0x10000>;
1140 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
1141 interrupt-names = "rga";
1142 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
1143 clock-names = "aclk", "hclk", "sclk";
1144 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
1145 reset-names = "core", "axi", "ahb";
1146 status = "disabled";
1149 pmucru: pmu-clock-controller@ff750000 {
1150 compatible = "rockchip,rk3399-pmucru";
1151 reg = <0x0 0xff750000 0x0 0x1000>;
1154 assigned-clocks = <&pmucru PLL_PPLL>;
1155 assigned-clock-rates = <676000000>;
1158 cru: clock-controller@ff760000 {
1159 compatible = "rockchip,rk3399-cru";
1160 reg = <0x0 0xff760000 0x0 0x1000>;
1164 <&cru ACLK_VOP0>, <&cru HCLK_VOP0>,
1165 <&cru ACLK_VOP1>, <&cru HCLK_VOP1>,
1166 <&cru ARMCLKL>, <&cru ARMCLKB>,
1167 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1169 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1171 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1172 <&cru PCLK_PERILP0>,
1173 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
1174 assigned-clock-rates =
1175 <400000000>, <200000000>,
1176 <400000000>, <200000000>,
1177 <816000000>, <816000000>,
1178 <594000000>, <800000000>,
1180 <150000000>, <75000000>,
1182 <100000000>, <100000000>,
1184 <100000000>, <50000000>;
1187 grf: syscon@ff770000 {
1188 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
1189 reg = <0x0 0xff770000 0x0 0x10000>;
1190 #address-cells = <1>;
1193 u2phy0: usb2-phy@e450 {
1194 compatible = "rockchip,rk3399-usb2phy";
1195 reg = <0xe450 0x10>;
1196 clocks = <&cru SCLK_USB2PHY0_REF>;
1197 clock-names = "phyclk";
1199 clock-output-names = "clk_usbphy0_480m";
1200 status = "disabled";
1202 u2phy0_otg: otg-port {
1204 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
1205 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
1206 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
1207 interrupt-names = "otg-bvalid", "otg-id",
1209 status = "disabled";
1212 u2phy0_host: host-port {
1214 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
1215 interrupt-names = "linestate";
1216 status = "disabled";
1220 u2phy1: usb2-phy@e460 {
1221 compatible = "rockchip,rk3399-usb2phy";
1222 reg = <0xe460 0x10>;
1223 clocks = <&cru SCLK_USB2PHY1_REF>;
1224 clock-names = "phyclk";
1226 clock-output-names = "clk_usbphy1_480m";
1227 status = "disabled";
1229 u2phy1_otg: otg-port {
1231 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
1232 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
1233 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1234 interrupt-names = "otg-bvalid", "otg-id",
1236 status = "disabled";
1239 u2phy1_host: host-port {
1241 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
1242 interrupt-names = "linestate";
1243 status = "disabled";
1248 tcphy0: phy@ff7c0000 {
1249 compatible = "rockchip,rk3399-typec-phy";
1250 reg = <0x0 0xff7c0000 0x0 0x40000>;
1251 rockchip,grf = <&grf>;
1253 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1254 <&cru SCLK_UPHY0_TCPDPHY_REF>;
1255 clock-names = "tcpdcore", "tcpdphy-ref";
1256 resets = <&cru SRST_UPHY0>,
1257 <&cru SRST_UPHY0_PIPE_L00>,
1258 <&cru SRST_P_UPHY0_TCPHY>;
1259 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1260 rockchip,typec-conn-dir = <0xe580 0 16>;
1261 rockchip,usb3tousb2-en = <0xe580 3 19>;
1262 rockchip,external-psm = <0xe588 14 30>;
1263 rockchip,pipe-status = <0xe5c0 0 0>;
1264 rockchip,uphy-dp-sel = <0x6268 19 19>;
1265 status = "disabled";
1268 tcphy1: phy@ff800000 {
1269 compatible = "rockchip,rk3399-typec-phy";
1270 reg = <0x0 0xff800000 0x0 0x40000>;
1271 rockchip,grf = <&grf>;
1273 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1274 <&cru SCLK_UPHY1_TCPDPHY_REF>;
1275 clock-names = "tcpdcore", "tcpdphy-ref";
1276 resets = <&cru SRST_UPHY1>,
1277 <&cru SRST_UPHY1_PIPE_L00>,
1278 <&cru SRST_P_UPHY1_TCPHY>;
1279 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1280 rockchip,typec-conn-dir = <0xe58c 0 16>;
1281 rockchip,usb3tousb2-en = <0xe58c 3 19>;
1282 rockchip,external-psm = <0xe594 14 30>;
1283 rockchip,pipe-status = <0xe5c0 16 16>;
1284 rockchip,uphy-dp-sel = <0x6268 3 19>;
1285 status = "disabled";
1289 compatible = "snps,dw-wdt";
1290 reg = <0x0 0xff840000 0x0 0x100>;
1291 clocks = <&cru PCLK_WDT>;
1292 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
1295 rktimer: rktimer@ff850000 {
1296 compatible = "rockchip,rk3399-timer";
1297 reg = <0x0 0xff850000 0x0 0x1000>;
1298 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
1299 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1300 clock-names = "pclk", "timer";
1303 spdif: spdif@ff870000 {
1304 compatible = "rockchip,rk3399-spdif";
1305 reg = <0x0 0xff870000 0x0 0x1000>;
1306 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
1307 dmas = <&dmac_bus 7>;
1309 clock-names = "mclk", "hclk";
1310 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1311 pinctrl-names = "default";
1312 pinctrl-0 = <&spdif_bus>;
1313 status = "disabled";
1316 i2s0: i2s@ff880000 {
1317 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1318 reg = <0x0 0xff880000 0x0 0x1000>;
1319 rockchip,grf = <&grf>;
1320 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>;
1321 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1322 dma-names = "tx", "rx";
1323 clock-names = "i2s_clk", "i2s_hclk";
1324 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1325 pinctrl-names = "default";
1326 pinctrl-0 = <&i2s0_8ch_bus>;
1327 status = "disabled";
1330 i2s1: i2s@ff890000 {
1331 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1332 reg = <0x0 0xff890000 0x0 0x1000>;
1333 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>;
1334 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1335 dma-names = "tx", "rx";
1336 clock-names = "i2s_clk", "i2s_hclk";
1337 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1338 pinctrl-names = "default";
1339 pinctrl-0 = <&i2s1_2ch_bus>;
1340 status = "disabled";
1343 i2s2: i2s@ff8a0000 {
1344 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1345 reg = <0x0 0xff8a0000 0x0 0x1000>;
1346 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>;
1347 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1348 dma-names = "tx", "rx";
1349 clock-names = "i2s_clk", "i2s_hclk";
1350 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1351 status = "disabled";
1355 compatible = "arm,malit860",
1360 reg = <0x0 0xff9a0000 0x0 0x10000>;
1362 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>,
1363 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
1364 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>;
1365 interrupt-names = "GPU", "JOB", "MMU";
1367 clocks = <&cru ACLK_GPU>;
1368 clock-names = "clk_mali";
1369 #cooling-cells = <2>; /* min followed by max */
1370 operating-points-v2 = <&gpu_opp_table>;
1371 power-domains = <&power RK3399_PD_GPU>;
1372 power-off-delay-ms = <200>;
1373 status = "disabled";
1375 gpu_power_model: power_model {
1376 compatible = "arm,mali-simple-power-model";
1379 static-power = <300>;
1380 dynamic-power = <396>;
1381 ts = <32000 4700 (-80) 2>;
1382 thermal-zone = "gpu-thermal";
1386 gpu_opp_table: gpu_opp_table {
1387 compatible = "operating-points-v2";
1391 opp-hz = /bits/ 64 <200000000>;
1392 opp-microvolt = <900000>;
1395 opp-hz = /bits/ 64 <300000000>;
1396 opp-microvolt = <900000>;
1399 opp-hz = /bits/ 64 <400000000>;
1400 opp-microvolt = <900000>;
1405 vopl: vop@ff8f0000 {
1406 compatible = "rockchip,rk3399-vop-lit";
1407 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1408 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1409 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1410 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1411 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1412 reset-names = "axi", "ahb", "dclk";
1413 power-domains = <&power RK3399_PD_VOPL>;
1414 iommus = <&vopl_mmu>;
1415 status = "disabled";
1418 #address-cells = <1>;
1421 vopl_out_mipi: endpoint@0 {
1423 remote-endpoint = <&mipi_in_vopl>;
1426 vopl_out_edp: endpoint@1 {
1428 remote-endpoint = <&edp_in_vopl>;
1431 vopl_out_hdmi: endpoint@2 {
1433 remote-endpoint = <&hdmi_in_vopl>;
1438 vopl_mmu: iommu@ff8f3f00 {
1439 compatible = "rockchip,iommu";
1440 reg = <0x0 0xff8f3f00 0x0 0x100>;
1441 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1442 interrupt-names = "vopl_mmu";
1444 status = "disabled";
1447 vopb: vop@ff900000 {
1448 compatible = "rockchip,rk3399-vop-big";
1449 reg = <0x0 0xff900000 0x0 0x3efc>;
1450 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1451 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1452 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1453 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1454 reset-names = "axi", "ahb", "dclk";
1455 power-domains = <&power RK3399_PD_VOPB>;
1456 iommus = <&vopb_mmu>;
1457 status = "disabled";
1460 #address-cells = <1>;
1463 vopb_out_edp: endpoint@0 {
1465 remote-endpoint = <&edp_in_vopb>;
1468 vopb_out_mipi: endpoint@1 {
1470 remote-endpoint = <&mipi_in_vopb>;
1473 vopb_out_hdmi: endpoint@2 {
1475 remote-endpoint = <&hdmi_in_vopb>;
1480 vopb_mmu: iommu@ff903f00 {
1481 compatible = "rockchip,iommu";
1482 reg = <0x0 0xff903f00 0x0 0x100>;
1483 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1484 interrupt-names = "vopb_mmu";
1486 status = "disabled";
1489 hdmi: hdmi@ff940000 {
1490 compatible = "rockchip,rk3399-dw-hdmi";
1491 reg = <0x0 0xff940000 0x0 0x20000>;
1493 rockchip,grf = <&grf>;
1494 power-domains = <&power RK3399_PD_HDCP>;
1495 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
1496 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_SFR>, <&cru SCLK_HDMI_SFR>, <&cru PCLK_EDP_CTRL>;
1497 clock-names = "iahb", "isfr", "vpll", "grf";
1498 status = "disabled";
1502 #address-cells = <1>;
1504 hdmi_in_vopb: endpoint@0 {
1506 remote-endpoint = <&vopb_out_hdmi>;
1508 hdmi_in_vopl: endpoint@1 {
1510 remote-endpoint = <&vopl_out_hdmi>;
1516 mipi_dsi: mipi@ff960000 {
1517 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1518 reg = <0x0 0xff960000 0x0 0x8000>;
1519 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
1520 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
1521 <&cru SCLK_DPHY_TX0_CFG>;
1522 clock-names = "ref", "pclk", "phy_cfg";
1523 power-domains = <&power RK3399_PD_VIO>;
1524 rockchip,grf = <&grf>;
1525 #address-cells = <1>;
1527 status = "disabled";
1530 #address-cells = <1>;
1535 #address-cells = <1>;
1538 mipi_in_vopb: endpoint@0 {
1540 remote-endpoint = <&vopb_out_mipi>;
1542 mipi_in_vopl: endpoint@1 {
1544 remote-endpoint = <&vopl_out_mipi>;
1551 compatible = "rockchip,rk3399-edp";
1552 reg = <0x0 0xff970000 0x0 0x8000>;
1553 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
1554 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1555 clock-names = "dp", "pclk";
1556 resets = <&cru SRST_P_EDP_CTRL>;
1558 rockchip,grf = <&grf>;
1559 status = "disabled";
1560 pinctrl-names = "default";
1561 pinctrl-0 = <&edp_hpd>;
1564 #address-cells = <1>;
1569 #address-cells = <1>;
1572 edp_in_vopb: endpoint@0 {
1574 remote-endpoint = <&vopb_out_edp>;
1577 edp_in_vopl: endpoint@1 {
1579 remote-endpoint = <&vopl_out_edp>;
1585 display_subsystem: display-subsystem {
1586 compatible = "rockchip,display-subsystem";
1587 ports = <&vopl_out>, <&vopb_out>;
1588 status = "disabled";
1592 compatible = "rockchip,rk3399-pinctrl";
1593 rockchip,grf = <&grf>;
1594 rockchip,pmu = <&pmugrf>;
1595 #address-cells = <0x2>;
1596 #size-cells = <0x2>;
1599 gpio0: gpio0@ff720000 {
1600 compatible = "rockchip,gpio-bank";
1601 reg = <0x0 0xff720000 0x0 0x100>;
1602 clocks = <&pmucru PCLK_GPIO0_PMU>;
1603 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
1606 #gpio-cells = <0x2>;
1608 interrupt-controller;
1609 #interrupt-cells = <0x2>;
1612 gpio1: gpio1@ff730000 {
1613 compatible = "rockchip,gpio-bank";
1614 reg = <0x0 0xff730000 0x0 0x100>;
1615 clocks = <&pmucru PCLK_GPIO1_PMU>;
1616 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
1619 #gpio-cells = <0x2>;
1621 interrupt-controller;
1622 #interrupt-cells = <0x2>;
1625 gpio2: gpio2@ff780000 {
1626 compatible = "rockchip,gpio-bank";
1627 reg = <0x0 0xff780000 0x0 0x100>;
1628 clocks = <&cru PCLK_GPIO2>;
1629 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>;
1632 #gpio-cells = <0x2>;
1634 interrupt-controller;
1635 #interrupt-cells = <0x2>;
1638 gpio3: gpio3@ff788000 {
1639 compatible = "rockchip,gpio-bank";
1640 reg = <0x0 0xff788000 0x0 0x100>;
1641 clocks = <&cru PCLK_GPIO3>;
1642 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
1645 #gpio-cells = <0x2>;
1647 interrupt-controller;
1648 #interrupt-cells = <0x2>;
1651 gpio4: gpio4@ff790000 {
1652 compatible = "rockchip,gpio-bank";
1653 reg = <0x0 0xff790000 0x0 0x100>;
1654 clocks = <&cru PCLK_GPIO4>;
1655 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
1658 #gpio-cells = <0x2>;
1660 interrupt-controller;
1661 #interrupt-cells = <0x2>;
1664 pcfg_pull_up: pcfg-pull-up {
1668 pcfg_pull_down: pcfg-pull-down {
1672 pcfg_pull_none: pcfg-pull-none {
1676 pcfg_pull_up_20ma: pcfg-pull-up-20ma {
1678 drive-strength = <20>;
1681 pcfg_pull_none_20ma: pcfg-pull-none-20ma {
1683 drive-strength = <20>;
1686 pcfg_pull_none_18ma: pcfg-pull-none-18ma {
1688 drive-strength = <18>;
1691 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1693 drive-strength = <12>;
1696 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1698 drive-strength = <8>;
1701 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1703 drive-strength = <4>;
1706 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1708 drive-strength = <2>;
1711 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
1713 drive-strength = <12>;
1716 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
1718 drive-strength = <13>;
1722 emmc_pwr: emmc-pwr {
1724 <0 5 RK_FUNC_1 &pcfg_pull_up>;
1729 rgmii_pins: rgmii-pins {
1732 <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
1734 <3 14 RK_FUNC_1 &pcfg_pull_none>,
1736 <3 13 RK_FUNC_1 &pcfg_pull_none>,
1738 <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1740 <3 11 RK_FUNC_1 &pcfg_pull_none>,
1742 <3 9 RK_FUNC_1 &pcfg_pull_none>,
1744 <3 8 RK_FUNC_1 &pcfg_pull_none>,
1746 <3 7 RK_FUNC_1 &pcfg_pull_none>,
1748 <3 6 RK_FUNC_1 &pcfg_pull_none>,
1750 <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1752 <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
1754 <3 3 RK_FUNC_1 &pcfg_pull_none>,
1756 <3 2 RK_FUNC_1 &pcfg_pull_none>,
1758 <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
1760 <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
1763 rmii_pins: rmii-pins {
1766 <3 13 RK_FUNC_1 &pcfg_pull_none>,
1768 <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1770 <3 11 RK_FUNC_1 &pcfg_pull_none>,
1772 <3 10 RK_FUNC_1 &pcfg_pull_none>,
1774 <3 9 RK_FUNC_1 &pcfg_pull_none>,
1776 <3 8 RK_FUNC_1 &pcfg_pull_none>,
1778 <3 7 RK_FUNC_1 &pcfg_pull_none>,
1780 <3 6 RK_FUNC_1 &pcfg_pull_none>,
1782 <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1784 <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
1789 i2c0_xfer: i2c0-xfer {
1791 <1 15 RK_FUNC_2 &pcfg_pull_none>,
1792 <1 16 RK_FUNC_2 &pcfg_pull_none>;
1797 i2c1_xfer: i2c1-xfer {
1799 <4 2 RK_FUNC_1 &pcfg_pull_none>,
1800 <4 1 RK_FUNC_1 &pcfg_pull_none>;
1805 i2c2_xfer: i2c2-xfer {
1807 <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1808 <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
1813 i2c3_xfer: i2c3-xfer {
1815 <4 17 RK_FUNC_1 &pcfg_pull_none>,
1816 <4 16 RK_FUNC_1 &pcfg_pull_none>;
1819 i2c3_gpio: i2c3_gpio {
1821 <4 17 RK_FUNC_GPIO &pcfg_pull_none>,
1822 <4 16 RK_FUNC_GPIO &pcfg_pull_none>;
1828 i2c4_xfer: i2c4-xfer {
1830 <1 12 RK_FUNC_1 &pcfg_pull_none>,
1831 <1 11 RK_FUNC_1 &pcfg_pull_none>;
1836 i2c5_xfer: i2c5-xfer {
1838 <3 11 RK_FUNC_2 &pcfg_pull_none>,
1839 <3 10 RK_FUNC_2 &pcfg_pull_none>;
1844 i2c6_xfer: i2c6-xfer {
1846 <2 10 RK_FUNC_2 &pcfg_pull_none>,
1847 <2 9 RK_FUNC_2 &pcfg_pull_none>;
1852 i2c7_xfer: i2c7-xfer {
1854 <2 8 RK_FUNC_2 &pcfg_pull_none>,
1855 <2 7 RK_FUNC_2 &pcfg_pull_none>;
1860 i2c8_xfer: i2c8-xfer {
1862 <1 21 RK_FUNC_1 &pcfg_pull_none>,
1863 <1 20 RK_FUNC_1 &pcfg_pull_none>;
1868 i2s0_8ch_bus: i2s0-8ch-bus {
1870 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1871 <3 25 RK_FUNC_1 &pcfg_pull_none>,
1872 <3 26 RK_FUNC_1 &pcfg_pull_none>,
1873 <3 27 RK_FUNC_1 &pcfg_pull_none>,
1874 <3 28 RK_FUNC_1 &pcfg_pull_none>,
1875 <3 29 RK_FUNC_1 &pcfg_pull_none>,
1876 <3 30 RK_FUNC_1 &pcfg_pull_none>,
1877 <3 31 RK_FUNC_1 &pcfg_pull_none>,
1878 <4 0 RK_FUNC_1 &pcfg_pull_none>;
1883 i2s1_2ch_bus: i2s1-2ch-bus {
1885 <4 3 RK_FUNC_1 &pcfg_pull_none>,
1886 <4 4 RK_FUNC_1 &pcfg_pull_none>,
1887 <4 5 RK_FUNC_1 &pcfg_pull_none>,
1888 <4 6 RK_FUNC_1 &pcfg_pull_none>,
1889 <4 7 RK_FUNC_1 &pcfg_pull_none>;
1894 sdio0_bus1: sdio0-bus1 {
1896 <2 20 RK_FUNC_1 &pcfg_pull_up>;
1899 sdio0_bus4: sdio0-bus4 {
1901 <2 20 RK_FUNC_1 &pcfg_pull_up>,
1902 <2 21 RK_FUNC_1 &pcfg_pull_up>,
1903 <2 22 RK_FUNC_1 &pcfg_pull_up>,
1904 <2 23 RK_FUNC_1 &pcfg_pull_up>;
1907 sdio0_cmd: sdio0-cmd {
1909 <2 24 RK_FUNC_1 &pcfg_pull_up>;
1912 sdio0_clk: sdio0-clk {
1914 <2 25 RK_FUNC_1 &pcfg_pull_none>;
1917 sdio0_cd: sdio0-cd {
1919 <2 26 RK_FUNC_1 &pcfg_pull_up>;
1922 sdio0_pwr: sdio0-pwr {
1924 <2 27 RK_FUNC_1 &pcfg_pull_up>;
1927 sdio0_bkpwr: sdio0-bkpwr {
1929 <2 28 RK_FUNC_1 &pcfg_pull_up>;
1932 sdio0_wp: sdio0-wp {
1934 <0 3 RK_FUNC_1 &pcfg_pull_up>;
1937 sdio0_int: sdio0-int {
1939 <0 4 RK_FUNC_1 &pcfg_pull_up>;
1944 sdmmc_bus1: sdmmc-bus1 {
1946 <4 8 RK_FUNC_1 &pcfg_pull_up>;
1949 sdmmc_bus4: sdmmc-bus4 {
1951 <4 8 RK_FUNC_1 &pcfg_pull_up>,
1952 <4 9 RK_FUNC_1 &pcfg_pull_up>,
1953 <4 10 RK_FUNC_1 &pcfg_pull_up>,
1954 <4 11 RK_FUNC_1 &pcfg_pull_up>;
1957 sdmmc_clk: sdmmc-clk {
1959 <4 12 RK_FUNC_1 &pcfg_pull_none>;
1962 sdmmc_cmd: sdmmc-cmd {
1964 <4 13 RK_FUNC_1 &pcfg_pull_up>;
1967 sdmmc_cd: sdmcc-cd {
1969 <0 7 RK_FUNC_1 &pcfg_pull_up>;
1972 sdmmc_wp: sdmmc-wp {
1974 <0 8 RK_FUNC_1 &pcfg_pull_up>;
1979 spdif_bus: spdif-bus {
1981 <4 21 RK_FUNC_1 &pcfg_pull_none>;
1984 spdif_bus_1: spdif-bus-1 {
1986 <3 16 RK_FUNC_3 &pcfg_pull_none>;
1991 spi0_clk: spi0-clk {
1993 <3 6 RK_FUNC_2 &pcfg_pull_up>;
1995 spi0_cs0: spi0-cs0 {
1997 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1999 spi0_cs1: spi0-cs1 {
2001 <3 8 RK_FUNC_2 &pcfg_pull_up>;
2005 <3 5 RK_FUNC_2 &pcfg_pull_up>;
2009 <3 4 RK_FUNC_2 &pcfg_pull_up>;
2014 spi1_clk: spi1-clk {
2016 <1 9 RK_FUNC_2 &pcfg_pull_up>;
2018 spi1_cs0: spi1-cs0 {
2020 <1 10 RK_FUNC_2 &pcfg_pull_up>;
2024 <1 7 RK_FUNC_2 &pcfg_pull_up>;
2028 <1 8 RK_FUNC_2 &pcfg_pull_up>;
2033 spi2_clk: spi2-clk {
2035 <2 11 RK_FUNC_1 &pcfg_pull_up>;
2037 spi2_cs0: spi2-cs0 {
2039 <2 12 RK_FUNC_1 &pcfg_pull_up>;
2043 <2 9 RK_FUNC_1 &pcfg_pull_up>;
2047 <2 10 RK_FUNC_1 &pcfg_pull_up>;
2052 spi3_clk: spi3-clk {
2054 <1 17 RK_FUNC_1 &pcfg_pull_up>;
2056 spi3_cs0: spi3-cs0 {
2058 <1 18 RK_FUNC_1 &pcfg_pull_up>;
2062 <1 15 RK_FUNC_1 &pcfg_pull_up>;
2066 <1 16 RK_FUNC_1 &pcfg_pull_up>;
2071 spi4_clk: spi4-clk {
2073 <3 2 RK_FUNC_2 &pcfg_pull_up>;
2075 spi4_cs0: spi4-cs0 {
2077 <3 3 RK_FUNC_2 &pcfg_pull_up>;
2081 <3 0 RK_FUNC_2 &pcfg_pull_up>;
2085 <3 1 RK_FUNC_2 &pcfg_pull_up>;
2090 spi5_clk: spi5-clk {
2092 <2 22 RK_FUNC_2 &pcfg_pull_up>;
2094 spi5_cs0: spi5-cs0 {
2096 <2 23 RK_FUNC_2 &pcfg_pull_up>;
2100 <2 20 RK_FUNC_2 &pcfg_pull_up>;
2104 <2 21 RK_FUNC_2 &pcfg_pull_up>;
2109 otp_gpio: otp-gpio {
2110 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
2114 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
2119 uart0_xfer: uart0-xfer {
2121 <2 16 RK_FUNC_1 &pcfg_pull_up>,
2122 <2 17 RK_FUNC_1 &pcfg_pull_none>;
2125 uart0_cts: uart0-cts {
2127 <2 18 RK_FUNC_1 &pcfg_pull_none>;
2130 uart0_rts: uart0-rts {
2132 <2 19 RK_FUNC_1 &pcfg_pull_none>;
2137 uart1_xfer: uart1-xfer {
2139 <3 12 RK_FUNC_2 &pcfg_pull_up>,
2140 <3 13 RK_FUNC_2 &pcfg_pull_none>;
2145 uart2a_xfer: uart2a-xfer {
2147 <4 8 RK_FUNC_2 &pcfg_pull_up>,
2148 <4 9 RK_FUNC_2 &pcfg_pull_none>;
2153 uart2b_xfer: uart2b-xfer {
2155 <4 16 RK_FUNC_2 &pcfg_pull_up>,
2156 <4 17 RK_FUNC_2 &pcfg_pull_none>;
2161 uart2c_xfer: uart2c-xfer {
2163 <4 19 RK_FUNC_1 &pcfg_pull_up>,
2164 <4 20 RK_FUNC_1 &pcfg_pull_none>;
2169 uart3_xfer: uart3-xfer {
2171 <3 14 RK_FUNC_2 &pcfg_pull_up>,
2172 <3 15 RK_FUNC_2 &pcfg_pull_none>;
2175 uart3_cts: uart3-cts {
2177 <3 18 RK_FUNC_2 &pcfg_pull_none>;
2180 uart3_rts: uart3-rts {
2182 <3 19 RK_FUNC_2 &pcfg_pull_none>;
2187 uart4_xfer: uart4-xfer {
2189 <1 7 RK_FUNC_1 &pcfg_pull_up>,
2190 <1 8 RK_FUNC_1 &pcfg_pull_none>;
2195 uarthdcp_xfer: uarthdcp-xfer {
2197 <4 21 RK_FUNC_2 &pcfg_pull_up>,
2198 <4 22 RK_FUNC_2 &pcfg_pull_none>;
2203 pwm0_pin: pwm0-pin {
2205 <4 18 RK_FUNC_1 &pcfg_pull_none>;
2208 vop0_pwm_pin: vop0-pwm-pin {
2210 <4 18 RK_FUNC_2 &pcfg_pull_none>;
2215 pwm1_pin: pwm1-pin {
2217 <4 22 RK_FUNC_1 &pcfg_pull_none>;
2220 vop1_pwm_pin: vop1-pwm-pin {
2222 <4 18 RK_FUNC_3 &pcfg_pull_none>;
2227 pwm2_pin: pwm2-pin {
2229 <1 19 RK_FUNC_1 &pcfg_pull_none>;
2234 pwm3a_pin: pwm3a-pin {
2236 <0 6 RK_FUNC_1 &pcfg_pull_none>;
2241 pwm3b_pin: pwm3b-pin {
2243 <1 14 RK_FUNC_1 &pcfg_pull_none>;
2250 <4 23 RK_FUNC_2 &pcfg_pull_none>;
2255 hdmi_i2c_xfer: hdmi-i2c-xfer {
2257 <4 17 RK_FUNC_3 &pcfg_pull_none>,
2258 <4 16 RK_FUNC_3 &pcfg_pull_none>;
2261 hdmi_cec: hdmi-cec {
2263 <4 23 RK_FUNC_1 &pcfg_pull_none>;
2268 pcie_clkreqn: pci-clkreqn {
2270 <2 26 RK_FUNC_2 &pcfg_pull_none>;
2273 pcie_clkreqnb: pci-clkreqnb {
2275 <4 24 RK_FUNC_1 &pcfg_pull_none>;