2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/clock/rk3399-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/interrupt-controller/irq.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/power/rk3399-power.h>
49 #include <dt-bindings/thermal/thermal.h>
52 compatible = "rockchip,rk3399";
53 interrupt-parent = <&gic>;
75 compatible = "arm,psci-1.0";
111 compatible = "arm,cortex-a53", "arm,armv8";
113 enable-method = "psci";
114 #cooling-cells = <2>; /* min followed by max */
115 clocks = <&cru ARMCLKL>;
116 operating-points-v2 = <&cluster0_opp>;
121 compatible = "arm,cortex-a53", "arm,armv8";
123 enable-method = "psci";
124 clocks = <&cru ARMCLKL>;
125 operating-points-v2 = <&cluster0_opp>;
130 compatible = "arm,cortex-a53", "arm,armv8";
132 enable-method = "psci";
133 clocks = <&cru ARMCLKL>;
134 operating-points-v2 = <&cluster0_opp>;
139 compatible = "arm,cortex-a53", "arm,armv8";
141 enable-method = "psci";
142 clocks = <&cru ARMCLKL>;
143 operating-points-v2 = <&cluster0_opp>;
148 compatible = "arm,cortex-a72", "arm,armv8";
150 enable-method = "psci";
151 #cooling-cells = <2>; /* min followed by max */
152 clocks = <&cru ARMCLKB>;
153 operating-points-v2 = <&cluster1_opp>;
158 compatible = "arm,cortex-a72", "arm,armv8";
160 enable-method = "psci";
161 clocks = <&cru ARMCLKB>;
162 operating-points-v2 = <&cluster1_opp>;
166 cluster0_opp: opp_table0 {
167 compatible = "operating-points-v2";
171 opp-hz = /bits/ 64 <408000000>;
172 opp-microvolt = <800000>;
173 clock-latency-ns = <40000>;
176 opp-hz = /bits/ 64 <600000000>;
177 opp-microvolt = <800000>;
180 opp-hz = /bits/ 64 <816000000>;
181 opp-microvolt = <800000>;
184 opp-hz = /bits/ 64 <1008000000>;
185 opp-microvolt = <875000>;
188 opp-hz = /bits/ 64 <1200000000>;
189 opp-microvolt = <925000>;
192 opp-hz = /bits/ 64 <1416000000>;
193 opp-microvolt = <1025000>;
197 cluster1_opp: opp_table1 {
198 compatible = "operating-points-v2";
202 opp-hz = /bits/ 64 <408000000>;
203 opp-microvolt = <800000>;
204 clock-latency-ns = <40000>;
207 opp-hz = /bits/ 64 <600000000>;
208 opp-microvolt = <800000>;
211 opp-hz = /bits/ 64 <816000000>;
212 opp-microvolt = <800000>;
215 opp-hz = /bits/ 64 <1008000000>;
216 opp-microvolt = <850000>;
219 opp-hz = /bits/ 64 <1200000000>;
220 opp-microvolt = <925000>;
225 compatible = "arm,armv8-timer";
226 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
227 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
228 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
229 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
233 compatible = "arm,armv8-pmuv3";
234 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
238 compatible = "fixed-clock";
240 clock-frequency = <24000000>;
241 clock-output-names = "xin24m";
245 compatible = "arm,amba-bus";
246 #address-cells = <2>;
250 dmac_bus: dma-controller@ff6d0000 {
251 compatible = "arm,pl330", "arm,primecell";
252 reg = <0x0 0xff6d0000 0x0 0x4000>;
253 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
254 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
256 clocks = <&cru ACLK_DMAC0_PERILP>;
257 clock-names = "apb_pclk";
260 dmac_peri: dma-controller@ff6e0000 {
261 compatible = "arm,pl330", "arm,primecell";
262 reg = <0x0 0xff6e0000 0x0 0x4000>;
263 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
264 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
266 clocks = <&cru ACLK_DMAC1_PERILP>;
267 clock-names = "apb_pclk";
272 compatible = "rockchip,rk3399-gmac";
273 reg = <0x0 0xfe300000 0x0 0x10000>;
274 rockchip,grf = <&grf>;
275 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
276 interrupt-names = "macirq";
277 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
278 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
279 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
281 clock-names = "stmmaceth", "mac_clk_rx",
282 "mac_clk_tx", "clk_mac_ref",
283 "clk_mac_refout", "aclk_mac",
285 resets = <&cru SRST_A_GMAC>;
286 reset-names = "stmmaceth";
291 compatible = "rockchip,rk3399-emmc-phy";
292 reg-offset = <0xf780>;
294 rockchip,grf = <&grf>;
298 sdio0: dwmmc@fe310000 {
299 compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc";
300 reg = <0x0 0xfe310000 0x0 0x4000>;
301 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
302 clock-freq-min-max = <400000 150000000>;
303 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
304 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
305 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
306 fifo-depth = <0x100>;
310 sdmmc: dwmmc@fe320000 {
311 compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc";
312 reg = <0x0 0xfe320000 0x0 0x4000>;
313 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
314 clock-freq-min-max = <400000 150000000>;
315 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
316 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
317 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
318 fifo-depth = <0x100>;
322 sdhci: sdhci@fe330000 {
323 compatible = "arasan,sdhci-5.1";
324 reg = <0x0 0xfe330000 0x0 0x10000>;
325 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
326 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
327 clock-names = "clk_xin", "clk_ahb";
329 phy-names = "phy_arasan";
334 compatible = "rockchip,rk3399-usb-phy";
335 rockchip,grf = <&grf>;
336 #address-cells = <1>;
339 usb2phy0: usb2-phy0 {
345 usb2phy1: usb2-phy1 {
352 usb_host0_echi: usb@fe380000 {
353 compatible = "generic-ehci";
354 reg = <0x0 0xfe380000 0x0 0x20000>;
355 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
356 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
357 clock-names = "hclk_host0", "hclk_host0_arb";
359 phy-names = "usb2_phy0";
363 usb_host0_ohci: usb@fe3a0000 {
364 compatible = "generic-ohci";
365 reg = <0x0 0xfe3a0000 0x0 0x20000>;
366 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
367 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
368 clock-names = "hclk_host0", "hclk_host0_arb";
372 usb_host1_echi: usb@fe3c0000 {
373 compatible = "generic-ehci";
374 reg = <0x0 0xfe3c0000 0x0 0x20000>;
375 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
376 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
377 clock-names = "hclk_host1", "hclk_host1_arb";
379 phy-names = "usb2_phy1";
383 usb_host1_ohci: usb@fe3e0000 {
384 compatible = "generic-ohci";
385 reg = <0x0 0xfe3e0000 0x0 0x20000>;
386 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
387 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
388 clock-names = "hclk_host1", "hclk_host1_arb";
392 usbdrd3_0: usb@fe800000 {
393 compatible = "rockchip,dwc3";
394 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
395 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
396 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
397 clock-names = "clk_usb3otg0_ref", "clk_usb3otg0_suspend",
398 "aclk_usb3otg0", "aclk_usb3_rksoc_axi_perf",
399 "aclk_usb3", "aclk_usb3_grf";
400 #address-cells = <2>;
404 usbdrd_dwc3_0: dwc3 {
405 compatible = "snps,dwc3";
406 reg = <0x0 0xfe800000 0x0 0x100000>;
407 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
410 snps,dis_enblslpm_quirk;
411 snps,phyif_utmi_16_bits;
412 snps,dis_u2_freeclk_exists_quirk;
413 snps,dis_del_phy_power_chg_quirk;
418 usbdrd3_1: usb@fe900000 {
419 compatible = "rockchip,dwc3";
420 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
421 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
422 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
423 clock-names = "clk_usb3otg1_ref", "clk_usb3otg1_suspend",
424 "aclk_usb3otg1", "aclk_usb3_rksoc_axi_perf",
425 "aclk_usb3", "aclk_usb3_grf";
426 #address-cells = <2>;
430 usbdrd_dwc3_1: dwc3 {
431 compatible = "snps,dwc3";
432 reg = <0x0 0xfe900000 0x0 0x100000>;
433 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
436 snps,dis_enblslpm_quirk;
437 snps,phyif_utmi_16_bits;
438 snps,dis_u2_freeclk_exists_quirk;
439 snps,dis_del_phy_power_chg_quirk;
444 gic: interrupt-controller@fee00000 {
445 compatible = "arm,gic-v3";
446 #interrupt-cells = <3>;
447 #address-cells = <2>;
450 interrupt-controller;
452 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
453 <0x0 0xfef00000 0 0xc0000>, /* GICR */
454 <0x0 0xfff00000 0 0x10000>, /* GICC */
455 <0x0 0xfff10000 0 0x10000>, /* GICH */
456 <0x0 0xfff20000 0 0x10000>; /* GICV */
457 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
458 its: interrupt-controller@fee20000 {
459 compatible = "arm,gic-v3-its";
461 reg = <0x0 0xfee20000 0x0 0x20000>;
465 saradc: saradc@ff100000 {
466 compatible = "rockchip,rk3399-saradc";
467 reg = <0x0 0xff100000 0x0 0x100>;
468 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
469 #io-channel-cells = <1>;
470 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
471 clock-names = "saradc", "apb_pclk";
476 compatible = "rockchip,rk3399-i2c";
477 reg = <0x0 0xff3c0000 0x0 0x1000>;
478 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
479 clock-names = "i2c", "pclk";
480 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
481 pinctrl-names = "default";
482 pinctrl-0 = <&i2c0_xfer>;
483 #address-cells = <1>;
489 compatible = "rockchip,rk3399-i2c";
490 reg = <0x0 0xff110000 0x0 0x1000>;
491 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
492 clock-names = "i2c", "pclk";
493 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
494 pinctrl-names = "default";
495 pinctrl-0 = <&i2c1_xfer>;
496 #address-cells = <1>;
502 compatible = "rockchip,rk3399-i2c";
503 reg = <0x0 0xff120000 0x0 0x1000>;
504 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
505 clock-names = "i2c", "pclk";
506 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
507 pinctrl-names = "default";
508 pinctrl-0 = <&i2c2_xfer>;
509 #address-cells = <1>;
515 compatible = "rockchip,rk3399-i2c";
516 reg = <0x0 0xff130000 0x0 0x1000>;
517 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
518 clock-names = "i2c", "pclk";
519 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
520 pinctrl-names = "default";
521 pinctrl-0 = <&i2c3_xfer>;
522 #address-cells = <1>;
528 compatible = "rockchip,rk3399-i2c";
529 reg = <0x0 0xff140000 0x0 0x1000>;
530 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
531 clock-names = "i2c", "pclk";
532 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
533 pinctrl-names = "default";
534 pinctrl-0 = <&i2c5_xfer>;
535 #address-cells = <1>;
541 compatible = "rockchip,rk3399-i2c";
542 reg = <0x0 0xff150000 0x0 0x1000>;
543 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
544 clock-names = "i2c", "pclk";
545 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
546 pinctrl-names = "default";
547 pinctrl-0 = <&i2c6_xfer>;
548 #address-cells = <1>;
554 compatible = "rockchip,rk3399-i2c";
555 reg = <0x0 0xff160000 0x0 0x1000>;
556 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
557 clock-names = "i2c", "pclk";
558 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
559 pinctrl-names = "default";
560 pinctrl-0 = <&i2c7_xfer>;
561 #address-cells = <1>;
566 uart0: serial@ff180000 {
567 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
568 reg = <0x0 0xff180000 0x0 0x100>;
569 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
570 clock-names = "baudclk", "apb_pclk";
571 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
574 pinctrl-names = "default";
575 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
579 uart1: serial@ff190000 {
580 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
581 reg = <0x0 0xff190000 0x0 0x100>;
582 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
583 clock-names = "baudclk", "apb_pclk";
584 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
587 pinctrl-names = "default";
588 pinctrl-0 = <&uart1_xfer>;
592 uart2: serial@ff1a0000 {
593 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
594 reg = <0x0 0xff1a0000 0x0 0x100>;
595 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
596 clock-names = "baudclk", "apb_pclk";
597 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
600 pinctrl-names = "default";
601 pinctrl-0 = <&uart2c_xfer>;
605 uart3: serial@ff1b0000 {
606 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
607 reg = <0x0 0xff1b0000 0x0 0x100>;
608 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
609 clock-names = "baudclk", "apb_pclk";
610 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
613 pinctrl-names = "default";
614 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
619 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
620 reg = <0x0 0xff1c0000 0x0 0x1000>;
621 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
622 clock-names = "spiclk", "apb_pclk";
623 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
624 pinctrl-names = "default";
625 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
626 #address-cells = <1>;
632 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
633 reg = <0x0 0xff1d0000 0x0 0x1000>;
634 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
635 clock-names = "spiclk", "apb_pclk";
636 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
637 pinctrl-names = "default";
638 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
639 #address-cells = <1>;
645 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
646 reg = <0x0 0xff1e0000 0x0 0x1000>;
647 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
648 clock-names = "spiclk", "apb_pclk";
649 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
650 pinctrl-names = "default";
651 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
652 #address-cells = <1>;
658 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
659 reg = <0x0 0xff1f0000 0x0 0x1000>;
660 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
661 clock-names = "spiclk", "apb_pclk";
662 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
663 pinctrl-names = "default";
664 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
665 #address-cells = <1>;
671 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
672 reg = <0x0 0xff200000 0x0 0x1000>;
673 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
674 clock-names = "spiclk", "apb_pclk";
675 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
676 pinctrl-names = "default";
677 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
678 #address-cells = <1>;
685 polling-delay-passive = <100>; /* milliseconds */
686 polling-delay = <1000>; /* milliseconds */
688 thermal-sensors = <&tsadc 0>;
691 cpu_alert0: cpu_alert0 {
692 temperature = <70000>; /* millicelsius */
693 hysteresis = <2000>; /* millicelsius */
696 cpu_alert1: cpu_alert1 {
697 temperature = <75000>; /* millicelsius */
698 hysteresis = <2000>; /* millicelsius */
702 temperature = <95000>; /* millicelsius */
703 hysteresis = <2000>; /* millicelsius */
710 trip = <&cpu_alert0>;
712 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
715 trip = <&cpu_alert1>;
717 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
723 polling-delay-passive = <100>; /* milliseconds */
724 polling-delay = <1000>; /* milliseconds */
726 thermal-sensors = <&tsadc 1>;
729 gpu_alert0: gpu_alert0 {
730 temperature = <75000>; /* millicelsius */
731 hysteresis = <2000>; /* millicelsius */
735 temperature = <950000>; /* millicelsius */
736 hysteresis = <2000>; /* millicelsius */
743 trip = <&gpu_alert0>;
745 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
751 tsadc: tsadc@ff260000 {
752 compatible = "rockchip,rk3399-tsadc";
753 reg = <0x0 0xff260000 0x0 0x100>;
754 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
755 rockchip,grf = <&grf>;
756 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
757 clock-names = "tsadc", "apb_pclk";
758 assigned-clocks = <&cru SCLK_TSADC>;
759 assigned-clock-rates = <750000>;
760 resets = <&cru SRST_TSADC>;
761 reset-names = "tsadc-apb";
762 pinctrl-names = "init", "default", "sleep";
763 pinctrl-0 = <&otp_gpio>;
764 pinctrl-1 = <&otp_out>;
765 pinctrl-2 = <&otp_gpio>;
766 #thermal-sensor-cells = <1>;
767 rockchip,hw-tshut-temp = <95000>;
771 pmu: power-management@ff31000 {
772 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
773 reg = <0x0 0xff310000 0x0 0x1000>;
775 power: power-controller {
777 compatible = "rockchip,rk3399-power-controller";
778 #power-domain-cells = <1>;
779 #address-cells = <1>;
783 reg = <RK3399_PD_CENTER>;
784 #address-cells = <1>;
788 reg = <RK3399_PD_VDU>;
791 reg = <RK3399_PD_VCODEC>;
794 reg = <RK3399_PD_IEP>;
797 reg = <RK3399_PD_RGA>;
801 reg = <RK3399_PD_VIO>;
802 #address-cells = <1>;
806 reg = <RK3399_PD_ISP0>;
809 reg = <RK3399_PD_ISP1>;
812 reg = <RK3399_PD_HDCP>;
815 reg = <RK3399_PD_VO>;
816 #address-cells = <1>;
820 reg = <RK3399_PD_VOPB>;
823 reg = <RK3399_PD_VOPL>;
828 reg = <RK3399_PD_GPU>;
833 pmugrf: syscon@ff320000 {
834 compatible = "rockchip,rk3399-pmugrf", "syscon";
835 reg = <0x0 0xff320000 0x0 0x1000>;
839 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
840 reg = <0x0 0xff350000 0x0 0x1000>;
841 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
842 clock-names = "spiclk", "apb_pclk";
843 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
844 pinctrl-names = "default";
845 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
846 #address-cells = <1>;
851 uart4: serial@ff370000 {
852 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
853 reg = <0x0 0xff370000 0x0 0x100>;
854 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
855 clock-names = "baudclk", "apb_pclk";
856 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
859 pinctrl-names = "default";
860 pinctrl-0 = <&uart4_xfer>;
865 compatible = "rockchip,rk3399-i2c";
866 reg = <0x0 0xff3d0000 0x0 0x1000>;
867 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
868 clock-names = "i2c", "pclk";
869 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
870 pinctrl-names = "default";
871 pinctrl-0 = <&i2c4_xfer>;
872 #address-cells = <1>;
878 compatible = "rockchip,rk3399-i2c";
879 reg = <0x0 0xff3e0000 0x0 0x1000>;
880 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
881 clock-names = "i2c", "pclk";
882 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
883 pinctrl-names = "default";
884 pinctrl-0 = <&i2c8_xfer>;
885 #address-cells = <1>;
891 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
892 reg = <0x0 0xff420000 0x0 0x10>;
894 pinctrl-names = "default";
895 pinctrl-0 = <&pwm0_pin>;
896 clocks = <&pmucru PCLK_RKPWM_PMU>;
902 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
903 reg = <0x0 0xff420010 0x0 0x10>;
905 pinctrl-names = "default";
906 pinctrl-0 = <&pwm1_pin>;
907 clocks = <&pmucru PCLK_RKPWM_PMU>;
913 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
914 reg = <0x0 0xff420020 0x0 0x10>;
916 pinctrl-names = "default";
917 pinctrl-0 = <&pwm2_pin>;
918 clocks = <&pmucru PCLK_RKPWM_PMU>;
924 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
925 reg = <0x0 0xff420030 0x0 0x10>;
927 pinctrl-names = "default";
928 pinctrl-0 = <&pwm3a_pin>;
929 clocks = <&pmucru PCLK_RKPWM_PMU>;
935 compatible = "rockchip,rk3399-rga";
936 reg = <0x0 0xff680000 0x0 0x10000>;
937 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
938 interrupt-names = "rga";
939 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
940 clock-names = "aclk", "hclk", "sclk";
941 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
942 reset-names = "core", "axi", "ahb";
946 pmucru: pmu-clock-controller@ff750000 {
947 compatible = "rockchip,rk3399-pmucru";
948 reg = <0x0 0xff750000 0x0 0x1000>;
951 assigned-clocks = <&pmucru PLL_PPLL>;
952 assigned-clock-rates = <676000000>;
955 cru: clock-controller@ff760000 {
956 compatible = "rockchip,rk3399-cru";
957 reg = <0x0 0xff760000 0x0 0x1000>;
961 <&cru ACLK_VOP0>, <&cru HCLK_VOP0>,
962 <&cru ACLK_VOP1>, <&cru HCLK_VOP1>,
963 <&cru ARMCLKL>, <&cru ARMCLKB>,
964 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
966 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
968 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
970 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
971 assigned-clock-rates =
972 <400000000>, <200000000>,
973 <400000000>, <200000000>,
974 <816000000>, <1008000000>,
975 <594000000>, <800000000>,
977 <150000000>, <75000000>,
979 <100000000>, <100000000>,
981 <100000000>, <50000000>;
984 grf: syscon@ff770000 {
985 compatible = "rockchip,rk3399-grf", "syscon";
986 reg = <0x0 0xff770000 0x0 0x10000>;
989 wdt0: watchdog@ff840000 {
990 compatible = "snps,dw-wdt";
991 reg = <0x0 0xff840000 0x0 0x100>;
992 clocks = <&cru PCLK_WDT>;
993 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
997 spdif: spdif@ff870000 {
998 compatible = "rockchip,rk3399-spdif";
999 reg = <0x0 0xff870000 0x0 0x1000>;
1000 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
1001 dmas = <&dmac_bus 7>;
1003 clock-names = "mclk", "hclk";
1004 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1005 pinctrl-names = "default";
1006 pinctrl-0 = <&spdif_bus>;
1007 status = "disabled";
1010 i2s0: i2s@ff880000 {
1011 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1012 reg = <0x0 0xff880000 0x0 0x1000>;
1013 rockchip,grf = <&grf>;
1014 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1015 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1016 dma-names = "tx", "rx";
1017 clock-names = "i2s_clk", "i2s_hclk";
1018 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1019 pinctrl-names = "default";
1020 pinctrl-0 = <&i2s0_8ch_bus>;
1021 status = "disabled";
1024 i2s1: i2s@ff890000 {
1025 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1026 reg = <0x0 0xff890000 0x0 0x1000>;
1027 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1028 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1029 dma-names = "tx", "rx";
1030 clock-names = "i2s_clk", "i2s_hclk";
1031 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1032 pinctrl-names = "default";
1033 pinctrl-0 = <&i2s1_2ch_bus>;
1034 status = "disabled";
1037 i2s2: i2s@ff8a0000 {
1038 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1039 reg = <0x0 0xff8a0000 0x0 0x1000>;
1040 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1041 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1042 dma-names = "tx", "rx";
1043 clock-names = "i2s_clk", "i2s_hclk";
1044 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1045 status = "disabled";
1049 compatible = "arm,malit860",
1054 reg = <0x0 0xff9a0000 0x0 0x10000>;
1056 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
1057 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
1058 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1059 interrupt-names = "GPU", "JOB", "MMU";
1061 clocks = <&cru ACLK_GPU>;
1062 clock-names = "clk_mali";
1063 #cooling-cells = <2>; /* min followed by max */
1064 operating-points-v2 = <&gpu_opp_table>;
1065 status = "disabled";
1068 gpu_opp_table: gpu_opp_table {
1069 compatible = "operating-points-v2";
1073 opp-hz = /bits/ 64 <200000000>;
1074 opp-microvolt = <900000>;
1077 opp-hz = /bits/ 64 <300000000>;
1078 opp-microvolt = <900000>;
1081 opp-hz = /bits/ 64 <400000000>;
1082 opp-microvolt = <900000>;
1087 vopl: vop@ff8f0000 {
1088 compatible = "rockchip,rk3399-vop-lit";
1089 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1090 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
1091 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1092 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1093 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1094 reset-names = "axi", "ahb", "dclk";
1095 iommus = <&vopl_mmu>;
1096 status = "disabled";
1099 #address-cells = <1>;
1102 vopl_out_mipi: endpoint@0 {
1104 remote-endpoint = <&mipi_in_vopl>;
1107 vopl_out_edp: endpoint@1 {
1109 remote-endpoint = <&edp_in_vopl>;
1114 vopl_mmu: iommu@ff8f3f00 {
1115 compatible = "rockchip,iommu";
1116 reg = <0x0 0xff8f3f00 0x0 0x100>;
1117 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
1118 interrupt-names = "vopl_mmu";
1120 status = "disabled";
1123 vopb: vop@ff900000 {
1124 compatible = "rockchip,rk3399-vop-big";
1125 reg = <0x0 0xff900000 0x0 0x3efc>;
1126 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1127 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1128 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1129 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1130 reset-names = "axi", "ahb", "dclk";
1131 iommus = <&vopb_mmu>;
1132 status = "disabled";
1135 #address-cells = <1>;
1138 vopb_out_edp: endpoint@0 {
1140 remote-endpoint = <&edp_in_vopb>;
1143 vopb_out_mipi: endpoint@1 {
1145 remote-endpoint = <&mipi_in_vopb>;
1150 vopb_mmu: iommu@ff903f00 {
1151 compatible = "rockchip,iommu";
1152 reg = <0x0 0xff903f00 0x0 0x100>;
1153 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1154 interrupt-names = "vopb_mmu";
1156 status = "disabled";
1159 mipi_dsi: mipi@ff960000 {
1160 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1161 reg = <0x0 0xff960000 0x0 0x8000>;
1162 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1163 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
1164 <&cru SCLK_DPHY_TX0_CFG>;
1165 clock-names = "ref", "pclk", "phy_cfg";
1166 rockchip,grf = <&grf>;
1167 #address-cells = <1>;
1169 status = "disabled";
1172 #address-cells = <1>;
1177 #address-cells = <1>;
1180 mipi_in_vopb: endpoint@0 {
1182 remote-endpoint = <&vopb_out_mipi>;
1184 mipi_in_vopl: endpoint@1 {
1186 remote-endpoint = <&vopl_out_mipi>;
1193 compatible = "rockchip,rk3399-edp";
1194 reg = <0x0 0xff970000 0x0 0x8000>;
1195 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1196 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1197 clock-names = "dp", "pclk";
1198 resets = <&cru SRST_P_EDP_CTRL>;
1200 rockchip,grf = <&grf>;
1201 status = "disabled";
1202 pinctrl-names = "default";
1203 pinctrl-0 = <&edp_hpd>;
1206 #address-cells = <1>;
1211 #address-cells = <1>;
1214 edp_in_vopb: endpoint@0 {
1216 remote-endpoint = <&vopb_out_edp>;
1219 edp_in_vopl: endpoint@1 {
1221 remote-endpoint = <&vopl_out_edp>;
1227 display_subsystem: display-subsystem {
1228 compatible = "rockchip,display-subsystem";
1229 ports = <&vopl_out>, <&vopb_out>;
1230 status = "disabled";
1234 compatible = "rockchip,rk3399-pinctrl";
1235 rockchip,grf = <&grf>;
1236 rockchip,pmu = <&pmugrf>;
1237 #address-cells = <0x2>;
1238 #size-cells = <0x2>;
1241 gpio0: gpio0@ff720000 {
1242 compatible = "rockchip,gpio-bank";
1243 reg = <0x0 0xff720000 0x0 0x100>;
1244 clocks = <&pmucru PCLK_GPIO0_PMU>;
1245 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1248 #gpio-cells = <0x2>;
1250 interrupt-controller;
1251 #interrupt-cells = <0x2>;
1254 gpio1: gpio1@ff730000 {
1255 compatible = "rockchip,gpio-bank";
1256 reg = <0x0 0xff730000 0x0 0x100>;
1257 clocks = <&pmucru PCLK_GPIO1_PMU>;
1258 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1261 #gpio-cells = <0x2>;
1263 interrupt-controller;
1264 #interrupt-cells = <0x2>;
1267 gpio2: gpio2@ff780000 {
1268 compatible = "rockchip,gpio-bank";
1269 reg = <0x0 0xff780000 0x0 0x100>;
1270 clocks = <&cru PCLK_GPIO2>;
1271 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1274 #gpio-cells = <0x2>;
1276 interrupt-controller;
1277 #interrupt-cells = <0x2>;
1280 gpio3: gpio3@ff788000 {
1281 compatible = "rockchip,gpio-bank";
1282 reg = <0x0 0xff788000 0x0 0x100>;
1283 clocks = <&cru PCLK_GPIO3>;
1284 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1287 #gpio-cells = <0x2>;
1289 interrupt-controller;
1290 #interrupt-cells = <0x2>;
1293 gpio4: gpio4@ff790000 {
1294 compatible = "rockchip,gpio-bank";
1295 reg = <0x0 0xff790000 0x0 0x100>;
1296 clocks = <&cru PCLK_GPIO4>;
1297 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1300 #gpio-cells = <0x2>;
1302 interrupt-controller;
1303 #interrupt-cells = <0x2>;
1306 pcfg_pull_up: pcfg-pull-up {
1310 pcfg_pull_down: pcfg-pull-down {
1314 pcfg_pull_none: pcfg-pull-none {
1318 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1320 drive-strength = <12>;
1323 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1325 drive-strength = <8>;
1328 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1330 drive-strength = <4>;
1333 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1335 drive-strength = <2>;
1338 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
1340 drive-strength = <12>;
1343 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
1345 drive-strength = <13>;
1349 emmc_pwr: emmc-pwr {
1351 <0 5 RK_FUNC_1 &pcfg_pull_up>;
1356 rgmii_pins: rgmii-pins {
1359 <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
1361 <3 14 RK_FUNC_1 &pcfg_pull_none>,
1363 <3 13 RK_FUNC_1 &pcfg_pull_none>,
1365 <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1367 <3 11 RK_FUNC_1 &pcfg_pull_none>,
1369 <3 9 RK_FUNC_1 &pcfg_pull_none>,
1371 <3 8 RK_FUNC_1 &pcfg_pull_none>,
1373 <3 7 RK_FUNC_1 &pcfg_pull_none>,
1375 <3 6 RK_FUNC_1 &pcfg_pull_none>,
1377 <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1379 <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
1381 <3 3 RK_FUNC_1 &pcfg_pull_none>,
1383 <3 2 RK_FUNC_1 &pcfg_pull_none>,
1385 <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
1387 <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
1390 rmii_pins: rmii-pins {
1393 <3 13 RK_FUNC_1 &pcfg_pull_none>,
1395 <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1397 <3 11 RK_FUNC_1 &pcfg_pull_none>,
1399 <3 10 RK_FUNC_1 &pcfg_pull_none>,
1401 <3 9 RK_FUNC_1 &pcfg_pull_none>,
1403 <3 8 RK_FUNC_1 &pcfg_pull_none>,
1405 <3 7 RK_FUNC_1 &pcfg_pull_none>,
1407 <3 6 RK_FUNC_1 &pcfg_pull_none>,
1409 <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1411 <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
1416 i2c0_xfer: i2c0-xfer {
1418 <1 15 RK_FUNC_2 &pcfg_pull_none>,
1419 <1 16 RK_FUNC_2 &pcfg_pull_none>;
1424 i2c1_xfer: i2c1-xfer {
1426 <4 2 RK_FUNC_1 &pcfg_pull_none>,
1427 <4 1 RK_FUNC_1 &pcfg_pull_none>;
1432 i2c2_xfer: i2c2-xfer {
1434 <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1435 <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
1440 i2c3_xfer: i2c3-xfer {
1442 <4 17 RK_FUNC_1 &pcfg_pull_none>,
1443 <4 16 RK_FUNC_1 &pcfg_pull_none>;
1448 i2c4_xfer: i2c4-xfer {
1450 <1 12 RK_FUNC_1 &pcfg_pull_none>,
1451 <1 11 RK_FUNC_1 &pcfg_pull_none>;
1456 i2c5_xfer: i2c5-xfer {
1458 <3 11 RK_FUNC_2 &pcfg_pull_none>,
1459 <3 10 RK_FUNC_2 &pcfg_pull_none>;
1464 i2c6_xfer: i2c6-xfer {
1466 <2 10 RK_FUNC_2 &pcfg_pull_none>,
1467 <2 9 RK_FUNC_2 &pcfg_pull_none>;
1472 i2c7_xfer: i2c7-xfer {
1474 <2 8 RK_FUNC_2 &pcfg_pull_none>,
1475 <2 7 RK_FUNC_2 &pcfg_pull_none>;
1480 i2c8_xfer: i2c8-xfer {
1482 <1 21 RK_FUNC_1 &pcfg_pull_none>,
1483 <1 20 RK_FUNC_1 &pcfg_pull_none>;
1488 i2s0_8ch_bus: i2s0-8ch-bus {
1490 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1491 <3 25 RK_FUNC_1 &pcfg_pull_none>,
1492 <3 26 RK_FUNC_1 &pcfg_pull_none>,
1493 <3 27 RK_FUNC_1 &pcfg_pull_none>,
1494 <3 28 RK_FUNC_1 &pcfg_pull_none>,
1495 <3 29 RK_FUNC_1 &pcfg_pull_none>,
1496 <3 30 RK_FUNC_1 &pcfg_pull_none>,
1497 <3 31 RK_FUNC_1 &pcfg_pull_none>,
1498 <4 0 RK_FUNC_1 &pcfg_pull_none>;
1503 i2s1_2ch_bus: i2s1-2ch-bus {
1505 <4 3 RK_FUNC_1 &pcfg_pull_none>,
1506 <4 4 RK_FUNC_1 &pcfg_pull_none>,
1507 <4 5 RK_FUNC_1 &pcfg_pull_none>,
1508 <4 6 RK_FUNC_1 &pcfg_pull_none>,
1509 <4 7 RK_FUNC_1 &pcfg_pull_none>;
1514 sdio0_bus1: sdio0-bus1 {
1516 <2 20 RK_FUNC_1 &pcfg_pull_up>;
1519 sdio0_bus4: sdio0-bus4 {
1521 <2 20 RK_FUNC_1 &pcfg_pull_up>,
1522 <2 21 RK_FUNC_1 &pcfg_pull_up>,
1523 <2 22 RK_FUNC_1 &pcfg_pull_up>,
1524 <2 23 RK_FUNC_1 &pcfg_pull_up>;
1527 sdio0_cmd: sdio0-cmd {
1529 <2 24 RK_FUNC_1 &pcfg_pull_up>;
1532 sdio0_clk: sdio0-clk {
1534 <2 25 RK_FUNC_1 &pcfg_pull_none>;
1537 sdio0_cd: sdio0-cd {
1539 <2 26 RK_FUNC_1 &pcfg_pull_up>;
1542 sdio0_pwr: sdio0-pwr {
1544 <2 27 RK_FUNC_1 &pcfg_pull_up>;
1547 sdio0_bkpwr: sdio0-bkpwr {
1549 <2 28 RK_FUNC_1 &pcfg_pull_up>;
1552 sdio0_wp: sdio0-wp {
1554 <0 3 RK_FUNC_1 &pcfg_pull_up>;
1557 sdio0_int: sdio0-int {
1559 <0 4 RK_FUNC_1 &pcfg_pull_up>;
1564 sdmmc_bus1: sdmmc-bus1 {
1566 <4 8 RK_FUNC_1 &pcfg_pull_up>;
1569 sdmmc_bus4: sdmmc-bus4 {
1571 <4 8 RK_FUNC_1 &pcfg_pull_up>,
1572 <4 9 RK_FUNC_1 &pcfg_pull_up>,
1573 <4 10 RK_FUNC_1 &pcfg_pull_up>,
1574 <4 11 RK_FUNC_1 &pcfg_pull_up>;
1577 sdmmc_clk: sdmmc-clk {
1579 <4 12 RK_FUNC_1 &pcfg_pull_none>;
1582 sdmmc_cmd: sdmmc-cmd {
1584 <4 13 RK_FUNC_1 &pcfg_pull_up>;
1587 sdmmc_cd: sdmcc-cd {
1589 <0 7 RK_FUNC_1 &pcfg_pull_up>;
1592 sdmmc_wp: sdmmc-wp {
1594 <0 8 RK_FUNC_1 &pcfg_pull_up>;
1599 spdif_bus: spdif-bus {
1601 <4 21 RK_FUNC_1 &pcfg_pull_none>;
1606 spi0_clk: spi0-clk {
1608 <3 6 RK_FUNC_2 &pcfg_pull_up>;
1610 spi0_cs0: spi0-cs0 {
1612 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1614 spi0_cs1: spi0-cs1 {
1616 <3 8 RK_FUNC_2 &pcfg_pull_up>;
1620 <3 5 RK_FUNC_2 &pcfg_pull_up>;
1624 <3 4 RK_FUNC_2 &pcfg_pull_up>;
1629 spi1_clk: spi1-clk {
1631 <1 9 RK_FUNC_2 &pcfg_pull_up>;
1633 spi1_cs0: spi1-cs0 {
1635 <1 10 RK_FUNC_2 &pcfg_pull_up>;
1639 <1 7 RK_FUNC_2 &pcfg_pull_up>;
1643 <1 8 RK_FUNC_2 &pcfg_pull_up>;
1648 spi2_clk: spi2-clk {
1650 <2 11 RK_FUNC_1 &pcfg_pull_up>;
1652 spi2_cs0: spi2-cs0 {
1654 <2 12 RK_FUNC_1 &pcfg_pull_up>;
1658 <2 9 RK_FUNC_1 &pcfg_pull_up>;
1662 <2 10 RK_FUNC_1 &pcfg_pull_up>;
1667 spi3_clk: spi3-clk {
1669 <1 17 RK_FUNC_1 &pcfg_pull_up>;
1671 spi3_cs0: spi3-cs0 {
1673 <1 18 RK_FUNC_1 &pcfg_pull_up>;
1677 <1 15 RK_FUNC_1 &pcfg_pull_up>;
1681 <1 16 RK_FUNC_1 &pcfg_pull_up>;
1686 spi4_clk: spi4-clk {
1688 <3 2 RK_FUNC_2 &pcfg_pull_up>;
1690 spi4_cs0: spi4-cs0 {
1692 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1696 <3 0 RK_FUNC_2 &pcfg_pull_up>;
1700 <3 1 RK_FUNC_2 &pcfg_pull_up>;
1705 spi5_clk: spi5-clk {
1707 <2 22 RK_FUNC_2 &pcfg_pull_up>;
1709 spi5_cs0: spi5-cs0 {
1711 <2 23 RK_FUNC_2 &pcfg_pull_up>;
1715 <2 20 RK_FUNC_2 &pcfg_pull_up>;
1719 <2 21 RK_FUNC_2 &pcfg_pull_up>;
1724 otp_gpio: otp-gpio {
1725 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
1729 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
1734 uart0_xfer: uart0-xfer {
1736 <2 16 RK_FUNC_1 &pcfg_pull_up>,
1737 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1740 uart0_cts: uart0-cts {
1742 <2 18 RK_FUNC_1 &pcfg_pull_none>;
1745 uart0_rts: uart0-rts {
1747 <2 19 RK_FUNC_1 &pcfg_pull_none>;
1752 uart1_xfer: uart1-xfer {
1754 <3 12 RK_FUNC_2 &pcfg_pull_up>,
1755 <3 13 RK_FUNC_2 &pcfg_pull_none>;
1760 uart2a_xfer: uart2a-xfer {
1762 <4 8 RK_FUNC_2 &pcfg_pull_up>,
1763 <4 9 RK_FUNC_2 &pcfg_pull_none>;
1768 uart2b_xfer: uart2b-xfer {
1770 <4 16 RK_FUNC_2 &pcfg_pull_up>,
1771 <4 17 RK_FUNC_2 &pcfg_pull_none>;
1776 uart2c_xfer: uart2c-xfer {
1778 <4 19 RK_FUNC_1 &pcfg_pull_up>,
1779 <4 20 RK_FUNC_1 &pcfg_pull_none>;
1784 uart3_xfer: uart3-xfer {
1786 <3 14 RK_FUNC_2 &pcfg_pull_up>,
1787 <3 15 RK_FUNC_2 &pcfg_pull_none>;
1790 uart3_cts: uart3-cts {
1792 <3 18 RK_FUNC_2 &pcfg_pull_none>;
1795 uart3_rts: uart3-rts {
1797 <3 19 RK_FUNC_2 &pcfg_pull_none>;
1802 uart4_xfer: uart4-xfer {
1804 <1 7 RK_FUNC_1 &pcfg_pull_up>,
1805 <1 8 RK_FUNC_1 &pcfg_pull_none>;
1810 uarthdcp_xfer: uarthdcp-xfer {
1812 <4 21 RK_FUNC_2 &pcfg_pull_up>,
1813 <4 22 RK_FUNC_2 &pcfg_pull_none>;
1818 pwm0_pin: pwm0-pin {
1820 <4 18 RK_FUNC_1 &pcfg_pull_none>;
1823 vop0_pwm_pin: vop0-pwm-pin {
1825 <4 18 RK_FUNC_2 &pcfg_pull_none>;
1830 pwm1_pin: pwm1-pin {
1832 <4 22 RK_FUNC_1 &pcfg_pull_none>;
1835 vop1_pwm_pin: vop1-pwm-pin {
1837 <4 18 RK_FUNC_3 &pcfg_pull_none>;
1842 pwm2_pin: pwm2-pin {
1844 <1 19 RK_FUNC_1 &pcfg_pull_none>;
1849 pwm3a_pin: pwm3a-pin {
1851 <0 6 RK_FUNC_1 &pcfg_pull_none>;
1856 pwm3b_pin: pwm3b-pin {
1858 <1 14 RK_FUNC_1 &pcfg_pull_none>;
1865 <4 23 RK_FUNC_2 &pcfg_pull_none>;