2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/clock/rk3399-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/interrupt-controller/irq.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/power/rk3399-power.h>
49 #include <dt-bindings/thermal/thermal.h>
52 compatible = "rockchip,rk3399";
53 interrupt-parent = <&gic>;
75 compatible = "arm,psci-1.0";
111 compatible = "arm,cortex-a53", "arm,armv8";
113 enable-method = "psci";
114 #cooling-cells = <2>; /* min followed by max */
115 clocks = <&cru ARMCLKL>;
116 operating-points-v2 = <&cluster0_opp>;
121 compatible = "arm,cortex-a53", "arm,armv8";
123 enable-method = "psci";
124 clocks = <&cru ARMCLKL>;
125 operating-points-v2 = <&cluster0_opp>;
130 compatible = "arm,cortex-a53", "arm,armv8";
132 enable-method = "psci";
133 clocks = <&cru ARMCLKL>;
134 operating-points-v2 = <&cluster0_opp>;
139 compatible = "arm,cortex-a53", "arm,armv8";
141 enable-method = "psci";
142 clocks = <&cru ARMCLKL>;
143 operating-points-v2 = <&cluster0_opp>;
148 compatible = "arm,cortex-a72", "arm,armv8";
150 enable-method = "psci";
151 #cooling-cells = <2>; /* min followed by max */
152 clocks = <&cru ARMCLKB>;
153 operating-points-v2 = <&cluster1_opp>;
158 compatible = "arm,cortex-a72", "arm,armv8";
160 enable-method = "psci";
161 clocks = <&cru ARMCLKB>;
162 operating-points-v2 = <&cluster1_opp>;
166 cluster0_opp: opp_table0 {
167 compatible = "operating-points-v2";
171 opp-hz = /bits/ 64 <408000000>;
172 opp-microvolt = <900000>;
173 clock-latency-ns = <40000>;
176 opp-hz = /bits/ 64 <600000000>;
177 opp-microvolt = <900000>;
180 opp-hz = /bits/ 64 <816000000>;
181 opp-microvolt = <900000>;
184 opp-hz = /bits/ 64 <1008000000>;
185 opp-microvolt = <900000>;
189 cluster1_opp: opp_table1 {
190 compatible = "operating-points-v2";
194 opp-hz = /bits/ 64 <408000000>;
195 opp-microvolt = <900000>;
196 clock-latency-ns = <40000>;
199 opp-hz = /bits/ 64 <600000000>;
200 opp-microvolt = <900000>;
203 opp-hz = /bits/ 64 <816000000>;
204 opp-microvolt = <900000>;
207 opp-hz = /bits/ 64 <1008000000>;
208 opp-microvolt = <900000>;
211 opp-hz = /bits/ 64 <1200000000>;
212 opp-microvolt = <900000>;
217 compatible = "arm,armv8-timer";
218 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
219 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
220 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
221 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
225 compatible = "fixed-clock";
227 clock-frequency = <24000000>;
228 clock-output-names = "xin24m";
232 compatible = "arm,amba-bus";
233 #address-cells = <2>;
237 dmac_bus: dma-controller@ff6d0000 {
238 compatible = "arm,pl330", "arm,primecell";
239 reg = <0x0 0xff6d0000 0x0 0x4000>;
240 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
241 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
243 clocks = <&cru ACLK_DMAC0_PERILP>;
244 clock-names = "apb_pclk";
247 dmac_peri: dma-controller@ff6e0000 {
248 compatible = "arm,pl330", "arm,primecell";
249 reg = <0x0 0xff6e0000 0x0 0x4000>;
250 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
251 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
253 clocks = <&cru ACLK_DMAC1_PERILP>;
254 clock-names = "apb_pclk";
259 compatible = "rockchip,rk3399-gmac";
260 reg = <0x0 0xfe300000 0x0 0x10000>;
261 rockchip,grf = <&grf>;
262 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
263 interrupt-names = "macirq";
264 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
265 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
266 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
268 clock-names = "stmmaceth", "mac_clk_rx",
269 "mac_clk_tx", "clk_mac_ref",
270 "clk_mac_refout", "aclk_mac",
272 resets = <&cru SRST_A_GMAC>;
273 reset-names = "stmmaceth";
278 compatible = "rockchip,rk3399-emmc-phy";
279 reg-offset = <0xf780>;
281 rockchip,grf = <&grf>;
285 sdio0: dwmmc@fe310000 {
286 compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc";
287 reg = <0x0 0xfe310000 0x0 0x4000>;
288 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
289 clock-freq-min-max = <400000 150000000>;
290 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
291 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
292 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
293 fifo-depth = <0x100>;
297 sdmmc: dwmmc@fe320000 {
298 compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc";
299 reg = <0x0 0xfe320000 0x0 0x4000>;
300 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
301 clock-freq-min-max = <400000 150000000>;
302 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
303 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
304 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
305 fifo-depth = <0x100>;
309 sdhci: sdhci@fe330000 {
310 compatible = "arasan,sdhci-5.1";
311 reg = <0x0 0xfe330000 0x0 0x10000>;
312 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
313 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
314 clock-names = "clk_xin", "clk_ahb";
316 phy-names = "phy_arasan";
321 compatible = "rockchip,rk3399-usb-phy";
322 rockchip,grf = <&grf>;
323 vbus_drv-gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>;
324 #address-cells = <1>;
327 usb2phy0: usb2-phy0 {
333 usb2phy1: usb2-phy1 {
340 usb_host0_echi: usb@fe380000 {
341 compatible = "generic-ehci";
342 reg = <0x0 0xfe380000 0x0 0x20000>;
343 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
344 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
345 clock-names = "hclk_host0", "hclk_host0_arb";
347 phy-names = "usb2_phy0";
351 usb_host0_ohci: usb@fe3a0000 {
352 compatible = "generic-ohci";
353 reg = <0x0 0xfe3a0000 0x0 0x20000>;
354 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
355 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
356 clock-names = "hclk_host0", "hclk_host0_arb";
360 usb_host1_echi: usb@fe3c0000 {
361 compatible = "generic-ehci";
362 reg = <0x0 0xfe3c0000 0x0 0x20000>;
363 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
364 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
365 clock-names = "hclk_host1", "hclk_host1_arb";
367 phy-names = "usb2_phy1";
371 usb_host1_ohci: usb@fe3e0000 {
372 compatible = "generic-ohci";
373 reg = <0x0 0xfe3e0000 0x0 0x20000>;
374 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
375 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
376 clock-names = "hclk_host1", "hclk_host1_arb";
380 usbdrd3_0: usb@fe800000 {
381 compatible = "rockchip,dwc3";
382 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
383 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
384 <&cru ACLK_USB3>, <&cru ACLK_USB3_NOC>,
385 <&cru ACLK_USB3_GRF>;
386 clock-names = "clk_usb3otg0_ref", "clk_usb3otg0_suspend",
387 "aclk_usb3otg0", "aclk_usb3_rksoc_axi_perf",
388 "aclk_usb3", "aclk_usb3_noc",
390 #address-cells = <2>;
394 usbdrd_dwc3_0: dwc3 {
395 compatible = "snps,dwc3";
396 reg = <0x0 0xfe800000 0x0 0x100000>;
397 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
400 snps,dis_enblslpm_quirk;
401 snps,phyif_utmi_16_bits;
402 snps,dis_u2_freeclk_exists_quirk;
403 snps,dis_del_phy_power_chg_quirk;
408 usbdrd3_1: usb@fe900000 {
409 compatible = "rockchip,dwc3";
410 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
411 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
412 <&cru ACLK_USB3>, <&cru ACLK_USB3_NOC>,
413 <&cru ACLK_USB3_GRF>;
414 clock-names = "clk_usb3otg1_ref", "clk_usb3otg1_suspend",
415 "aclk_usb3otg1", "aclk_usb3_rksoc_axi_perf",
416 "aclk_usb3", "aclk_usb3_noc",
418 #address-cells = <2>;
422 usbdrd_dwc3_1: dwc3 {
423 compatible = "snps,dwc3";
424 reg = <0x0 0xfe900000 0x0 0x100000>;
425 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
428 snps,dis_enblslpm_quirk;
429 snps,phyif_utmi_16_bits;
430 snps,dis_u2_freeclk_exists_quirk;
431 snps,dis_del_phy_power_chg_quirk;
436 gic: interrupt-controller@fee00000 {
437 compatible = "arm,gic-v3";
438 #interrupt-cells = <3>;
439 #address-cells = <2>;
442 interrupt-controller;
444 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
445 <0x0 0xfef00000 0 0xc0000>, /* GICR */
446 <0x0 0xfff00000 0 0x10000>, /* GICC */
447 <0x0 0xfff10000 0 0x10000>, /* GICH */
448 <0x0 0xfff20000 0 0x10000>; /* GICV */
449 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
450 its: interrupt-controller@fee20000 {
451 compatible = "arm,gic-v3-its";
453 reg = <0x0 0xfee20000 0x0 0x20000>;
457 saradc: saradc@ff100000 {
458 compatible = "rockchip,rk3399-saradc";
459 reg = <0x0 0xff100000 0x0 0x100>;
460 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
461 #io-channel-cells = <1>;
462 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
463 clock-names = "saradc", "apb_pclk";
468 compatible = "rockchip,rk3399-i2c";
469 reg = <0x0 0xff3c0000 0x0 0x1000>;
470 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
471 clock-names = "i2c", "pclk";
472 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
473 pinctrl-names = "default";
474 pinctrl-0 = <&i2c0_xfer>;
475 #address-cells = <1>;
481 compatible = "rockchip,rk3399-i2c";
482 reg = <0x0 0xff110000 0x0 0x1000>;
483 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
484 clock-names = "i2c", "pclk";
485 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
486 pinctrl-names = "default";
487 pinctrl-0 = <&i2c1_xfer>;
488 #address-cells = <1>;
494 compatible = "rockchip,rk3399-i2c";
495 reg = <0x0 0xff120000 0x0 0x1000>;
496 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
497 clock-names = "i2c", "pclk";
498 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
499 pinctrl-names = "default";
500 pinctrl-0 = <&i2c2_xfer>;
501 #address-cells = <1>;
507 compatible = "rockchip,rk3399-i2c";
508 reg = <0x0 0xff130000 0x0 0x1000>;
509 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
510 clock-names = "i2c", "pclk";
511 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
512 pinctrl-names = "default";
513 pinctrl-0 = <&i2c3_xfer>;
514 #address-cells = <1>;
520 compatible = "rockchip,rk3399-i2c";
521 reg = <0x0 0xff140000 0x0 0x1000>;
522 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
523 clock-names = "i2c", "pclk";
524 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
525 pinctrl-names = "default";
526 pinctrl-0 = <&i2c5_xfer>;
527 #address-cells = <1>;
533 compatible = "rockchip,rk3399-i2c";
534 reg = <0x0 0xff150000 0x0 0x1000>;
535 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
536 clock-names = "i2c", "pclk";
537 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
538 pinctrl-names = "default";
539 pinctrl-0 = <&i2c6_xfer>;
540 #address-cells = <1>;
546 compatible = "rockchip,rk3399-i2c";
547 reg = <0x0 0xff160000 0x0 0x1000>;
548 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
549 clock-names = "i2c", "pclk";
550 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
551 pinctrl-names = "default";
552 pinctrl-0 = <&i2c7_xfer>;
553 #address-cells = <1>;
558 uart0: serial@ff180000 {
559 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
560 reg = <0x0 0xff180000 0x0 0x100>;
561 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
562 clock-names = "baudclk", "apb_pclk";
563 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
566 pinctrl-names = "default";
567 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
571 uart1: serial@ff190000 {
572 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
573 reg = <0x0 0xff190000 0x0 0x100>;
574 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
575 clock-names = "baudclk", "apb_pclk";
576 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
579 pinctrl-names = "default";
580 pinctrl-0 = <&uart1_xfer>;
584 uart2: serial@ff1a0000 {
585 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
586 reg = <0x0 0xff1a0000 0x0 0x100>;
587 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
588 clock-names = "baudclk", "apb_pclk";
589 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
592 pinctrl-names = "default";
593 pinctrl-0 = <&uart2c_xfer>;
597 uart3: serial@ff1b0000 {
598 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
599 reg = <0x0 0xff1b0000 0x0 0x100>;
600 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
601 clock-names = "baudclk", "apb_pclk";
602 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
605 pinctrl-names = "default";
606 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
611 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
612 reg = <0x0 0xff1c0000 0x0 0x1000>;
613 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
614 clock-names = "spiclk", "apb_pclk";
615 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
616 pinctrl-names = "default";
617 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
618 #address-cells = <1>;
624 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
625 reg = <0x0 0xff1d0000 0x0 0x1000>;
626 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
627 clock-names = "spiclk", "apb_pclk";
628 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
629 pinctrl-names = "default";
630 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
631 #address-cells = <1>;
637 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
638 reg = <0x0 0xff1e0000 0x0 0x1000>;
639 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
640 clock-names = "spiclk", "apb_pclk";
641 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
642 pinctrl-names = "default";
643 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
644 #address-cells = <1>;
650 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
651 reg = <0x0 0xff1f0000 0x0 0x1000>;
652 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
653 clock-names = "spiclk", "apb_pclk";
654 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
655 pinctrl-names = "default";
656 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
657 #address-cells = <1>;
663 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
664 reg = <0x0 0xff200000 0x0 0x1000>;
665 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
666 clock-names = "spiclk", "apb_pclk";
667 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
668 pinctrl-names = "default";
669 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
670 #address-cells = <1>;
676 #include "rk3368-thermal.dtsi"
679 tsadc: tsadc@ff260000 {
680 compatible = "rockchip,rk3399-tsadc";
681 reg = <0x0 0xff260000 0x0 0x100>;
682 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
683 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
684 clock-names = "tsadc", "apb_pclk";
685 resets = <&cru SRST_TSADC>;
686 reset-names = "tsadc-apb";
687 pinctrl-names = "init", "default", "sleep";
688 pinctrl-0 = <&otp_gpio>;
689 pinctrl-1 = <&otp_out>;
690 pinctrl-2 = <&otp_gpio>;
691 #thermal-sensor-cells = <1>;
692 rockchip,hw-tshut-temp = <95000>;
696 pmu: power-management@ff31000 {
697 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
698 reg = <0x0 0xff310000 0x0 0x1000>;
700 power: power-controller {
702 compatible = "rockchip,rk3399-power-controller";
703 #power-domain-cells = <1>;
704 #address-cells = <1>;
708 reg = <RK3399_PD_CENTER>;
709 #address-cells = <1>;
713 reg = <RK3399_PD_VDU>;
716 reg = <RK3399_PD_VCODEC>;
719 reg = <RK3399_PD_IEP>;
722 reg = <RK3399_PD_RGA>;
726 reg = <RK3399_PD_VIO>;
727 #address-cells = <1>;
731 reg = <RK3399_PD_ISP0>;
734 reg = <RK3399_PD_ISP1>;
737 reg = <RK3399_PD_HDCP>;
740 reg = <RK3399_PD_VO>;
741 #address-cells = <1>;
745 reg = <RK3399_PD_VOPB>;
748 reg = <RK3399_PD_VOPL>;
753 reg = <RK3399_PD_GPU>;
758 pmugrf: syscon@ff320000 {
759 compatible = "rockchip,rk3399-pmugrf", "syscon";
760 reg = <0x0 0xff320000 0x0 0x1000>;
764 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
765 reg = <0x0 0xff350000 0x0 0x1000>;
766 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
767 clock-names = "spiclk", "apb_pclk";
768 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
769 pinctrl-names = "default";
770 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
771 #address-cells = <1>;
776 uart4: serial@ff370000 {
777 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
778 reg = <0x0 0xff370000 0x0 0x100>;
779 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
780 clock-names = "baudclk", "apb_pclk";
781 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
784 pinctrl-names = "default";
785 pinctrl-0 = <&uart4_xfer>;
790 compatible = "rockchip,rk3399-i2c";
791 reg = <0x0 0xff3d0000 0x0 0x1000>;
792 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
793 clock-names = "i2c", "pclk";
794 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
795 pinctrl-names = "default";
796 pinctrl-0 = <&i2c4_xfer>;
797 #address-cells = <1>;
803 compatible = "rockchip,rk3399-i2c";
804 reg = <0x0 0xff3e0000 0x0 0x1000>;
805 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
806 clock-names = "i2c", "pclk";
807 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
808 pinctrl-names = "default";
809 pinctrl-0 = <&i2c8_xfer>;
810 #address-cells = <1>;
816 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
817 reg = <0x0 0xff420000 0x0 0x10>;
819 pinctrl-names = "default";
820 pinctrl-0 = <&pwm0_pin>;
821 clocks = <&pmucru PCLK_RKPWM_PMU>;
827 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
828 reg = <0x0 0xff420010 0x0 0x10>;
830 pinctrl-names = "default";
831 pinctrl-0 = <&pwm1_pin>;
832 clocks = <&pmucru PCLK_RKPWM_PMU>;
838 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
839 reg = <0x0 0xff420020 0x0 0x10>;
841 pinctrl-names = "default";
842 pinctrl-0 = <&pwm2_pin>;
843 clocks = <&pmucru PCLK_RKPWM_PMU>;
849 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
850 reg = <0x0 0xff420030 0x0 0x10>;
852 pinctrl-names = "default";
853 pinctrl-0 = <&pwm3a_pin>;
854 clocks = <&pmucru PCLK_RKPWM_PMU>;
859 pmucru: pmu-clock-controller@ff750000 {
860 compatible = "rockchip,rk3399-pmucru";
861 reg = <0x0 0xff750000 0x0 0x1000>;
862 rockchip,grf = <&pmugrf>;
865 assigned-clocks = <&pmucru PLL_PPLL>;
866 assigned-clock-rates = <676000000>;
869 cru: clock-controller@ff760000 {
870 compatible = "rockchip,rk3399-cru";
871 reg = <0x0 0xff760000 0x0 0x1000>;
872 rockchip,grf = <&grf>;
876 <&cru ARMCLKL>, <&cru ARMCLKB>,
877 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
879 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
881 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
883 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
884 assigned-clock-rates =
885 <816000000>, <1008000000>,
886 <594000000>, <800000000>,
888 <150000000>, <75000000>,
890 <100000000>, <100000000>,
892 <100000000>, <50000000>;
895 grf: syscon@ff770000 {
896 compatible = "rockchip,rk3399-grf", "syscon";
897 reg = <0x0 0xff770000 0x0 0x10000>;
900 wdt0: watchdog@ff840000 {
901 compatible = "snps,dw-wdt";
902 reg = <0x0 0xff840000 0x0 0x100>;
903 clocks = <&cru PCLK_WDT>;
904 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
908 spdif: spdif@ff870000 {
909 compatible = "rockchip,rk3399-spdif";
910 reg = <0x0 0xff870000 0x0 0x1000>;
911 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
912 dmas = <&dmac_bus 7>;
914 clock-names = "hclk", "mclk";
915 clocks = <&cru HCLK_SPDIF>, <&cru SCLK_SPDIF_8CH>;
916 pinctrl-names = "default";
917 pinctrl-0 = <&spdif_bus>;
922 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
923 reg = <0x0 0xff880000 0x0 0x1000>;
924 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
925 #address-cells = <1>;
927 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
928 dma-names = "tx", "rx";
929 clock-names = "i2s_hclk", "i2s_clk";
930 clocks = <&cru HCLK_I2S0_8CH>, <&cru SCLK_I2S0_8CH>;
931 pinctrl-names = "default";
932 pinctrl-0 = <&i2s0_8ch_bus>;
937 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
938 reg = <0x0 0xff890000 0x0 0x1000>;
939 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
940 #address-cells = <1>;
942 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
943 dma-names = "tx", "rx";
944 clock-names = "i2s_hclk", "i2s_clk";
945 clocks = <&cru HCLK_I2S1_8CH>, <&cru SCLK_I2S1_8CH>;
946 pinctrl-names = "default";
947 pinctrl-0 = <&i2s1_2ch_bus>;
952 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
953 reg = <0x0 0xff8a0000 0x0 0x1000>;
954 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
955 #address-cells = <1>;
957 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
958 dma-names = "tx", "rx";
959 clock-names = "i2s_hclk", "i2s_clk";
960 clocks = <&cru HCLK_I2S2_8CH>, <&cru SCLK_I2S2_8CH>;
965 compatible = "rockchip,rk3399-pinctrl";
966 rockchip,grf = <&grf>;
967 rockchip,pmu = <&pmugrf>;
968 #address-cells = <0x2>;
972 gpio0: gpio0@ff720000 {
973 compatible = "rockchip,gpio-bank";
974 reg = <0x0 0xff720000 0x0 0x100>;
975 clocks = <&pmucru PCLK_GPIO0_PMU>;
976 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
981 interrupt-controller;
982 #interrupt-cells = <0x2>;
985 gpio1: gpio1@ff730000 {
986 compatible = "rockchip,gpio-bank";
987 reg = <0x0 0xff730000 0x0 0x100>;
988 clocks = <&pmucru PCLK_GPIO1_PMU>;
989 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
994 interrupt-controller;
995 #interrupt-cells = <0x2>;
998 gpio2: gpio2@ff780000 {
999 compatible = "rockchip,gpio-bank";
1000 reg = <0x0 0xff780000 0x0 0x100>;
1001 clocks = <&cru PCLK_GPIO2>;
1002 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1005 #gpio-cells = <0x2>;
1007 interrupt-controller;
1008 #interrupt-cells = <0x2>;
1011 gpio3: gpio3@ff788000 {
1012 compatible = "rockchip,gpio-bank";
1013 reg = <0x0 0xff788000 0x0 0x100>;
1014 clocks = <&cru PCLK_GPIO3>;
1015 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1018 #gpio-cells = <0x2>;
1020 interrupt-controller;
1021 #interrupt-cells = <0x2>;
1024 gpio4: gpio4@ff790000 {
1025 compatible = "rockchip,gpio-bank";
1026 reg = <0x0 0xff790000 0x0 0x100>;
1027 clocks = <&cru PCLK_GPIO4>;
1028 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1031 #gpio-cells = <0x2>;
1033 interrupt-controller;
1034 #interrupt-cells = <0x2>;
1037 pcfg_pull_up: pcfg-pull-up {
1041 pcfg_pull_down: pcfg-pull-down {
1045 pcfg_pull_none: pcfg-pull-none {
1049 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1051 drive-strength = <12>;
1054 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1056 drive-strength = <8>;
1059 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1061 drive-strength = <4>;
1064 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1066 drive-strength = <2>;
1069 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
1071 drive-strength = <12>;
1075 emmc_pwr: emmc-pwr {
1077 <0 5 RK_FUNC_1 &pcfg_pull_up>;
1082 rgmii_pins: rgmii-pins {
1085 <3 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
1087 <3 14 RK_FUNC_1 &pcfg_pull_none>,
1089 <3 13 RK_FUNC_1 &pcfg_pull_none>,
1091 <3 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1093 <3 11 RK_FUNC_1 &pcfg_pull_none>,
1095 <3 9 RK_FUNC_1 &pcfg_pull_none>,
1097 <3 8 RK_FUNC_1 &pcfg_pull_none>,
1099 <3 7 RK_FUNC_1 &pcfg_pull_none>,
1101 <3 6 RK_FUNC_1 &pcfg_pull_none>,
1103 <3 5 RK_FUNC_1 &pcfg_pull_none_12ma>,
1105 <3 4 RK_FUNC_1 &pcfg_pull_none_12ma>,
1107 <3 3 RK_FUNC_1 &pcfg_pull_none>,
1109 <3 2 RK_FUNC_1 &pcfg_pull_none>,
1111 <3 1 RK_FUNC_1 &pcfg_pull_none_12ma>,
1113 <3 0 RK_FUNC_1 &pcfg_pull_none_12ma>;
1116 rmii_pins: rmii-pins {
1119 <3 13 RK_FUNC_1 &pcfg_pull_none>,
1121 <3 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1123 <3 11 RK_FUNC_1 &pcfg_pull_none>,
1125 <3 10 RK_FUNC_1 &pcfg_pull_none>,
1127 <3 9 RK_FUNC_1 &pcfg_pull_none>,
1129 <3 8 RK_FUNC_1 &pcfg_pull_none>,
1131 <3 7 RK_FUNC_1 &pcfg_pull_none>,
1133 <3 6 RK_FUNC_1 &pcfg_pull_none>,
1135 <3 5 RK_FUNC_1 &pcfg_pull_none_12ma>,
1137 <3 4 RK_FUNC_1 &pcfg_pull_none_12ma>;
1142 i2c0_xfer: i2c0-xfer {
1144 <1 15 RK_FUNC_2 &pcfg_pull_none>,
1145 <1 16 RK_FUNC_2 &pcfg_pull_none>;
1150 i2c1_xfer: i2c1-xfer {
1152 <4 2 RK_FUNC_1 &pcfg_pull_none>,
1153 <4 1 RK_FUNC_1 &pcfg_pull_none>;
1158 i2c2_xfer: i2c2-xfer {
1160 <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1161 <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
1166 i2c3_xfer: i2c3-xfer {
1168 <4 17 RK_FUNC_1 &pcfg_pull_none>,
1169 <4 16 RK_FUNC_1 &pcfg_pull_none>;
1174 i2c4_xfer: i2c4-xfer {
1176 <1 12 RK_FUNC_1 &pcfg_pull_none>,
1177 <1 11 RK_FUNC_1 &pcfg_pull_none>;
1182 i2c5_xfer: i2c5-xfer {
1184 <3 11 RK_FUNC_2 &pcfg_pull_none>,
1185 <3 10 RK_FUNC_2 &pcfg_pull_none>;
1190 i2c6_xfer: i2c6-xfer {
1192 <2 10 RK_FUNC_2 &pcfg_pull_none>,
1193 <2 9 RK_FUNC_2 &pcfg_pull_none>;
1198 i2c7_xfer: i2c7-xfer {
1200 <2 8 RK_FUNC_2 &pcfg_pull_none>,
1201 <2 7 RK_FUNC_2 &pcfg_pull_none>;
1206 i2c8_xfer: i2c8-xfer {
1208 <1 21 RK_FUNC_1 &pcfg_pull_none>,
1209 <1 20 RK_FUNC_1 &pcfg_pull_none>;
1214 i2s0_8ch_bus: i2s0-8ch-bus {
1216 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1217 <3 25 RK_FUNC_1 &pcfg_pull_none>,
1218 <3 26 RK_FUNC_1 &pcfg_pull_none>,
1219 <3 27 RK_FUNC_1 &pcfg_pull_none>,
1220 <3 28 RK_FUNC_1 &pcfg_pull_none>,
1221 <3 29 RK_FUNC_1 &pcfg_pull_none>,
1222 <3 30 RK_FUNC_1 &pcfg_pull_none>,
1223 <3 31 RK_FUNC_1 &pcfg_pull_none>,
1224 <4 0 RK_FUNC_1 &pcfg_pull_none>;
1229 i2s1_2ch_bus: i2s1-2ch-bus {
1231 <4 3 RK_FUNC_1 &pcfg_pull_none>,
1232 <4 4 RK_FUNC_1 &pcfg_pull_none>,
1233 <4 5 RK_FUNC_1 &pcfg_pull_none>,
1234 <4 6 RK_FUNC_1 &pcfg_pull_none>,
1235 <4 7 RK_FUNC_1 &pcfg_pull_none>;
1240 sdio0_bus1: sdio0-bus1 {
1242 <2 20 RK_FUNC_1 &pcfg_pull_up>;
1245 sdio0_bus4: sdio0-bus4 {
1247 <2 20 RK_FUNC_1 &pcfg_pull_up>,
1248 <2 21 RK_FUNC_1 &pcfg_pull_up>,
1249 <2 22 RK_FUNC_1 &pcfg_pull_up>,
1250 <2 23 RK_FUNC_1 &pcfg_pull_up>;
1253 sdio0_cmd: sdio0-cmd {
1255 <2 24 RK_FUNC_1 &pcfg_pull_up>;
1258 sdio0_clk: sdio0-clk {
1260 <2 25 RK_FUNC_1 &pcfg_pull_none>;
1263 sdio0_cd: sdio0-cd {
1265 <2 26 RK_FUNC_1 &pcfg_pull_up>;
1268 sdio0_pwr: sdio0-pwr {
1270 <2 27 RK_FUNC_1 &pcfg_pull_up>;
1273 sdio0_bkpwr: sdio0-bkpwr {
1275 <2 28 RK_FUNC_1 &pcfg_pull_up>;
1278 sdio0_wp: sdio0-wp {
1280 <0 3 RK_FUNC_1 &pcfg_pull_up>;
1283 sdio0_int: sdio0-int {
1285 <0 4 RK_FUNC_1 &pcfg_pull_up>;
1290 sdmmc_bus1: sdmmc-bus1 {
1292 <4 8 RK_FUNC_1 &pcfg_pull_up>;
1295 sdmmc_bus4: sdmmc-bus4 {
1297 <4 8 RK_FUNC_1 &pcfg_pull_up>,
1298 <4 9 RK_FUNC_1 &pcfg_pull_up>,
1299 <4 10 RK_FUNC_1 &pcfg_pull_up>,
1300 <4 11 RK_FUNC_1 &pcfg_pull_up>;
1303 sdmmc_clk: sdmmc-clk {
1305 <4 12 RK_FUNC_1 &pcfg_pull_none>;
1308 sdmmc_cmd: sdmmc-cmd {
1310 <4 13 RK_FUNC_1 &pcfg_pull_up>;
1313 sdmmc_cd: sdmcc-cd {
1315 <0 7 RK_FUNC_1 &pcfg_pull_up>;
1318 sdmmc_wp: sdmmc-wp {
1320 <0 8 RK_FUNC_1 &pcfg_pull_up>;
1325 spdif_bus: spdif-bus {
1327 <4 21 RK_FUNC_1 &pcfg_pull_none>;
1332 spi0_clk: spi0-clk {
1334 <3 6 RK_FUNC_2 &pcfg_pull_up>;
1336 spi0_cs0: spi0-cs0 {
1338 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1340 spi0_cs1: spi0-cs1 {
1342 <3 8 RK_FUNC_2 &pcfg_pull_up>;
1346 <3 5 RK_FUNC_2 &pcfg_pull_up>;
1350 <3 4 RK_FUNC_2 &pcfg_pull_up>;
1355 spi1_clk: spi1-clk {
1357 <1 9 RK_FUNC_2 &pcfg_pull_up>;
1359 spi1_cs0: spi1-cs0 {
1361 <1 10 RK_FUNC_2 &pcfg_pull_up>;
1365 <1 7 RK_FUNC_2 &pcfg_pull_up>;
1369 <1 8 RK_FUNC_2 &pcfg_pull_up>;
1374 spi2_clk: spi2-clk {
1376 <2 11 RK_FUNC_1 &pcfg_pull_up>;
1378 spi2_cs0: spi2-cs0 {
1380 <2 12 RK_FUNC_1 &pcfg_pull_up>;
1384 <2 9 RK_FUNC_1 &pcfg_pull_up>;
1388 <2 10 RK_FUNC_1 &pcfg_pull_up>;
1393 spi3_clk: spi3-clk {
1395 <1 17 RK_FUNC_1 &pcfg_pull_up>;
1397 spi3_cs0: spi3-cs0 {
1399 <1 18 RK_FUNC_1 &pcfg_pull_up>;
1403 <1 15 RK_FUNC_1 &pcfg_pull_up>;
1407 <1 16 RK_FUNC_1 &pcfg_pull_up>;
1412 spi4_clk: spi4-clk {
1414 <3 2 RK_FUNC_2 &pcfg_pull_up>;
1416 spi4_cs0: spi4-cs0 {
1418 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1422 <3 0 RK_FUNC_2 &pcfg_pull_up>;
1426 <3 1 RK_FUNC_2 &pcfg_pull_up>;
1431 spi5_clk: spi5-clk {
1433 <2 22 RK_FUNC_2 &pcfg_pull_up>;
1435 spi5_cs0: spi5-cs0 {
1437 <2 23 RK_FUNC_2 &pcfg_pull_up>;
1441 <2 20 RK_FUNC_2 &pcfg_pull_up>;
1445 <2 21 RK_FUNC_2 &pcfg_pull_up>;
1450 otp_gpio: otp-gpio {
1451 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
1455 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
1460 uart0_xfer: uart0-xfer {
1462 <2 16 RK_FUNC_1 &pcfg_pull_up>,
1463 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1466 uart0_cts: uart0-cts {
1468 <2 18 RK_FUNC_1 &pcfg_pull_none>;
1471 uart0_rts: uart0-rts {
1473 <2 19 RK_FUNC_1 &pcfg_pull_none>;
1478 uart1_xfer: uart1-xfer {
1480 <3 12 RK_FUNC_2 &pcfg_pull_up>,
1481 <3 13 RK_FUNC_2 &pcfg_pull_none>;
1486 uart2a_xfer: uart2a-xfer {
1488 <4 8 RK_FUNC_2 &pcfg_pull_up>,
1489 <4 9 RK_FUNC_2 &pcfg_pull_none>;
1494 uart2b_xfer: uart2b-xfer {
1496 <4 16 RK_FUNC_2 &pcfg_pull_up>,
1497 <4 17 RK_FUNC_2 &pcfg_pull_none>;
1502 uart2c_xfer: uart2c-xfer {
1504 <4 19 RK_FUNC_1 &pcfg_pull_up>,
1505 <4 20 RK_FUNC_1 &pcfg_pull_none>;
1510 uart3_xfer: uart3-xfer {
1512 <3 14 RK_FUNC_2 &pcfg_pull_up>,
1513 <3 15 RK_FUNC_2 &pcfg_pull_none>;
1516 uart3_cts: uart3-cts {
1518 <3 18 RK_FUNC_2 &pcfg_pull_none>;
1521 uart3_rts: uart3-rts {
1523 <3 19 RK_FUNC_2 &pcfg_pull_none>;
1528 uart4_xfer: uart4-xfer {
1530 <1 7 RK_FUNC_1 &pcfg_pull_up>,
1531 <1 8 RK_FUNC_1 &pcfg_pull_none>;
1536 uarthdcp_xfer: uarthdcp-xfer {
1538 <4 21 RK_FUNC_2 &pcfg_pull_up>,
1539 <4 22 RK_FUNC_2 &pcfg_pull_none>;
1544 pwm0_pin: pwm0-pin {
1546 <4 18 RK_FUNC_1 &pcfg_pull_none>;
1549 vop0_pwm_pin: vop0-pwm-pin {
1551 <4 18 RK_FUNC_2 &pcfg_pull_none>;
1556 pwm1_pin: pwm1-pin {
1558 <4 22 RK_FUNC_1 &pcfg_pull_none>;
1561 vop1_pwm_pin: vop1-pwm-pin {
1563 <4 18 RK_FUNC_3 &pcfg_pull_none>;
1568 pwm2_pin: pwm2-pin {
1570 <1 19 RK_FUNC_1 &pcfg_pull_none>;
1575 pwm3a_pin: pwm3a-pin {
1577 <0 6 RK_FUNC_1 &pcfg_pull_none>;
1582 pwm3b_pin: pwm3b-pin {
1584 <1 14 RK_FUNC_1 &pcfg_pull_none>;
1589 pmic_int_l: pmic-int-l {
1591 <1 21 RK_FUNC_GPIO &pcfg_pull_up>;