arch/arm64/boot/dts/rockchip/rk3399.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3399-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/interrupt-controller/irq.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/power/rk3399-power.h>
  49 #include <dt-bindings/thermal/thermal.h>
  50
  51 / {
  52         compatible = "rockchip,rk3399";
  53
  54         interrupt-parent = <&gic>;
  55         #address-cells = <2>;
  56         #size-cells = <2>;
  57
  58         aliases {
  59                 i2c0 = &i2c0;
  60                 i2c1 = &i2c1;
  61                 i2c2 = &i2c2;
  62                 i2c3 = &i2c3;
  63                 i2c4 = &i2c4;
  64                 i2c5 = &i2c5;
  65                 i2c6 = &i2c6;
  66                 i2c7 = &i2c7;
  67                 i2c8 = &i2c8;
  68                 serial0 = &uart0;
  69                 serial1 = &uart1;
  70                 serial2 = &uart2;
  71                 serial3 = &uart3;
  72                 serial4 = &uart4;
  73         };
  74
  75         psci {
  76                 compatible = "arm,psci-1.0";
  77                 method = "smc";
  78         };
  79
  80         cpus {
  81                 #address-cells = <2>;
  82                 #size-cells = <0>;
  83
  84                 cpu-map {
  85                         cluster0 {
  86                                 core0 {
  87                                         cpu = <&cpu_l0>;
  88                                 };
  89                                 core1 {
  90                                         cpu = <&cpu_l1>;
  91                                 };
  92                                 core2 {
  93                                         cpu = <&cpu_l2>;
  94                                 };
  95                                 core3 {
  96                                         cpu = <&cpu_l3>;
  97                                 };
  98                         };
  99
 100                         cluster1 {
 101                                 core0 {
 102                                         cpu = <&cpu_b0>;
 103                                 };
 104                                 core1 {
 105                                         cpu = <&cpu_b1>;
 106                                 };
 107                         };
 108                 };
 109
 110                 cpu_l0: cpu@0 {
 111                         device_type = "cpu";
 112                         compatible = "arm,cortex-a53", "arm,armv8";
 113                         reg = <0x0 0x0>;
 114                         enable-method = "psci";
 115                         #cooling-cells = <2>; /* min followed by max */
 116                         clocks = <&cru ARMCLKL>;
 117                         cpu-idle-states = <&cpu_sleep>;
 118                         operating-points-v2 = <&cluster0_opp>;
 119                 };
 120
 121                 cpu_l1: cpu@1 {
 122                         device_type = "cpu";
 123                         compatible = "arm,cortex-a53", "arm,armv8";
 124                         reg = <0x0 0x1>;
 125                         enable-method = "psci";
 126                         clocks = <&cru ARMCLKL>;
 127                         cpu-idle-states = <&cpu_sleep>;
 128                         operating-points-v2 = <&cluster0_opp>;
 129                 };
 130
 131                 cpu_l2: cpu@2 {
 132                         device_type = "cpu";
 133                         compatible = "arm,cortex-a53", "arm,armv8";
 134                         reg = <0x0 0x2>;
 135                         enable-method = "psci";
 136                         clocks = <&cru ARMCLKL>;
 137                         cpu-idle-states = <&cpu_sleep>;
 138                         operating-points-v2 = <&cluster0_opp>;
 139                 };
 140
 141                 cpu_l3: cpu@3 {
 142                         device_type = "cpu";
 143                         compatible = "arm,cortex-a53", "arm,armv8";
 144                         reg = <0x0 0x3>;
 145                         enable-method = "psci";
 146                         clocks = <&cru ARMCLKL>;
 147                         cpu-idle-states = <&cpu_sleep>;
 148                         operating-points-v2 = <&cluster0_opp>;
 149                 };
 150
 151                 cpu_b0: cpu@100 {
 152                         device_type = "cpu";
 153                         compatible = "arm,cortex-a72", "arm,armv8";
 154                         reg = <0x0 0x100>;
 155                         enable-method = "psci";
 156                         #cooling-cells = <2>; /* min followed by max */
 157                         clocks = <&cru ARMCLKB>;
 158                         cpu-idle-states = <&cpu_sleep>;
 159                         operating-points-v2 = <&cluster1_opp>;
 160                 };
 161
 162                 cpu_b1: cpu@101 {
 163                         device_type = "cpu";
 164                         compatible = "arm,cortex-a72", "arm,armv8";
 165                         reg = <0x0 0x101>;
 166                         enable-method = "psci";
 167                         clocks = <&cru ARMCLKB>;
 168                         cpu-idle-states = <&cpu_sleep>;
 169                         operating-points-v2 = <&cluster1_opp>;
 170                 };
 171
 172                 idle-states {
 173                         entry-method = "psci";
 174                         cpu_sleep: cpu-sleep-0 {
 175                                 compatible = "arm,idle-state";
 176                                 local-timer-stop;
 177                                 arm,psci-suspend-param = <0x0010000>;
 178                                 entry-latency-us = <350>;
 179                                 exit-latency-us = <600>;
 180                                 min-residency-us = <1150>;
 181                         };
 182                 };
 183         };
 184
 185         cluster0_opp: opp_table0 {
 186                 compatible = "operating-points-v2";
 187                 opp-shared;
 188
 189                 opp00 {
 190                         opp-hz = /bits/ 64 <408000000>;
 191                         opp-microvolt = <800000>;
 192                         clock-latency-ns = <40000>;
 193                 };
 194                 opp01 {
 195                         opp-hz = /bits/ 64 <600000000>;
 196                         opp-microvolt = <800000>;
 197                 };
 198                 opp02 {
 199                         opp-hz = /bits/ 64 <816000000>;
 200                         opp-microvolt = <800000>;
 201                 };
 202                 opp03 {
 203                         opp-hz = /bits/ 64 <1008000000>;
 204                         opp-microvolt = <875000>;
 205                 };
 206                 opp04 {
 207                         opp-hz = /bits/ 64 <1200000000>;
 208                         opp-microvolt = <925000>;
 209                 };
 210                 opp05 {
 211                         opp-hz = /bits/ 64 <1416000000>;
 212                         opp-microvolt = <1025000>;
 213                 };
 214         };
 215
 216         cluster1_opp: opp_table1 {
 217                 compatible = "operating-points-v2";
 218                 opp-shared;
 219
 220                 opp00 {
 221                         opp-hz = /bits/ 64 <408000000>;
 222                         opp-microvolt = <800000>;
 223                         clock-latency-ns = <40000>;
 224                 };
 225                 opp01 {
 226                         opp-hz = /bits/ 64 <600000000>;
 227                         opp-microvolt = <800000>;
 228                 };
 229                 opp02 {
 230                         opp-hz = /bits/ 64 <816000000>;
 231                         opp-microvolt = <800000>;
 232                 };
 233                 opp03 {
 234                         opp-hz = /bits/ 64 <1008000000>;
 235                         opp-microvolt = <850000>;
 236                 };
 237                 opp04 {
 238                         opp-hz = /bits/ 64 <1200000000>;
 239                         opp-microvolt = <925000>;
 240                 };
 241         };
 242
 243         timer {
 244                 compatible = "arm,armv8-timer";
 245                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
 246                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
 247                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
 248                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
 249         };
 250
 251         arm-pmu {
 252                 compatible = "arm,armv8-pmuv3";
 253                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
 254         };
 255
 256         xin24m: xin24m {
 257                 compatible = "fixed-clock";
 258                 #clock-cells = <0>;
 259                 clock-frequency = <24000000>;
 260                 clock-output-names = "xin24m";
 261         };
 262
 263         amba {
 264                 compatible = "arm,amba-bus";
 265                 #address-cells = <2>;
 266                 #size-cells = <2>;
 267                 ranges;
 268
 269                 dmac_bus: dma-controller@ff6d0000 {
 270                         compatible = "arm,pl330", "arm,primecell";
 271                         reg = <0x0 0xff6d0000 0x0 0x4000>;
 272                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 273                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 274                         #dma-cells = <1>;
 275                         clocks = <&cru ACLK_DMAC0_PERILP>;
 276                         clock-names = "apb_pclk";
 277                 };
 278
 279                 dmac_peri: dma-controller@ff6e0000 {
 280                         compatible = "arm,pl330", "arm,primecell";
 281                         reg = <0x0 0xff6e0000 0x0 0x4000>;
 282                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 283                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 284                         #dma-cells = <1>;
 285                         clocks = <&cru ACLK_DMAC1_PERILP>;
 286                         clock-names = "apb_pclk";
 287                 };
 288         };
 289
 290         gmac: eth@fe300000 {
 291                 compatible = "rockchip,rk3399-gmac";
 292                 reg = <0x0 0xfe300000 0x0 0x10000>;
 293                 rockchip,grf = <&grf>;
 294                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 295                 interrupt-names = "macirq";
 296                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
 297                          <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
 298                          <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
 299                          <&cru PCLK_GMAC>;
 300                 clock-names = "stmmaceth", "mac_clk_rx",
 301                               "mac_clk_tx", "clk_mac_ref",
 302                               "clk_mac_refout", "aclk_mac",
 303                               "pclk_mac";
 304                 resets = <&cru SRST_A_GMAC>;
 305                 reset-names = "stmmaceth";
 306                 status = "disabled";
 307         };
 308
 309         emmc_phy: phy {
 310                 compatible = "rockchip,rk3399-emmc-phy";
 311                 reg-offset = <0xf780>;
 312                 #phy-cells = <0>;
 313                 rockchip,grf = <&grf>;
 314                 ctrl-base = <0xfe330000>;
 315                 status = "disabled";
 316         };
 317
 318         sdio0: dwmmc@fe310000 {
 319                 compatible = "rockchip,rk3399-dw-mshc",
 320                              "rockchip,rk3288-dw-mshc";
 321                 reg = <0x0 0xfe310000 0x0 0x4000>;
 322                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 323                 clock-freq-min-max = <400000 150000000>;
 324                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 325                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 326                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 327                 fifo-depth = <0x100>;
 328                 status = "disabled";
 329         };
 330
 331         sdmmc: dwmmc@fe320000 {
 332                 compatible = "rockchip,rk3399-dw-mshc",
 333                              "rockchip,rk3288-dw-mshc";
 334                 reg = <0x0 0xfe320000 0x0 0x4000>;
 335                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 336                 clock-freq-min-max = <400000 150000000>;
 337                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 338                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 339                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 340                 fifo-depth = <0x100>;
 341                 status = "disabled";
 342         };
 343
 344         sdhci: sdhci@fe330000 {
 345                 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
 346                 reg = <0x0 0xfe330000 0x0 0x10000>;
 347                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 348                 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
 349                 clock-names = "clk_xin", "clk_ahb";
 350                 assigned-clocks = <&cru SCLK_EMMC>;
 351                 assigned-clock-parents = <&cru PLL_CPLL>;
 352                 assigned-clock-rates = <200000000>;
 353                 phys = <&emmc_phy>;
 354                 phy-names = "phy_arasan";
 355                 status = "disabled";
 356         };
 357
 358         usb2phy: usb2phy {
 359                 compatible = "rockchip,rk3399-usb-phy";
 360                 rockchip,grf = <&grf>;
 361                 #address-cells = <1>;
 362                 #size-cells = <0>;
 363
 364                 usb2phy0: usb2-phy0 {
 365                         #phy-cells = <0>;
 366                         #clock-cells = <0>;
 367                         reg = <0xe458>;
 368                 };
 369
 370                 usb2phy1: usb2-phy1 {
 371                         #phy-cells = <0>;
 372                         #clock-cells = <0>;
 373                         reg = <0xe468>;
 374                 };
 375         };
 376
 377         usb_host0_ehci: usb@fe380000 {
 378                 compatible = "generic-ehci";
 379                 reg = <0x0 0xfe380000 0x0 0x20000>;
 380                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 381                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
 382                 clock-names = "hclk_host0", "hclk_host0_arb";
 383                 phys = <&usb2phy0>;
 384                 phy-names = "usb2_phy0";
 385                 status = "disabled";
 386         };
 387
 388         usb_host0_ohci: usb@fe3a0000 {
 389                 compatible = "generic-ohci";
 390                 reg = <0x0 0xfe3a0000 0x0 0x20000>;
 391                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 392                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
 393                 clock-names = "hclk_host0", "hclk_host0_arb";
 394                 status = "disabled";
 395         };
 396
 397         usb_host1_ehci: usb@fe3c0000 {
 398                 compatible = "generic-ehci";
 399                 reg = <0x0 0xfe3c0000 0x0 0x20000>;
 400                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 401                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
 402                 clock-names = "hclk_host1", "hclk_host1_arb";
 403                 phys = <&usb2phy1>;
 404                 phy-names = "usb2_phy1";
 405                 status = "disabled";
 406         };
 407
 408         usb_host1_ohci: usb@fe3e0000 {
 409                 compatible = "generic-ohci";
 410                 reg = <0x0 0xfe3e0000 0x0 0x20000>;
 411                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 412                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
 413                 clock-names = "hclk_host1", "hclk_host1_arb";
 414                 status = "disabled";
 415         };
 416
 417         usbdrd3_0: usb@fe800000 {
 418                 compatible = "rockchip,dwc3";
 419                 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
 420                          <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
 421                          <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
 422                 clock-names = "clk_usb3otg0_ref", "clk_usb3otg0_suspend",
 423                               "aclk_usb3otg0", "aclk_usb3_rksoc_axi_perf",
 424                               "aclk_usb3", "aclk_usb3_grf";
 425                 #address-cells = <2>;
 426                 #size-cells = <2>;
 427                 ranges;
 428                 status = "disabled";
 429                 usbdrd_dwc3_0: dwc3 {
 430                         compatible = "snps,dwc3";
 431                         reg = <0x0 0xfe800000 0x0 0x100000>;
 432                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 433                         dr_mode = "otg";
 434                         tx-fifo-resize;
 435                         snps,dis_enblslpm_quirk;
 436                         snps,phyif_utmi_16_bits;
 437                         snps,dis_u2_freeclk_exists_quirk;
 438                         snps,dis_del_phy_power_chg_quirk;
 439                         snps,xhci_slow_suspend_quirk;
 440                         status = "disabled";
 441                 };
 442         };
 443
 444         usbdrd3_1: usb@fe900000 {
 445                 compatible = "rockchip,dwc3";
 446                 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
 447                          <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
 448                          <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
 449                 clock-names = "clk_usb3otg1_ref", "clk_usb3otg1_suspend",
 450                               "aclk_usb3otg1", "aclk_usb3_rksoc_axi_perf",
 451                               "aclk_usb3", "aclk_usb3_grf";
 452                 #address-cells = <2>;
 453                 #size-cells = <2>;
 454                 ranges;
 455                 status = "disabled";
 456                 usbdrd_dwc3_1: dwc3 {
 457                         compatible = "snps,dwc3";
 458                         reg = <0x0 0xfe900000 0x0 0x100000>;
 459                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 460                         dr_mode = "otg";
 461                         tx-fifo-resize;
 462                         snps,dis_enblslpm_quirk;
 463                         snps,phyif_utmi_16_bits;
 464                         snps,dis_u2_freeclk_exists_quirk;
 465                         snps,dis_del_phy_power_chg_quirk;
 466                         snps,xhci_slow_suspend_quirk;
 467                         status = "disabled";
 468                 };
 469         };
 470
 471         gic: interrupt-controller@fee00000 {
 472                 compatible = "arm,gic-v3";
 473                 #interrupt-cells = <3>;
 474                 #address-cells = <2>;
 475                 #size-cells = <2>;
 476                 ranges;
 477                 interrupt-controller;
 478
 479                 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
 480                       <0x0 0xfef00000 0 0xc0000>, /* GICR */
 481                       <0x0 0xfff00000 0 0x10000>, /* GICC */
 482                       <0x0 0xfff10000 0 0x10000>, /* GICH */
 483                       <0x0 0xfff20000 0 0x10000>; /* GICV */
 484                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 485                 its: interrupt-controller@fee20000 {
 486                         compatible = "arm,gic-v3-its";
 487                         msi-controller;
 488                         reg = <0x0 0xfee20000 0x0 0x20000>;
 489                 };
 490         };
 491
 492         saradc: saradc@ff100000 {
 493                 compatible = "rockchip,rk3399-saradc";
 494                 reg = <0x0 0xff100000 0x0 0x100>;
 495                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 496                 #io-channel-cells = <1>;
 497                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 498                 clock-names = "saradc", "apb_pclk";
 499                 status = "disabled";
 500         };
 501
 502         i2c0: i2c@ff3c0000 {
 503                 compatible = "rockchip,rk3399-i2c";
 504                 reg = <0x0 0xff3c0000 0x0 0x1000>;
 505                 clocks =  <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
 506                 clock-names = "i2c", "pclk";
 507                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 508                 pinctrl-names = "default";
 509                 pinctrl-0 = <&i2c0_xfer>;
 510                 #address-cells = <1>;
 511                 #size-cells = <0>;
 512                 status = "disabled";
 513         };
 514
 515         i2c1: i2c@ff110000 {
 516                 compatible = "rockchip,rk3399-i2c";
 517                 reg = <0x0 0xff110000 0x0 0x1000>;
 518                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 519                 clock-names = "i2c", "pclk";
 520                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 521                 pinctrl-names = "default";
 522                 pinctrl-0 = <&i2c1_xfer>;
 523                 #address-cells = <1>;
 524                 #size-cells = <0>;
 525                 status = "disabled";
 526         };
 527
 528         i2c2: i2c@ff120000 {
 529                 compatible = "rockchip,rk3399-i2c";
 530                 reg = <0x0 0xff120000 0x0 0x1000>;
 531                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 532                 clock-names = "i2c", "pclk";
 533                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 534                 pinctrl-names = "default";
 535                 pinctrl-0 = <&i2c2_xfer>;
 536                 #address-cells = <1>;
 537                 #size-cells = <0>;
 538                 status = "disabled";
 539         };
 540
 541         i2c3: i2c@ff130000 {
 542                 compatible = "rockchip,rk3399-i2c";
 543                 reg = <0x0 0xff130000 0x0 0x1000>;
 544                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 545                 clock-names = "i2c", "pclk";
 546                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 547                 pinctrl-names = "default";
 548                 pinctrl-0 = <&i2c3_xfer>;
 549                 #address-cells = <1>;
 550                 #size-cells = <0>;
 551                 status = "disabled";
 552         };
 553
 554         i2c5: i2c@ff140000 {
 555                 compatible = "rockchip,rk3399-i2c";
 556                 reg = <0x0 0xff140000 0x0 0x1000>;
 557                 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
 558                 clock-names = "i2c", "pclk";
 559                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 560                 pinctrl-names = "default";
 561                 pinctrl-0 = <&i2c5_xfer>;
 562                 #address-cells = <1>;
 563                 #size-cells = <0>;
 564                 status = "disabled";
 565         };
 566
 567         i2c6: i2c@ff150000 {
 568                 compatible = "rockchip,rk3399-i2c";
 569                 reg = <0x0 0xff150000 0x0 0x1000>;
 570                 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
 571                 clock-names = "i2c", "pclk";
 572                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 573                 pinctrl-names = "default";
 574                 pinctrl-0 = <&i2c6_xfer>;
 575                 #address-cells = <1>;
 576                 #size-cells = <0>;
 577                 status = "disabled";
 578         };
 579
 580         i2c7: i2c@ff160000 {
 581                 compatible = "rockchip,rk3399-i2c";
 582                 reg = <0x0 0xff160000 0x0 0x1000>;
 583                 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
 584                 clock-names = "i2c", "pclk";
 585                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 586                 pinctrl-names = "default";
 587                 pinctrl-0 = <&i2c7_xfer>;
 588                 #address-cells = <1>;
 589                 #size-cells = <0>;
 590                 status = "disabled";
 591         };
 592
 593         uart0: serial@ff180000 {
 594                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 595                 reg = <0x0 0xff180000 0x0 0x100>;
 596                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 597                 clock-names = "baudclk", "apb_pclk";
 598                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 599                 reg-shift = <2>;
 600                 reg-io-width = <4>;
 601                 pinctrl-names = "default";
 602                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 603                 status = "disabled";
 604         };
 605
 606         uart1: serial@ff190000 {
 607                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 608                 reg = <0x0 0xff190000 0x0 0x100>;
 609                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 610                 clock-names = "baudclk", "apb_pclk";
 611                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 612                 reg-shift = <2>;
 613                 reg-io-width = <4>;
 614                 pinctrl-names = "default";
 615                 pinctrl-0 = <&uart1_xfer>;
 616                 status = "disabled";
 617         };
 618
 619         uart2: serial@ff1a0000 {
 620                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 621                 reg = <0x0 0xff1a0000 0x0 0x100>;
 622                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 623                 clock-names = "baudclk", "apb_pclk";
 624                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 625                 reg-shift = <2>;
 626                 reg-io-width = <4>;
 627                 pinctrl-names = "default";
 628                 pinctrl-0 = <&uart2c_xfer>;
 629                 status = "disabled";
 630         };
 631
 632         uart3: serial@ff1b0000 {
 633                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 634                 reg = <0x0 0xff1b0000 0x0 0x100>;
 635                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 636                 clock-names = "baudclk", "apb_pclk";
 637                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 638                 reg-shift = <2>;
 639                 reg-io-width = <4>;
 640                 pinctrl-names = "default";
 641                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 642                 status = "disabled";
 643         };
 644
 645         spi0: spi@ff1c0000 {
 646                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 647                 reg = <0x0 0xff1c0000 0x0 0x1000>;
 648                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 649                 clock-names = "spiclk", "apb_pclk";
 650                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 651                 pinctrl-names = "default";
 652                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 653                 #address-cells = <1>;
 654                 #size-cells = <0>;
 655                 status = "disabled";
 656         };
 657
 658         spi1: spi@ff1d0000 {
 659                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 660                 reg = <0x0 0xff1d0000 0x0 0x1000>;
 661                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 662                 clock-names = "spiclk", "apb_pclk";
 663                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 664                 pinctrl-names = "default";
 665                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 666                 #address-cells = <1>;
 667                 #size-cells = <0>;
 668                 status = "disabled";
 669         };
 670
 671         spi2: spi@ff1e0000 {
 672                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 673                 reg = <0x0 0xff1e0000 0x0 0x1000>;
 674                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 675                 clock-names = "spiclk", "apb_pclk";
 676                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 677                 pinctrl-names = "default";
 678                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 679                 #address-cells = <1>;
 680                 #size-cells = <0>;
 681                 status = "disabled";
 682         };
 683
 684         spi4: spi@ff1f0000 {
 685                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 686                 reg = <0x0 0xff1f0000 0x0 0x1000>;
 687                 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
 688                 clock-names = "spiclk", "apb_pclk";
 689                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 690                 pinctrl-names = "default";
 691                 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
 692                 #address-cells = <1>;
 693                 #size-cells = <0>;
 694                 status = "disabled";
 695         };
 696
 697         spi5: spi@ff200000 {
 698                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 699                 reg = <0x0 0xff200000 0x0 0x1000>;
 700                 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
 701                 clock-names = "spiclk", "apb_pclk";
 702                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
 703                 pinctrl-names = "default";
 704                 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
 705                 #address-cells = <1>;
 706                 #size-cells = <0>;
 707                 status = "disabled";
 708         };
 709
 710         thermal-zones {
 711                 cpu {
 712                         polling-delay-passive = <100>; /* milliseconds */
 713                         polling-delay = <1000>; /* milliseconds */
 714
 715                         thermal-sensors = <&tsadc 0>;
 716
 717                         trips {
 718                                 cpu_alert0: cpu_alert0 {
 719                                         temperature = <70000>; /* millicelsius */
 720                                         hysteresis = <2000>; /* millicelsius */
 721                                         type = "passive";
 722                                 };
 723                                 cpu_alert1: cpu_alert1 {
 724                                         temperature = <75000>; /* millicelsius */
 725                                         hysteresis = <2000>; /* millicelsius */
 726                                         type = "passive";
 727                                 };
 728                                 cpu_crit: cpu_crit {
 729                                         temperature = <95000>; /* millicelsius */
 730                                         hysteresis = <2000>; /* millicelsius */
 731                                         type = "critical";
 732                                 };
 733                         };
 734
 735                         cooling-maps {
 736                                 map0 {
 737                                         trip = <&cpu_alert0>;
 738                                         cooling-device =
 739                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 740                                 };
 741                                 map1 {
 742                                         trip = <&cpu_alert1>;
 743                                         cooling-device =
 744                                                 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 745                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 746                                 };
 747                         };
 748                 };
 749
 750                 gpu {
 751                         polling-delay-passive = <100>; /* milliseconds */
 752                         polling-delay = <1000>; /* milliseconds */
 753
 754                         thermal-sensors = <&tsadc 1>;
 755
 756                         trips {
 757                                 gpu_alert0: gpu_alert0 {
 758                                         temperature = <75000>; /* millicelsius */
 759                                         hysteresis = <2000>; /* millicelsius */
 760                                         type = "passive";
 761                                 };
 762                                 gpu_crit: gpu_crit {
 763                                         temperature = <95000>; /* millicelsius */
 764                                         hysteresis = <2000>; /* millicelsius */
 765                                         type = "critical";
 766                                 };
 767                         };
 768
 769                         cooling-maps {
 770                                 map0 {
 771                                         trip = <&gpu_alert0>;
 772                                         cooling-device =
 773                                                 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 774                                 };
 775                         };
 776                 };
 777         };
 778
 779         tsadc: tsadc@ff260000 {
 780                 compatible = "rockchip,rk3399-tsadc";
 781                 reg = <0x0 0xff260000 0x0 0x100>;
 782                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 783                 rockchip,grf = <&grf>;
 784                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 785                 clock-names = "tsadc", "apb_pclk";
 786                 assigned-clocks = <&cru SCLK_TSADC>;
 787                 assigned-clock-rates = <750000>;
 788                 resets = <&cru SRST_TSADC>;
 789                 reset-names = "tsadc-apb";
 790                 pinctrl-names = "init", "default", "sleep";
 791                 pinctrl-0 = <&otp_gpio>;
 792                 pinctrl-1 = <&otp_out>;
 793                 pinctrl-2 = <&otp_gpio>;
 794                 #thermal-sensor-cells = <1>;
 795                 rockchip,hw-tshut-temp = <95000>;
 796                 status = "disabled";
 797         };
 798
 799         qos_gpu: qos_gpu@0xffae0000 {
 800                 compatible ="syscon";
 801                 reg = <0x0 0xffae0000 0x0 0x20>;
 802         };
 803         qos_video_m0: qos_video_m0@0xffab8000 {
 804                 compatible ="syscon";
 805                 reg = <0x0 0xffab8000 0x0 0x20>;
 806         };
 807         qos_video_m1_r: qos_video_m1_r@0xffac0000 {
 808                 compatible ="syscon";
 809                 reg = <0x0 0xffac0000 0x0 0x20>;
 810         };
 811         qos_video_m1_w: qos_video_m1_w@0xffac0080 {
 812                 compatible ="syscon";
 813                 reg = <0x0 0xffac0080 0x0 0x20>;
 814         };
 815         qos_rga_r: qos_rga_r@0xffab0000 {
 816                 compatible ="syscon";
 817                 reg = <0x0 0xffab0000 0x0 0x20>;
 818         };
 819         qos_rga_w: qos_rga_w@0xffab0080 {
 820                 compatible ="syscon";
 821                 reg = <0x0 0xffab0000 0x0 0x20>;
 822         };
 823         qos_iep: qos_iep@0xffa98000 {
 824                 compatible ="syscon";
 825                 reg = <0x0 0xffa98000 0x0 0x20>;
 826         };
 827         qos_vop_big_r: qos_vop_big_r@0xffac8000 {
 828                 compatible ="syscon";
 829                 reg = <0x0 0xffac8000 0x0 0x20>;
 830         };
 831         qos_vop_big_w: qos_vop_big_w@0xffac8080 {
 832                 compatible ="syscon";
 833                 reg = <0x0 0xffac8080 0x0 0x20>;
 834         };
 835         qos_vop_little: qos_vop_little@0xffad0000 {
 836                 compatible ="syscon";
 837                 reg = <0x0 0xffad0000 0x0 0x20>;
 838         };
 839         qos_isp0_m0: qos_isp0_m0@0xffaa0000 {
 840                 compatible ="syscon";
 841                 reg = <0x0 0xffaa0000 0x0 0x20>;
 842         };
 843         qos_isp0_m1: qos_isp0_m1@0xffaa0080 {
 844                 compatible ="syscon";
 845                 reg = <0x0 0xffaa0080 0x0 0x20>;
 846         };
 847         qos_isp1_m0: qos_isp1_m0@0xffaa8000 {
 848                 compatible ="syscon";
 849                 reg = <0x0 0xffaa8000 0x0 0x20>;
 850         };
 851         qos_isp1_m1: qos_isp1_m1@0xffaa8080 {
 852                 compatible ="syscon";
 853                 reg = <0x0 0xffaa8080 0x0 0x20>;
 854         };
 855         qos_hdcp: qos_hdcp@0xffa90000 {
 856                 compatible ="syscon";
 857                 reg = <0x0 0xffa90000 0x0 0x20>;
 858         };
 859
 860         pmu: power-management@ff310000 {
 861                 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
 862                 reg = <0x0 0xff310000 0x0 0x1000>;
 863
 864                 power: power-controller {
 865                         status = "disabled";
 866                         compatible = "rockchip,rk3399-power-controller";
 867                         #power-domain-cells = <1>;
 868                         #address-cells = <1>;
 869                         #size-cells = <0>;
 870
 871                         pd_center {
 872                                 reg = <RK3399_PD_CENTER>;
 873                                 #address-cells = <1>;
 874                                 #size-cells = <0>;
 875
 876                                 pd_vdu {
 877                                         reg = <RK3399_PD_VDU>;
 878                                         pm_qos = <&qos_video_m1_r>,
 879                                                  <&qos_video_m1_w>;
 880                                 };
 881                                 pd_vcodec {
 882                                         reg = <RK3399_PD_VCODEC>;
 883                                         pm_qos = <&qos_video_m0>;
 884                                 };
 885                                 pd_iep {
 886                                         reg = <RK3399_PD_IEP>;
 887                                         pm_qos = <&qos_iep>;
 888                                 };
 889                                 pd_rga {
 890                                         reg = <RK3399_PD_RGA>;
 891                                         pm_qos = <&qos_rga_r>,
 892                                                  <&qos_rga_w>;
 893                                 };
 894                         };
 895                         pd_vio {
 896                                 reg = <RK3399_PD_VIO>;
 897                                 #address-cells = <1>;
 898                                 #size-cells = <0>;
 899
 900                                 pd_isp0 {
 901                                         reg = <RK3399_PD_ISP0>;
 902                                         pm_qos = <&qos_isp0_m0>,
 903                                                  <&qos_isp0_m1>;
 904                                 };
 905                                 pd_isp1 {
 906                                         reg = <RK3399_PD_ISP1>;
 907                                         pm_qos = <&qos_isp1_m0>,
 908                                                  <&qos_isp1_m1>;
 909                                 };
 910                                 pd_hdcp {
 911                                         reg = <RK3399_PD_HDCP>;
 912                                         pm_qos = <&qos_hdcp>;
 913                                 };
 914                                 pd_vo {
 915                                         reg = <RK3399_PD_VO>;
 916                                         #address-cells = <1>;
 917                                         #size-cells = <0>;
 918
 919                                         pd_vopb {
 920                                                 reg = <RK3399_PD_VOPB>;
 921                                                 pm_qos = <&qos_vop_big_r>,
 922                                                          <&qos_vop_big_w>;
 923                                         };
 924                                         pd_vopl {
 925                                                 reg = <RK3399_PD_VOPL>;
 926                                                 pm_qos = <&qos_vop_little>;
 927                                         };
 928                                 };
 929                         };
 930                         pd_gpu {
 931                                 reg = <RK3399_PD_GPU>;
 932                                 pm_qos = <&qos_gpu>;
 933                         };
 934                 };
 935         };
 936
 937         pmugrf: syscon@ff320000 {
 938                 compatible = "rockchip,rk3399-pmugrf", "syscon";
 939                 reg = <0x0 0xff320000 0x0 0x1000>;
 940         };
 941
 942         spi3: spi@ff350000 {
 943                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 944                 reg = <0x0 0xff350000 0x0 0x1000>;
 945                 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
 946                 clock-names = "spiclk", "apb_pclk";
 947                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 948                 pinctrl-names = "default";
 949                 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
 950                 #address-cells = <1>;
 951                 #size-cells = <0>;
 952                 status = "disabled";
 953         };
 954
 955         uart4: serial@ff370000 {
 956                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 957                 reg = <0x0 0xff370000 0x0 0x100>;
 958                 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
 959                 clock-names = "baudclk", "apb_pclk";
 960                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 961                 reg-shift = <2>;
 962                 reg-io-width = <4>;
 963                 pinctrl-names = "default";
 964                 pinctrl-0 = <&uart4_xfer>;
 965                 status = "disabled";
 966         };
 967
 968         i2c4: i2c@ff3d0000 {
 969                 compatible = "rockchip,rk3399-i2c";
 970                 reg = <0x0 0xff3d0000 0x0 0x1000>;
 971                 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
 972                 clock-names = "i2c", "pclk";
 973                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 974                 pinctrl-names = "default";
 975                 pinctrl-0 = <&i2c4_xfer>;
 976                 #address-cells = <1>;
 977                 #size-cells = <0>;
 978                 status = "disabled";
 979         };
 980
 981         i2c8: i2c@ff3e0000 {
 982                 compatible = "rockchip,rk3399-i2c";
 983                 reg = <0x0 0xff3e0000 0x0 0x1000>;
 984                 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
 985                 clock-names = "i2c", "pclk";
 986                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 987                 pinctrl-names = "default";
 988                 pinctrl-0 = <&i2c8_xfer>;
 989                 #address-cells = <1>;
 990                 #size-cells = <0>;
 991                 status = "disabled";
 992         };
 993
 994         pwm0: pwm@ff420000 {
 995                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 996                 reg = <0x0 0xff420000 0x0 0x10>;
 997                 #pwm-cells = <3>;
 998                 pinctrl-names = "default";
 999                 pinctrl-0 = <&pwm0_pin>;
1000                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1001                 clock-names = "pwm";
1002                 status = "disabled";
1003         };
1004
1005         pwm1: pwm@ff420010 {
1006                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1007                 reg = <0x0 0xff420010 0x0 0x10>;
1008                 #pwm-cells = <3>;
1009                 pinctrl-names = "default";
1010                 pinctrl-0 = <&pwm1_pin>;
1011                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1012                 clock-names = "pwm";
1013                 status = "disabled";
1014         };
1015
1016         pwm2: pwm@ff420020 {
1017                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1018                 reg = <0x0 0xff420020 0x0 0x10>;
1019                 #pwm-cells = <3>;
1020                 pinctrl-names = "default";
1021                 pinctrl-0 = <&pwm2_pin>;
1022                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1023                 clock-names = "pwm";
1024                 status = "disabled";
1025         };
1026
1027         pwm3: pwm@ff420030 {
1028                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1029                 reg = <0x0 0xff420030 0x0 0x10>;
1030                 #pwm-cells = <3>;
1031                 pinctrl-names = "default";
1032                 pinctrl-0 = <&pwm3a_pin>;
1033                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1034                 clock-names = "pwm";
1035                 status = "disabled";
1036         };
1037
1038         rga: rga@ff680000 {
1039                 compatible = "rockchip,rk3399-rga";
1040                 reg = <0x0 0xff680000 0x0 0x10000>;
1041                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
1042                 interrupt-names = "rga";
1043                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
1044                 clock-names = "aclk", "hclk", "sclk";
1045                 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
1046                 reset-names = "core", "axi", "ahb";
1047                 status = "disabled";
1048         };
1049
1050         pmucru: pmu-clock-controller@ff750000 {
1051                 compatible = "rockchip,rk3399-pmucru";
1052                 reg = <0x0 0xff750000 0x0 0x1000>;
1053                 #clock-cells = <1>;
1054                 #reset-cells = <1>;
1055                 assigned-clocks = <&pmucru PLL_PPLL>;
1056                 assigned-clock-rates = <676000000>;
1057         };
1058
1059         cru: clock-controller@ff760000 {
1060                 compatible = "rockchip,rk3399-cru";
1061                 reg = <0x0 0xff760000 0x0 0x1000>;
1062                 #clock-cells = <1>;
1063                 #reset-cells = <1>;
1064                 assigned-clocks =
1065                         <&cru ACLK_VOP0>, <&cru HCLK_VOP0>,
1066                         <&cru ACLK_VOP1>, <&cru HCLK_VOP1>,
1067                         <&cru ARMCLKL>, <&cru ARMCLKB>,
1068                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1069                         <&cru PLL_NPLL>,
1070                         <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1071                         <&cru PCLK_PERIHP>,
1072                         <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1073                         <&cru PCLK_PERILP0>,
1074                         <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
1075                 assigned-clock-rates =
1076                          <400000000>,  <200000000>,
1077                          <400000000>,  <200000000>,
1078                          <816000000>, <1008000000>,
1079                          <594000000>,  <800000000>,
1080                         <1000000000>,
1081                          <150000000>,   <75000000>,
1082                           <37500000>,
1083                          <100000000>,  <100000000>,
1084                           <50000000>,
1085                          <100000000>,   <50000000>;
1086         };
1087
1088         grf: syscon@ff770000 {
1089                 compatible = "rockchip,rk3399-grf", "syscon";
1090                 reg = <0x0 0xff770000 0x0 0x10000>;
1091         };
1092
1093         watchdog@ff840000 {
1094                 compatible = "snps,dw-wdt";
1095                 reg = <0x0 0xff840000 0x0 0x100>;
1096                 clocks = <&cru PCLK_WDT>;
1097                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1098         };
1099
1100         spdif: spdif@ff870000 {
1101                 compatible = "rockchip,rk3399-spdif";
1102                 reg = <0x0 0xff870000 0x0 0x1000>;
1103                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
1104                 dmas = <&dmac_bus 7>;
1105                 dma-names = "tx";
1106                 clock-names = "mclk", "hclk";
1107                 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1108                 pinctrl-names = "default";
1109                 pinctrl-0 = <&spdif_bus>;
1110                 status = "disabled";
1111         };
1112
1113         i2s0: i2s@ff880000 {
1114                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1115                 reg = <0x0 0xff880000 0x0 0x1000>;
1116                 rockchip,grf = <&grf>;
1117                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1118                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1119                 dma-names = "tx", "rx";
1120                 clock-names = "i2s_clk", "i2s_hclk";
1121                 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1122                 pinctrl-names = "default";
1123                 pinctrl-0 = <&i2s0_8ch_bus>;
1124                 status = "disabled";
1125         };
1126
1127         i2s1: i2s@ff890000 {
1128                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1129                 reg = <0x0 0xff890000 0x0 0x1000>;
1130                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1131                 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1132                 dma-names = "tx", "rx";
1133                 clock-names = "i2s_clk", "i2s_hclk";
1134                 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1135                 pinctrl-names = "default";
1136                 pinctrl-0 = <&i2s1_2ch_bus>;
1137                 status = "disabled";
1138         };
1139
1140         i2s2: i2s@ff8a0000 {
1141                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1142                 reg = <0x0 0xff8a0000 0x0 0x1000>;
1143                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1144                 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1145                 dma-names = "tx", "rx";
1146                 clock-names = "i2s_clk", "i2s_hclk";
1147                 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1148                 status = "disabled";
1149         };
1150
1151         gpu: gpu@ff9a0000 {
1152                 compatible = "arm,malit860",
1153                              "arm,malit86x",
1154                              "arm,malit8xx",
1155                              "arm,mali-midgard";
1156
1157                 reg = <0x0 0xff9a0000 0x0 0x10000>;
1158
1159                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
1160                              <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
1161                              <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1162                 interrupt-names = "GPU", "JOB", "MMU";
1163
1164                 clocks = <&cru ACLK_GPU>;
1165                 clock-names = "clk_mali";
1166                 #cooling-cells = <2>; /* min followed by max */
1167                 operating-points-v2 = <&gpu_opp_table>;
1168
1169                 status = "disabled";
1170
1171                 power_model {
1172                         compatible = "arm,mali-simple-power-model";
1173                         voltage = <900>;
1174                         frequency = <500>;
1175                         static-power = <500>;
1176                         dynamic-power = <1500>;
1177                         ts = <20000 2000 (-20) 2>;
1178                         thermal-zone = "gpu";
1179                 };
1180         };
1181
1182         gpu_opp_table: gpu_opp_table {
1183                 compatible = "operating-points-v2";
1184                 opp-shared;
1185
1186                 opp00 {
1187                         opp-hz = /bits/ 64 <200000000>;
1188                         opp-microvolt = <900000>;
1189                 };
1190                 opp01 {
1191                         opp-hz = /bits/ 64 <300000000>;
1192                         opp-microvolt = <900000>;
1193                 };
1194                 opp02 {
1195                         opp-hz = /bits/ 64 <400000000>;
1196                         opp-microvolt = <900000>;
1197                 };
1198
1199         };
1200
1201         vopl: vop@ff8f0000 {
1202                 compatible = "rockchip,rk3399-vop-lit";
1203                 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1204                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
1205                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1206                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1207                 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1208                 reset-names = "axi", "ahb", "dclk";
1209                 iommus = <&vopl_mmu>;
1210                 status = "disabled";
1211
1212                 vopl_out: port {
1213                         #address-cells = <1>;
1214                         #size-cells = <0>;
1215
1216                         vopl_out_mipi: endpoint@0 {
1217                                 reg = <0>;
1218                                 remote-endpoint = <&mipi_in_vopl>;
1219                         };
1220
1221                         vopl_out_edp: endpoint@1 {
1222                                 reg = <1>;
1223                                 remote-endpoint = <&edp_in_vopl>;
1224                         };
1225                 };
1226         };
1227
1228         vopl_mmu: iommu@ff8f3f00 {
1229                 compatible = "rockchip,iommu";
1230                 reg = <0x0 0xff8f3f00 0x0 0x100>;
1231                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
1232                 interrupt-names = "vopl_mmu";
1233                 #iommu-cells = <0>;
1234                 status = "disabled";
1235         };
1236
1237         vopb: vop@ff900000 {
1238                 compatible = "rockchip,rk3399-vop-big";
1239                 reg = <0x0 0xff900000 0x0 0x3efc>;
1240                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1241                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1242                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1243                 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1244                 reset-names = "axi", "ahb", "dclk";
1245                 iommus = <&vopb_mmu>;
1246                 status = "disabled";
1247
1248                 vopb_out: port {
1249                         #address-cells = <1>;
1250                         #size-cells = <0>;
1251
1252                         vopb_out_edp: endpoint@0 {
1253                                 reg = <0>;
1254                                 remote-endpoint = <&edp_in_vopb>;
1255                         };
1256
1257                         vopb_out_mipi: endpoint@1 {
1258                                 reg = <1>;
1259                                 remote-endpoint = <&mipi_in_vopb>;
1260                         };
1261                 };
1262         };
1263
1264         vopb_mmu: iommu@ff903f00 {
1265                 compatible = "rockchip,iommu";
1266                 reg = <0x0 0xff903f00 0x0 0x100>;
1267                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1268                 interrupt-names = "vopb_mmu";
1269                 #iommu-cells = <0>;
1270                 status = "disabled";
1271         };
1272
1273         mipi_dsi: mipi@ff960000 {
1274                 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1275                 reg = <0x0 0xff960000 0x0 0x8000>;
1276                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1277                 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
1278                          <&cru SCLK_DPHY_TX0_CFG>;
1279                 clock-names = "ref", "pclk", "phy_cfg";
1280                 rockchip,grf = <&grf>;
1281                 #address-cells = <1>;
1282                 #size-cells = <0>;
1283                 status = "disabled";
1284
1285                 ports {
1286                         #address-cells = <1>;
1287                         #size-cells = <0>;
1288                         reg = <1>;
1289
1290                         mipi_in: port {
1291                                 #address-cells = <1>;
1292                                 #size-cells = <0>;
1293
1294                                 mipi_in_vopb: endpoint@0 {
1295                                         reg = <0>;
1296                                         remote-endpoint = <&vopb_out_mipi>;
1297                                 };
1298                                 mipi_in_vopl: endpoint@1 {
1299                                         reg = <1>;
1300                                         remote-endpoint = <&vopl_out_mipi>;
1301                                 };
1302                         };
1303                 };
1304         };
1305
1306         edp: edp@ff970000 {
1307                 compatible = "rockchip,rk3399-edp";
1308                 reg = <0x0 0xff970000 0x0 0x8000>;
1309                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1310                 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1311                 clock-names = "dp", "pclk";
1312                 resets = <&cru SRST_P_EDP_CTRL>;
1313                 reset-names = "dp";
1314                 rockchip,grf = <&grf>;
1315                 status = "disabled";
1316                 pinctrl-names = "default";
1317                 pinctrl-0 = <&edp_hpd>;
1318
1319                 ports {
1320                         #address-cells = <1>;
1321                         #size-cells = <0>;
1322
1323                         edp_in: port@0 {
1324                                 reg = <0>;
1325                                 #address-cells = <1>;
1326                                 #size-cells = <0>;
1327
1328                                 edp_in_vopb: endpoint@0 {
1329                                         reg = <0>;
1330                                         remote-endpoint = <&vopb_out_edp>;
1331                                 };
1332
1333                                 edp_in_vopl: endpoint@1 {
1334                                         reg = <1>;
1335                                         remote-endpoint = <&vopl_out_edp>;
1336                                 };
1337                         };
1338                 };
1339         };
1340
1341         display_subsystem: display-subsystem {
1342                 compatible = "rockchip,display-subsystem";
1343                 ports = <&vopl_out>, <&vopb_out>;
1344                 status = "disabled";
1345         };
1346
1347         pinctrl: pinctrl {
1348                 compatible = "rockchip,rk3399-pinctrl";
1349                 rockchip,grf = <&grf>;
1350                 rockchip,pmu = <&pmugrf>;
1351                 #address-cells = <0x2>;
1352                 #size-cells = <0x2>;
1353                 ranges;
1354
1355                 gpio0: gpio0@ff720000 {
1356                         compatible = "rockchip,gpio-bank";
1357                         reg = <0x0 0xff720000 0x0 0x100>;
1358                         clocks = <&pmucru PCLK_GPIO0_PMU>;
1359                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1360
1361                         gpio-controller;
1362                         #gpio-cells = <0x2>;
1363
1364                         interrupt-controller;
1365                         #interrupt-cells = <0x2>;
1366                 };
1367
1368                 gpio1: gpio1@ff730000 {
1369                         compatible = "rockchip,gpio-bank";
1370                         reg = <0x0 0xff730000 0x0 0x100>;
1371                         clocks = <&pmucru PCLK_GPIO1_PMU>;
1372                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1373
1374                         gpio-controller;
1375                         #gpio-cells = <0x2>;
1376
1377                         interrupt-controller;
1378                         #interrupt-cells = <0x2>;
1379                 };
1380
1381                 gpio2: gpio2@ff780000 {
1382                         compatible = "rockchip,gpio-bank";
1383                         reg = <0x0 0xff780000 0x0 0x100>;
1384                         clocks = <&cru PCLK_GPIO2>;
1385                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1386
1387                         gpio-controller;
1388                         #gpio-cells = <0x2>;
1389
1390                         interrupt-controller;
1391                         #interrupt-cells = <0x2>;
1392                 };
1393
1394                 gpio3: gpio3@ff788000 {
1395                         compatible = "rockchip,gpio-bank";
1396                         reg = <0x0 0xff788000 0x0 0x100>;
1397                         clocks = <&cru PCLK_GPIO3>;
1398                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1399
1400                         gpio-controller;
1401                         #gpio-cells = <0x2>;
1402
1403                         interrupt-controller;
1404                         #interrupt-cells = <0x2>;
1405                 };
1406
1407                 gpio4: gpio4@ff790000 {
1408                         compatible = "rockchip,gpio-bank";
1409                         reg = <0x0 0xff790000 0x0 0x100>;
1410                         clocks = <&cru PCLK_GPIO4>;
1411                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1412
1413                         gpio-controller;
1414                         #gpio-cells = <0x2>;
1415
1416                         interrupt-controller;
1417                         #interrupt-cells = <0x2>;
1418                 };
1419
1420                 pcfg_pull_up: pcfg-pull-up {
1421                         bias-pull-up;
1422                 };
1423
1424                 pcfg_pull_down: pcfg-pull-down {
1425                         bias-pull-down;
1426                 };
1427
1428                 pcfg_pull_none: pcfg-pull-none {
1429                         bias-disable;
1430                 };
1431
1432                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1433                         bias-disable;
1434                         drive-strength = <12>;
1435                 };
1436
1437                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1438                         bias-pull-up;
1439                         drive-strength = <8>;
1440                 };
1441
1442                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1443                         bias-pull-down;
1444                         drive-strength = <4>;
1445                 };
1446
1447                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1448                         bias-pull-up;
1449                         drive-strength = <2>;
1450                 };
1451
1452                 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
1453                         bias-pull-down;
1454                         drive-strength = <12>;
1455                 };
1456
1457                 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
1458                         bias-disable;
1459                         drive-strength = <13>;
1460                 };
1461
1462                 emmc {
1463                         emmc_pwr: emmc-pwr {
1464                                 rockchip,pins =
1465                                         <0 5 RK_FUNC_1 &pcfg_pull_up>;
1466                         };
1467                 };
1468
1469                 gmac {
1470                         rgmii_pins: rgmii-pins {
1471                                 rockchip,pins =
1472                                         /* mac_txclk */
1473                                         <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
1474                                         /* mac_rxclk */
1475                                         <3 14 RK_FUNC_1 &pcfg_pull_none>,
1476                                         /* mac_mdio */
1477                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
1478                                         /* mac_txen */
1479                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1480                                         /* mac_clk */
1481                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
1482                                         /* mac_rxdv */
1483                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
1484                                         /* mac_mdc */
1485                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
1486                                         /* mac_rxd1 */
1487                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
1488                                         /* mac_rxd0 */
1489                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
1490                                         /* mac_txd1 */
1491                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1492                                         /* mac_txd0 */
1493                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
1494                                         /* mac_rxd3 */
1495                                         <3 3 RK_FUNC_1 &pcfg_pull_none>,
1496                                         /* mac_rxd2 */
1497                                         <3 2 RK_FUNC_1 &pcfg_pull_none>,
1498                                         /* mac_txd3 */
1499                                         <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
1500                                         /* mac_txd2 */
1501                                         <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
1502                         };
1503
1504                         rmii_pins: rmii-pins {
1505                                 rockchip,pins =
1506                                         /* mac_mdio */
1507                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
1508                                         /* mac_txen */
1509                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1510                                         /* mac_clk */
1511                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
1512                                         /* mac_rxer */
1513                                         <3 10 RK_FUNC_1 &pcfg_pull_none>,
1514                                         /* mac_rxdv */
1515                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
1516                                         /* mac_mdc */
1517                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
1518                                         /* mac_rxd1 */
1519                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
1520                                         /* mac_rxd0 */
1521                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
1522                                         /* mac_txd1 */
1523                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1524                                         /* mac_txd0 */
1525                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
1526                         };
1527                 };
1528
1529                 i2c0 {
1530                         i2c0_xfer: i2c0-xfer {
1531                                 rockchip,pins =
1532                                         <1 15 RK_FUNC_2 &pcfg_pull_none>,
1533                                         <1 16 RK_FUNC_2 &pcfg_pull_none>;
1534                         };
1535                 };
1536
1537                 i2c1 {
1538                         i2c1_xfer: i2c1-xfer {
1539                                 rockchip,pins =
1540                                         <4 2 RK_FUNC_1 &pcfg_pull_none>,
1541                                         <4 1 RK_FUNC_1 &pcfg_pull_none>;
1542                         };
1543                 };
1544
1545                 i2c2 {
1546                         i2c2_xfer: i2c2-xfer {
1547                                 rockchip,pins =
1548                                         <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1549                                         <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
1550                         };
1551                 };
1552
1553                 i2c3 {
1554                         i2c3_xfer: i2c3-xfer {
1555                                 rockchip,pins =
1556                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
1557                                         <4 16 RK_FUNC_1 &pcfg_pull_none>;
1558                         };
1559
1560                         i2c3_gpio: i2c3_gpio {
1561                                 rockchip,pins =
1562                                         <4 17 RK_FUNC_GPIO &pcfg_pull_none>,
1563                                         <4 16 RK_FUNC_GPIO &pcfg_pull_none>;
1564                         };
1565
1566                 };
1567
1568                 i2c4 {
1569                         i2c4_xfer: i2c4-xfer {
1570                                 rockchip,pins =
1571                                         <1 12 RK_FUNC_1 &pcfg_pull_none>,
1572                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
1573                         };
1574                 };
1575
1576                 i2c5 {
1577                         i2c5_xfer: i2c5-xfer {
1578                                 rockchip,pins =
1579                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
1580                                         <3 10 RK_FUNC_2 &pcfg_pull_none>;
1581                         };
1582                 };
1583
1584                 i2c6 {
1585                         i2c6_xfer: i2c6-xfer {
1586                                 rockchip,pins =
1587                                         <2 10 RK_FUNC_2 &pcfg_pull_none>,
1588                                         <2 9 RK_FUNC_2 &pcfg_pull_none>;
1589                         };
1590                 };
1591
1592                 i2c7 {
1593                         i2c7_xfer: i2c7-xfer {
1594                                 rockchip,pins =
1595                                         <2 8 RK_FUNC_2 &pcfg_pull_none>,
1596                                         <2 7 RK_FUNC_2 &pcfg_pull_none>;
1597                         };
1598                 };
1599
1600                 i2c8 {
1601                         i2c8_xfer: i2c8-xfer {
1602                                 rockchip,pins =
1603                                         <1 21 RK_FUNC_1 &pcfg_pull_none>,
1604                                         <1 20 RK_FUNC_1 &pcfg_pull_none>;
1605                         };
1606                 };
1607
1608                 i2s0 {
1609                         i2s0_8ch_bus: i2s0-8ch-bus {
1610                                 rockchip,pins =
1611                                         <3 24 RK_FUNC_1 &pcfg_pull_none>,
1612                                         <3 25 RK_FUNC_1 &pcfg_pull_none>,
1613                                         <3 26 RK_FUNC_1 &pcfg_pull_none>,
1614                                         <3 27 RK_FUNC_1 &pcfg_pull_none>,
1615                                         <3 28 RK_FUNC_1 &pcfg_pull_none>,
1616                                         <3 29 RK_FUNC_1 &pcfg_pull_none>,
1617                                         <3 30 RK_FUNC_1 &pcfg_pull_none>,
1618                                         <3 31 RK_FUNC_1 &pcfg_pull_none>,
1619                                         <4 0 RK_FUNC_1 &pcfg_pull_none>;
1620                         };
1621                 };
1622
1623                 i2s1 {
1624                         i2s1_2ch_bus: i2s1-2ch-bus {
1625                                 rockchip,pins =
1626                                         <4 3 RK_FUNC_1 &pcfg_pull_none>,
1627                                         <4 4 RK_FUNC_1 &pcfg_pull_none>,
1628                                         <4 5 RK_FUNC_1 &pcfg_pull_none>,
1629                                         <4 6 RK_FUNC_1 &pcfg_pull_none>,
1630                                         <4 7 RK_FUNC_1 &pcfg_pull_none>;
1631                         };
1632                 };
1633
1634                 sdio0 {
1635                         sdio0_bus1: sdio0-bus1 {
1636                                 rockchip,pins =
1637                                         <2 20 RK_FUNC_1 &pcfg_pull_up>;
1638                         };
1639
1640                         sdio0_bus4: sdio0-bus4 {
1641                                 rockchip,pins =
1642                                         <2 20 RK_FUNC_1 &pcfg_pull_up>,
1643                                         <2 21 RK_FUNC_1 &pcfg_pull_up>,
1644                                         <2 22 RK_FUNC_1 &pcfg_pull_up>,
1645                                         <2 23 RK_FUNC_1 &pcfg_pull_up>;
1646                         };
1647
1648                         sdio0_cmd: sdio0-cmd {
1649                                 rockchip,pins =
1650                                         <2 24 RK_FUNC_1 &pcfg_pull_up>;
1651                         };
1652
1653                         sdio0_clk: sdio0-clk {
1654                                 rockchip,pins =
1655                                         <2 25 RK_FUNC_1 &pcfg_pull_none>;
1656                         };
1657
1658                         sdio0_cd: sdio0-cd {
1659                                 rockchip,pins =
1660                                         <2 26 RK_FUNC_1 &pcfg_pull_up>;
1661                         };
1662
1663                         sdio0_pwr: sdio0-pwr {
1664                                 rockchip,pins =
1665                                         <2 27 RK_FUNC_1 &pcfg_pull_up>;
1666                         };
1667
1668                         sdio0_bkpwr: sdio0-bkpwr {
1669                                 rockchip,pins =
1670                                         <2 28 RK_FUNC_1 &pcfg_pull_up>;
1671                         };
1672
1673                         sdio0_wp: sdio0-wp {
1674                                 rockchip,pins =
1675                                         <0 3 RK_FUNC_1 &pcfg_pull_up>;
1676                         };
1677
1678                         sdio0_int: sdio0-int {
1679                                 rockchip,pins =
1680                                         <0 4 RK_FUNC_1 &pcfg_pull_up>;
1681                         };
1682                 };
1683
1684                 sdmmc {
1685                         sdmmc_bus1: sdmmc-bus1 {
1686                                 rockchip,pins =
1687                                         <4 8 RK_FUNC_1 &pcfg_pull_up>;
1688                         };
1689
1690                         sdmmc_bus4: sdmmc-bus4 {
1691                                 rockchip,pins =
1692                                         <4 8 RK_FUNC_1 &pcfg_pull_up>,
1693                                         <4 9 RK_FUNC_1 &pcfg_pull_up>,
1694                                         <4 10 RK_FUNC_1 &pcfg_pull_up>,
1695                                         <4 11 RK_FUNC_1 &pcfg_pull_up>;
1696                         };
1697
1698                         sdmmc_clk: sdmmc-clk {
1699                                 rockchip,pins =
1700                                         <4 12 RK_FUNC_1 &pcfg_pull_none>;
1701                         };
1702
1703                         sdmmc_cmd: sdmmc-cmd {
1704                                 rockchip,pins =
1705                                         <4 13 RK_FUNC_1 &pcfg_pull_up>;
1706                         };
1707
1708                         sdmmc_cd: sdmcc-cd {
1709                                 rockchip,pins =
1710                                         <0 7 RK_FUNC_1 &pcfg_pull_up>;
1711                         };
1712
1713                         sdmmc_wp: sdmmc-wp {
1714                                 rockchip,pins =
1715                                         <0 8 RK_FUNC_1 &pcfg_pull_up>;
1716                         };
1717                 };
1718
1719                 spdif {
1720                         spdif_bus: spdif-bus {
1721                                 rockchip,pins =
1722                                         <4 21 RK_FUNC_1 &pcfg_pull_none>;
1723                         };
1724                 };
1725
1726                 spi0 {
1727                         spi0_clk: spi0-clk {
1728                                 rockchip,pins =
1729                                         <3 6 RK_FUNC_2 &pcfg_pull_up>;
1730                         };
1731                         spi0_cs0: spi0-cs0 {
1732                                 rockchip,pins =
1733                                         <3 7 RK_FUNC_2 &pcfg_pull_up>;
1734                         };
1735                         spi0_cs1: spi0-cs1 {
1736                                 rockchip,pins =
1737                                         <3 8 RK_FUNC_2 &pcfg_pull_up>;
1738                         };
1739                         spi0_tx: spi0-tx {
1740                                 rockchip,pins =
1741                                         <3 5 RK_FUNC_2 &pcfg_pull_up>;
1742                         };
1743                         spi0_rx: spi0-rx {
1744                                 rockchip,pins =
1745                                         <3 4 RK_FUNC_2 &pcfg_pull_up>;
1746                         };
1747                 };
1748
1749                 spi1 {
1750                         spi1_clk: spi1-clk {
1751                                 rockchip,pins =
1752                                         <1 9 RK_FUNC_2 &pcfg_pull_up>;
1753                         };
1754                         spi1_cs0: spi1-cs0 {
1755                                 rockchip,pins =
1756                                         <1 10 RK_FUNC_2 &pcfg_pull_up>;
1757                         };
1758                         spi1_rx: spi1-rx {
1759                                 rockchip,pins =
1760                                         <1 7 RK_FUNC_2 &pcfg_pull_up>;
1761                         };
1762                         spi1_tx: spi1-tx {
1763                                 rockchip,pins =
1764                                         <1 8 RK_FUNC_2 &pcfg_pull_up>;
1765                         };
1766                 };
1767
1768                 spi2 {
1769                         spi2_clk: spi2-clk {
1770                                 rockchip,pins =
1771                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
1772                         };
1773                         spi2_cs0: spi2-cs0 {
1774                                 rockchip,pins =
1775                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
1776                         };
1777                         spi2_rx: spi2-rx {
1778                                 rockchip,pins =
1779                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
1780                         };
1781                         spi2_tx: spi2-tx {
1782                                 rockchip,pins =
1783                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
1784                         };
1785                 };
1786
1787                 spi3 {
1788                         spi3_clk: spi3-clk {
1789                                 rockchip,pins =
1790                                         <1 17 RK_FUNC_1 &pcfg_pull_up>;
1791                         };
1792                         spi3_cs0: spi3-cs0 {
1793                                 rockchip,pins =
1794                                         <1 18 RK_FUNC_1 &pcfg_pull_up>;
1795                         };
1796                         spi3_rx: spi3-rx {
1797                                 rockchip,pins =
1798                                         <1 15 RK_FUNC_1 &pcfg_pull_up>;
1799                         };
1800                         spi3_tx: spi3-tx {
1801                                 rockchip,pins =
1802                                         <1 16 RK_FUNC_1 &pcfg_pull_up>;
1803                         };
1804                 };
1805
1806                 spi4 {
1807                         spi4_clk: spi4-clk {
1808                                 rockchip,pins =
1809                                         <3 2 RK_FUNC_2 &pcfg_pull_up>;
1810                         };
1811                         spi4_cs0: spi4-cs0 {
1812                                 rockchip,pins =
1813                                         <3 3 RK_FUNC_2 &pcfg_pull_up>;
1814                         };
1815                         spi4_rx: spi4-rx {
1816                                 rockchip,pins =
1817                                         <3 0 RK_FUNC_2 &pcfg_pull_up>;
1818                         };
1819                         spi4_tx: spi4-tx {
1820                                 rockchip,pins =
1821                                         <3 1 RK_FUNC_2 &pcfg_pull_up>;
1822                         };
1823                 };
1824
1825                 spi5 {
1826                         spi5_clk: spi5-clk {
1827                                 rockchip,pins =
1828                                         <2 22 RK_FUNC_2 &pcfg_pull_up>;
1829                         };
1830                         spi5_cs0: spi5-cs0 {
1831                                 rockchip,pins =
1832                                         <2 23 RK_FUNC_2 &pcfg_pull_up>;
1833                         };
1834                         spi5_rx: spi5-rx {
1835                                 rockchip,pins =
1836                                         <2 20 RK_FUNC_2 &pcfg_pull_up>;
1837                         };
1838                         spi5_tx: spi5-tx {
1839                                 rockchip,pins =
1840                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
1841                         };
1842                 };
1843
1844                 tsadc {
1845                         otp_gpio: otp-gpio {
1846                                 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
1847                         };
1848
1849                         otp_out: otp-out {
1850                                 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
1851                         };
1852                 };
1853
1854                 uart0 {
1855                         uart0_xfer: uart0-xfer {
1856                                 rockchip,pins =
1857                                         <2 16 RK_FUNC_1 &pcfg_pull_up>,
1858                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
1859                         };
1860
1861                         uart0_cts: uart0-cts {
1862                                 rockchip,pins =
1863                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
1864                         };
1865
1866                         uart0_rts: uart0-rts {
1867                                 rockchip,pins =
1868                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
1869                         };
1870                 };
1871
1872                 uart1 {
1873                         uart1_xfer: uart1-xfer {
1874                                 rockchip,pins =
1875                                         <3 12 RK_FUNC_2 &pcfg_pull_up>,
1876                                         <3 13 RK_FUNC_2 &pcfg_pull_none>;
1877                         };
1878                 };
1879
1880                 uart2a {
1881                         uart2a_xfer: uart2a-xfer {
1882                                 rockchip,pins =
1883                                         <4 8 RK_FUNC_2 &pcfg_pull_up>,
1884                                         <4 9 RK_FUNC_2 &pcfg_pull_none>;
1885                         };
1886                 };
1887
1888                 uart2b {
1889                         uart2b_xfer: uart2b-xfer {
1890                                 rockchip,pins =
1891                                         <4 16 RK_FUNC_2 &pcfg_pull_up>,
1892                                         <4 17 RK_FUNC_2 &pcfg_pull_none>;
1893                         };
1894                 };
1895
1896                 uart2c {
1897                         uart2c_xfer: uart2c-xfer {
1898                                 rockchip,pins =
1899                                         <4 19 RK_FUNC_1 &pcfg_pull_up>,
1900                                         <4 20 RK_FUNC_1 &pcfg_pull_none>;
1901                         };
1902                 };
1903
1904                 uart3 {
1905                         uart3_xfer: uart3-xfer {
1906                                 rockchip,pins =
1907                                         <3 14 RK_FUNC_2 &pcfg_pull_up>,
1908                                         <3 15 RK_FUNC_2 &pcfg_pull_none>;
1909                         };
1910
1911                         uart3_cts: uart3-cts {
1912                                 rockchip,pins =
1913                                         <3 18 RK_FUNC_2 &pcfg_pull_none>;
1914                         };
1915
1916                         uart3_rts: uart3-rts {
1917                                 rockchip,pins =
1918                                         <3 19 RK_FUNC_2 &pcfg_pull_none>;
1919                         };
1920                 };
1921
1922                 uart4 {
1923                         uart4_xfer: uart4-xfer {
1924                                 rockchip,pins =
1925                                         <1 7 RK_FUNC_1 &pcfg_pull_up>,
1926                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
1927                         };
1928                 };
1929
1930                 uarthdcp {
1931                         uarthdcp_xfer: uarthdcp-xfer {
1932                                 rockchip,pins =
1933                                         <4 21 RK_FUNC_2 &pcfg_pull_up>,
1934                                         <4 22 RK_FUNC_2 &pcfg_pull_none>;
1935                         };
1936                 };
1937
1938                 pwm0 {
1939                         pwm0_pin: pwm0-pin {
1940                                 rockchip,pins =
1941                                         <4 18 RK_FUNC_1 &pcfg_pull_none>;
1942                         };
1943
1944                         vop0_pwm_pin: vop0-pwm-pin {
1945                                 rockchip,pins =
1946                                         <4 18 RK_FUNC_2 &pcfg_pull_none>;
1947                         };
1948                 };
1949
1950                 pwm1 {
1951                         pwm1_pin: pwm1-pin {
1952                                 rockchip,pins =
1953                                         <4 22 RK_FUNC_1 &pcfg_pull_none>;
1954                         };
1955
1956                         vop1_pwm_pin: vop1-pwm-pin {
1957                                 rockchip,pins =
1958                                         <4 18 RK_FUNC_3 &pcfg_pull_none>;
1959                         };
1960                 };
1961
1962                 pwm2 {
1963                         pwm2_pin: pwm2-pin {
1964                                 rockchip,pins =
1965                                         <1 19 RK_FUNC_1 &pcfg_pull_none>;
1966                         };
1967                 };
1968
1969                 pwm3a {
1970                         pwm3a_pin: pwm3a-pin {
1971                                 rockchip,pins =
1972                                         <0 6 RK_FUNC_1 &pcfg_pull_none>;
1973                         };
1974                 };
1975
1976                 pwm3b {
1977                         pwm3b_pin: pwm3b-pin {
1978                                 rockchip,pins =
1979                                         <1 14 RK_FUNC_1 &pcfg_pull_none>;
1980                         };
1981                 };
1982
1983                 edp {
1984                         edp_hpd: edp-hpd {
1985                                 rockchip,pins =
1986                                         <4 23 RK_FUNC_2 &pcfg_pull_none>;
1987                         };
1988                 };
1989
1990                 hdmi {
1991                         hdmi_i2c_xfer: hdmi-i2c-xfer {
1992                                 rockchip,pins =
1993                                         <4 17 RK_FUNC_3 &pcfg_pull_none>,
1994                                         <4 16 RK_FUNC_3 &pcfg_pull_none>;
1995                         };
1996
1997                         hdmi_cec: hdmi-cec {
1998                                 rockchip,pins =
1999                                         <4 23 RK_FUNC_1 &pcfg_pull_none>;
2000                         };
2001                 };
2002         };
2003 };