2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/clock/rk3399-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/interrupt-controller/irq.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/power/rk3399-power.h>
49 #include <dt-bindings/thermal/thermal.h>
52 compatible = "rockchip,rk3399";
53 interrupt-parent = <&gic>;
75 compatible = "arm,psci-1.0";
111 compatible = "arm,cortex-a53", "arm,armv8";
113 enable-method = "psci";
114 #cooling-cells = <2>; /* min followed by max */
115 clocks = <&cru ARMCLKL>;
116 operating-points-v2 = <&cluster0_opp>;
121 compatible = "arm,cortex-a53", "arm,armv8";
123 enable-method = "psci";
124 clocks = <&cru ARMCLKL>;
125 operating-points-v2 = <&cluster0_opp>;
130 compatible = "arm,cortex-a53", "arm,armv8";
132 enable-method = "psci";
133 clocks = <&cru ARMCLKL>;
134 operating-points-v2 = <&cluster0_opp>;
139 compatible = "arm,cortex-a53", "arm,armv8";
141 enable-method = "psci";
142 clocks = <&cru ARMCLKL>;
143 operating-points-v2 = <&cluster0_opp>;
148 compatible = "arm,cortex-a72", "arm,armv8";
150 enable-method = "psci";
151 #cooling-cells = <2>; /* min followed by max */
152 clocks = <&cru ARMCLKB>;
153 operating-points-v2 = <&cluster1_opp>;
158 compatible = "arm,cortex-a72", "arm,armv8";
160 enable-method = "psci";
161 clocks = <&cru ARMCLKB>;
162 operating-points-v2 = <&cluster1_opp>;
166 cluster0_opp: opp_table0 {
167 compatible = "operating-points-v2";
171 opp-hz = /bits/ 64 <408000000>;
172 opp-microvolt = <900000>;
173 clock-latency-ns = <40000>;
176 opp-hz = /bits/ 64 <600000000>;
177 opp-microvolt = <900000>;
180 opp-hz = /bits/ 64 <816000000>;
181 opp-microvolt = <900000>;
184 opp-hz = /bits/ 64 <1008000000>;
185 opp-microvolt = <900000>;
189 cluster1_opp: opp_table1 {
190 compatible = "operating-points-v2";
194 opp-hz = /bits/ 64 <408000000>;
195 opp-microvolt = <900000>;
196 clock-latency-ns = <40000>;
199 opp-hz = /bits/ 64 <600000000>;
200 opp-microvolt = <900000>;
203 opp-hz = /bits/ 64 <816000000>;
204 opp-microvolt = <900000>;
207 opp-hz = /bits/ 64 <1008000000>;
208 opp-microvolt = <900000>;
211 opp-hz = /bits/ 64 <1200000000>;
212 opp-microvolt = <900000>;
217 compatible = "arm,armv8-timer";
218 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
219 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
220 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
221 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
225 compatible = "arm,cortex-a53-pmu";
226 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
227 interrupt-affinity = <&cpu_l0>,
234 compatible = "arm,cortex-a72-pmu", "arm,cortex-a57-pmu";
235 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
236 interrupt-affinity = <&cpu_b0>,
241 compatible = "fixed-clock";
243 clock-frequency = <24000000>;
244 clock-output-names = "xin24m";
248 compatible = "arm,amba-bus";
249 #address-cells = <2>;
253 dmac_bus: dma-controller@ff6d0000 {
254 compatible = "arm,pl330", "arm,primecell";
255 reg = <0x0 0xff6d0000 0x0 0x4000>;
256 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
257 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
259 clocks = <&cru ACLK_DMAC0_PERILP>;
260 clock-names = "apb_pclk";
263 dmac_peri: dma-controller@ff6e0000 {
264 compatible = "arm,pl330", "arm,primecell";
265 reg = <0x0 0xff6e0000 0x0 0x4000>;
266 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
267 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
269 clocks = <&cru ACLK_DMAC1_PERILP>;
270 clock-names = "apb_pclk";
275 compatible = "rockchip,rk3399-gmac";
276 reg = <0x0 0xfe300000 0x0 0x10000>;
277 rockchip,grf = <&grf>;
278 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
279 interrupt-names = "macirq";
280 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
281 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
282 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
284 clock-names = "stmmaceth", "mac_clk_rx",
285 "mac_clk_tx", "clk_mac_ref",
286 "clk_mac_refout", "aclk_mac",
288 resets = <&cru SRST_A_GMAC>;
289 reset-names = "stmmaceth";
294 compatible = "rockchip,rk3399-emmc-phy";
295 reg-offset = <0xf780>;
297 rockchip,grf = <&grf>;
301 sdio0: dwmmc@fe310000 {
302 compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc";
303 reg = <0x0 0xfe310000 0x0 0x4000>;
304 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
305 clock-freq-min-max = <400000 150000000>;
306 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
307 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
308 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
309 fifo-depth = <0x100>;
313 sdmmc: dwmmc@fe320000 {
314 compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc";
315 reg = <0x0 0xfe320000 0x0 0x4000>;
316 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
317 clock-freq-min-max = <400000 150000000>;
318 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
319 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
320 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
321 fifo-depth = <0x100>;
325 sdhci: sdhci@fe330000 {
326 compatible = "arasan,sdhci-5.1";
327 reg = <0x0 0xfe330000 0x0 0x10000>;
328 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
329 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
330 clock-names = "clk_xin", "clk_ahb";
332 phy-names = "phy_arasan";
337 compatible = "rockchip,rk3399-usb-phy";
338 rockchip,grf = <&grf>;
339 vbus_drv-gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>;
340 #address-cells = <1>;
343 usb2phy0: usb2-phy0 {
349 usb2phy1: usb2-phy1 {
356 usb_host0_echi: usb@fe380000 {
357 compatible = "generic-ehci";
358 reg = <0x0 0xfe380000 0x0 0x20000>;
359 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
360 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
361 clock-names = "hclk_host0", "hclk_host0_arb";
363 phy-names = "usb2_phy0";
367 usb_host0_ohci: usb@fe3a0000 {
368 compatible = "generic-ohci";
369 reg = <0x0 0xfe3a0000 0x0 0x20000>;
370 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
371 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
372 clock-names = "hclk_host0", "hclk_host0_arb";
376 usb_host1_echi: usb@fe3c0000 {
377 compatible = "generic-ehci";
378 reg = <0x0 0xfe3c0000 0x0 0x20000>;
379 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
380 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
381 clock-names = "hclk_host1", "hclk_host1_arb";
383 phy-names = "usb2_phy1";
387 usb_host1_ohci: usb@fe3e0000 {
388 compatible = "generic-ohci";
389 reg = <0x0 0xfe3e0000 0x0 0x20000>;
390 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
391 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
392 clock-names = "hclk_host1", "hclk_host1_arb";
396 usbdrd3_0: usb@fe800000 {
397 compatible = "rockchip,dwc3";
398 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
399 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
400 <&cru ACLK_USB3>, <&cru ACLK_USB3_NOC>,
401 <&cru ACLK_USB3_GRF>;
402 clock-names = "clk_usb3otg0_ref", "clk_usb3otg0_suspend",
403 "aclk_usb3otg0", "aclk_usb3_rksoc_axi_perf",
404 "aclk_usb3", "aclk_usb3_noc",
406 #address-cells = <2>;
410 usbdrd_dwc3_0: dwc3 {
411 compatible = "snps,dwc3";
412 reg = <0x0 0xfe800000 0x0 0x100000>;
413 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
416 snps,dis_enblslpm_quirk;
417 snps,phyif_utmi_16_bits;
418 snps,dis_u2_freeclk_exists_quirk;
419 snps,dis_del_phy_power_chg_quirk;
424 usbdrd3_1: usb@fe900000 {
425 compatible = "rockchip,dwc3";
426 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
427 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
428 <&cru ACLK_USB3>, <&cru ACLK_USB3_NOC>,
429 <&cru ACLK_USB3_GRF>;
430 clock-names = "clk_usb3otg1_ref", "clk_usb3otg1_suspend",
431 "aclk_usb3otg1", "aclk_usb3_rksoc_axi_perf",
432 "aclk_usb3", "aclk_usb3_noc",
434 #address-cells = <2>;
438 usbdrd_dwc3_1: dwc3 {
439 compatible = "snps,dwc3";
440 reg = <0x0 0xfe900000 0x0 0x100000>;
441 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
444 snps,dis_enblslpm_quirk;
445 snps,phyif_utmi_16_bits;
446 snps,dis_u2_freeclk_exists_quirk;
447 snps,dis_del_phy_power_chg_quirk;
452 gic: interrupt-controller@fee00000 {
453 compatible = "arm,gic-v3";
454 #interrupt-cells = <3>;
455 #address-cells = <2>;
458 interrupt-controller;
460 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
461 <0x0 0xfef00000 0 0xc0000>, /* GICR */
462 <0x0 0xfff00000 0 0x10000>, /* GICC */
463 <0x0 0xfff10000 0 0x10000>, /* GICH */
464 <0x0 0xfff20000 0 0x10000>; /* GICV */
465 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
466 its: interrupt-controller@fee20000 {
467 compatible = "arm,gic-v3-its";
469 reg = <0x0 0xfee20000 0x0 0x20000>;
473 saradc: saradc@ff100000 {
474 compatible = "rockchip,rk3399-saradc";
475 reg = <0x0 0xff100000 0x0 0x100>;
476 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
477 #io-channel-cells = <1>;
478 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
479 clock-names = "saradc", "apb_pclk";
484 compatible = "rockchip,rk3399-i2c";
485 reg = <0x0 0xff3c0000 0x0 0x1000>;
486 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
487 clock-names = "i2c", "pclk";
488 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
489 pinctrl-names = "default";
490 pinctrl-0 = <&i2c0_xfer>;
491 #address-cells = <1>;
497 compatible = "rockchip,rk3399-i2c";
498 reg = <0x0 0xff110000 0x0 0x1000>;
499 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
500 clock-names = "i2c", "pclk";
501 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
502 pinctrl-names = "default";
503 pinctrl-0 = <&i2c1_xfer>;
504 #address-cells = <1>;
510 compatible = "rockchip,rk3399-i2c";
511 reg = <0x0 0xff120000 0x0 0x1000>;
512 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
513 clock-names = "i2c", "pclk";
514 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
515 pinctrl-names = "default";
516 pinctrl-0 = <&i2c2_xfer>;
517 #address-cells = <1>;
523 compatible = "rockchip,rk3399-i2c";
524 reg = <0x0 0xff130000 0x0 0x1000>;
525 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
526 clock-names = "i2c", "pclk";
527 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
528 pinctrl-names = "default";
529 pinctrl-0 = <&i2c3_xfer>;
530 #address-cells = <1>;
536 compatible = "rockchip,rk3399-i2c";
537 reg = <0x0 0xff140000 0x0 0x1000>;
538 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
539 clock-names = "i2c", "pclk";
540 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
541 pinctrl-names = "default";
542 pinctrl-0 = <&i2c5_xfer>;
543 #address-cells = <1>;
549 compatible = "rockchip,rk3399-i2c";
550 reg = <0x0 0xff150000 0x0 0x1000>;
551 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
552 clock-names = "i2c", "pclk";
553 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
554 pinctrl-names = "default";
555 pinctrl-0 = <&i2c6_xfer>;
556 #address-cells = <1>;
562 compatible = "rockchip,rk3399-i2c";
563 reg = <0x0 0xff160000 0x0 0x1000>;
564 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
565 clock-names = "i2c", "pclk";
566 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
567 pinctrl-names = "default";
568 pinctrl-0 = <&i2c7_xfer>;
569 #address-cells = <1>;
574 uart0: serial@ff180000 {
575 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
576 reg = <0x0 0xff180000 0x0 0x100>;
577 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
578 clock-names = "baudclk", "apb_pclk";
579 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
582 pinctrl-names = "default";
583 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
587 uart1: serial@ff190000 {
588 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
589 reg = <0x0 0xff190000 0x0 0x100>;
590 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
591 clock-names = "baudclk", "apb_pclk";
592 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
595 pinctrl-names = "default";
596 pinctrl-0 = <&uart1_xfer>;
600 uart2: serial@ff1a0000 {
601 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
602 reg = <0x0 0xff1a0000 0x0 0x100>;
603 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
604 clock-names = "baudclk", "apb_pclk";
605 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
608 pinctrl-names = "default";
609 pinctrl-0 = <&uart2c_xfer>;
613 uart3: serial@ff1b0000 {
614 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
615 reg = <0x0 0xff1b0000 0x0 0x100>;
616 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
617 clock-names = "baudclk", "apb_pclk";
618 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
621 pinctrl-names = "default";
622 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
627 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
628 reg = <0x0 0xff1c0000 0x0 0x1000>;
629 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
630 clock-names = "spiclk", "apb_pclk";
631 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
632 pinctrl-names = "default";
633 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
634 #address-cells = <1>;
640 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
641 reg = <0x0 0xff1d0000 0x0 0x1000>;
642 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
643 clock-names = "spiclk", "apb_pclk";
644 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
645 pinctrl-names = "default";
646 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
647 #address-cells = <1>;
653 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
654 reg = <0x0 0xff1e0000 0x0 0x1000>;
655 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
656 clock-names = "spiclk", "apb_pclk";
657 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
658 pinctrl-names = "default";
659 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
660 #address-cells = <1>;
666 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
667 reg = <0x0 0xff1f0000 0x0 0x1000>;
668 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
669 clock-names = "spiclk", "apb_pclk";
670 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
671 pinctrl-names = "default";
672 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
673 #address-cells = <1>;
679 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
680 reg = <0x0 0xff200000 0x0 0x1000>;
681 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
682 clock-names = "spiclk", "apb_pclk";
683 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
684 pinctrl-names = "default";
685 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
686 #address-cells = <1>;
692 #include "rk3368-thermal.dtsi"
695 tsadc: tsadc@ff260000 {
696 compatible = "rockchip,rk3399-tsadc";
697 reg = <0x0 0xff260000 0x0 0x100>;
698 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
699 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
700 clock-names = "tsadc", "apb_pclk";
701 resets = <&cru SRST_TSADC>;
702 reset-names = "tsadc-apb";
703 pinctrl-names = "init", "default", "sleep";
704 pinctrl-0 = <&otp_gpio>;
705 pinctrl-1 = <&otp_out>;
706 pinctrl-2 = <&otp_gpio>;
707 #thermal-sensor-cells = <1>;
708 rockchip,hw-tshut-temp = <95000>;
712 pmu: power-management@ff31000 {
713 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
714 reg = <0x0 0xff310000 0x0 0x1000>;
716 power: power-controller {
718 compatible = "rockchip,rk3399-power-controller";
719 #power-domain-cells = <1>;
720 #address-cells = <1>;
724 reg = <RK3399_PD_CENTER>;
725 #address-cells = <1>;
729 reg = <RK3399_PD_VDU>;
732 reg = <RK3399_PD_VCODEC>;
735 reg = <RK3399_PD_IEP>;
738 reg = <RK3399_PD_RGA>;
742 reg = <RK3399_PD_VIO>;
743 #address-cells = <1>;
747 reg = <RK3399_PD_ISP0>;
750 reg = <RK3399_PD_ISP1>;
753 reg = <RK3399_PD_HDCP>;
756 reg = <RK3399_PD_VO>;
757 #address-cells = <1>;
761 reg = <RK3399_PD_VOPB>;
764 reg = <RK3399_PD_VOPL>;
769 reg = <RK3399_PD_GPU>;
774 pmugrf: syscon@ff320000 {
775 compatible = "rockchip,rk3399-pmugrf", "syscon";
776 reg = <0x0 0xff320000 0x0 0x1000>;
780 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
781 reg = <0x0 0xff350000 0x0 0x1000>;
782 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
783 clock-names = "spiclk", "apb_pclk";
784 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
785 pinctrl-names = "default";
786 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
787 #address-cells = <1>;
792 uart4: serial@ff370000 {
793 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
794 reg = <0x0 0xff370000 0x0 0x100>;
795 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
796 clock-names = "baudclk", "apb_pclk";
797 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
800 pinctrl-names = "default";
801 pinctrl-0 = <&uart4_xfer>;
806 compatible = "rockchip,rk3399-i2c";
807 reg = <0x0 0xff3d0000 0x0 0x1000>;
808 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
809 clock-names = "i2c", "pclk";
810 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
811 pinctrl-names = "default";
812 pinctrl-0 = <&i2c4_xfer>;
813 #address-cells = <1>;
819 compatible = "rockchip,rk3399-i2c";
820 reg = <0x0 0xff3e0000 0x0 0x1000>;
821 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
822 clock-names = "i2c", "pclk";
823 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
824 pinctrl-names = "default";
825 pinctrl-0 = <&i2c8_xfer>;
826 #address-cells = <1>;
832 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
833 reg = <0x0 0xff420000 0x0 0x10>;
835 pinctrl-names = "default";
836 pinctrl-0 = <&pwm0_pin>;
837 clocks = <&pmucru PCLK_RKPWM_PMU>;
843 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
844 reg = <0x0 0xff420010 0x0 0x10>;
846 pinctrl-names = "default";
847 pinctrl-0 = <&pwm1_pin>;
848 clocks = <&pmucru PCLK_RKPWM_PMU>;
854 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
855 reg = <0x0 0xff420020 0x0 0x10>;
857 pinctrl-names = "default";
858 pinctrl-0 = <&pwm2_pin>;
859 clocks = <&pmucru PCLK_RKPWM_PMU>;
865 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
866 reg = <0x0 0xff420030 0x0 0x10>;
868 pinctrl-names = "default";
869 pinctrl-0 = <&pwm3a_pin>;
870 clocks = <&pmucru PCLK_RKPWM_PMU>;
875 pmucru: pmu-clock-controller@ff750000 {
876 compatible = "rockchip,rk3399-pmucru";
877 reg = <0x0 0xff750000 0x0 0x1000>;
878 rockchip,grf = <&pmugrf>;
881 assigned-clocks = <&pmucru PLL_PPLL>;
882 assigned-clock-rates = <676000000>;
885 cru: clock-controller@ff760000 {
886 compatible = "rockchip,rk3399-cru";
887 reg = <0x0 0xff760000 0x0 0x1000>;
888 rockchip,grf = <&grf>;
892 <&cru ARMCLKL>, <&cru ARMCLKB>,
893 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
895 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
897 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
899 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
900 assigned-clock-rates =
901 <816000000>, <1008000000>,
902 <594000000>, <800000000>,
904 <150000000>, <75000000>,
906 <100000000>, <100000000>,
908 <100000000>, <50000000>;
911 grf: syscon@ff770000 {
912 compatible = "rockchip,rk3399-grf", "syscon";
913 reg = <0x0 0xff770000 0x0 0x10000>;
916 wdt0: watchdog@ff840000 {
917 compatible = "snps,dw-wdt";
918 reg = <0x0 0xff840000 0x0 0x100>;
919 clocks = <&cru PCLK_WDT>;
920 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
924 spdif: spdif@ff870000 {
925 compatible = "rockchip,rk3399-spdif";
926 reg = <0x0 0xff870000 0x0 0x1000>;
927 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
928 dmas = <&dmac_bus 7>;
930 clock-names = "hclk", "mclk";
931 clocks = <&cru HCLK_SPDIF>, <&cru SCLK_SPDIF_8CH>;
932 pinctrl-names = "default";
933 pinctrl-0 = <&spdif_bus>;
938 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
939 reg = <0x0 0xff880000 0x0 0x1000>;
940 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
941 #address-cells = <1>;
943 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
944 dma-names = "tx", "rx";
945 clock-names = "i2s_hclk", "i2s_clk";
946 clocks = <&cru HCLK_I2S0_8CH>, <&cru SCLK_I2S0_8CH>;
947 pinctrl-names = "default";
948 pinctrl-0 = <&i2s0_8ch_bus>;
953 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
954 reg = <0x0 0xff890000 0x0 0x1000>;
955 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
956 #address-cells = <1>;
958 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
959 dma-names = "tx", "rx";
960 clock-names = "i2s_hclk", "i2s_clk";
961 clocks = <&cru HCLK_I2S1_8CH>, <&cru SCLK_I2S1_8CH>;
962 pinctrl-names = "default";
963 pinctrl-0 = <&i2s1_2ch_bus>;
968 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
969 reg = <0x0 0xff8a0000 0x0 0x1000>;
970 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
971 #address-cells = <1>;
973 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
974 dma-names = "tx", "rx";
975 clock-names = "i2s_hclk", "i2s_clk";
976 clocks = <&cru HCLK_I2S2_8CH>, <&cru SCLK_I2S2_8CH>;
981 compatible = "rockchip,rk3399-pinctrl";
982 rockchip,grf = <&grf>;
983 rockchip,pmu = <&pmugrf>;
984 #address-cells = <0x2>;
988 gpio0: gpio0@ff720000 {
989 compatible = "rockchip,gpio-bank";
990 reg = <0x0 0xff720000 0x0 0x100>;
991 clocks = <&pmucru PCLK_GPIO0_PMU>;
992 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
997 interrupt-controller;
998 #interrupt-cells = <0x2>;
1001 gpio1: gpio1@ff730000 {
1002 compatible = "rockchip,gpio-bank";
1003 reg = <0x0 0xff730000 0x0 0x100>;
1004 clocks = <&pmucru PCLK_GPIO1_PMU>;
1005 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1008 #gpio-cells = <0x2>;
1010 interrupt-controller;
1011 #interrupt-cells = <0x2>;
1014 gpio2: gpio2@ff780000 {
1015 compatible = "rockchip,gpio-bank";
1016 reg = <0x0 0xff780000 0x0 0x100>;
1017 clocks = <&cru PCLK_GPIO2>;
1018 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1021 #gpio-cells = <0x2>;
1023 interrupt-controller;
1024 #interrupt-cells = <0x2>;
1027 gpio3: gpio3@ff788000 {
1028 compatible = "rockchip,gpio-bank";
1029 reg = <0x0 0xff788000 0x0 0x100>;
1030 clocks = <&cru PCLK_GPIO3>;
1031 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1034 #gpio-cells = <0x2>;
1036 interrupt-controller;
1037 #interrupt-cells = <0x2>;
1040 gpio4: gpio4@ff790000 {
1041 compatible = "rockchip,gpio-bank";
1042 reg = <0x0 0xff790000 0x0 0x100>;
1043 clocks = <&cru PCLK_GPIO4>;
1044 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1047 #gpio-cells = <0x2>;
1049 interrupt-controller;
1050 #interrupt-cells = <0x2>;
1053 pcfg_pull_up: pcfg-pull-up {
1057 pcfg_pull_down: pcfg-pull-down {
1061 pcfg_pull_none: pcfg-pull-none {
1065 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1067 drive-strength = <12>;
1070 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1072 drive-strength = <8>;
1075 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1077 drive-strength = <4>;
1080 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1082 drive-strength = <2>;
1085 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
1087 drive-strength = <12>;
1091 emmc_pwr: emmc-pwr {
1093 <0 5 RK_FUNC_1 &pcfg_pull_up>;
1098 rgmii_pins: rgmii-pins {
1101 <3 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
1103 <3 14 RK_FUNC_1 &pcfg_pull_none>,
1105 <3 13 RK_FUNC_1 &pcfg_pull_none>,
1107 <3 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1109 <3 11 RK_FUNC_1 &pcfg_pull_none>,
1111 <3 9 RK_FUNC_1 &pcfg_pull_none>,
1113 <3 8 RK_FUNC_1 &pcfg_pull_none>,
1115 <3 7 RK_FUNC_1 &pcfg_pull_none>,
1117 <3 6 RK_FUNC_1 &pcfg_pull_none>,
1119 <3 5 RK_FUNC_1 &pcfg_pull_none_12ma>,
1121 <3 4 RK_FUNC_1 &pcfg_pull_none_12ma>,
1123 <3 3 RK_FUNC_1 &pcfg_pull_none>,
1125 <3 2 RK_FUNC_1 &pcfg_pull_none>,
1127 <3 1 RK_FUNC_1 &pcfg_pull_none_12ma>,
1129 <3 0 RK_FUNC_1 &pcfg_pull_none_12ma>;
1132 rmii_pins: rmii-pins {
1135 <3 13 RK_FUNC_1 &pcfg_pull_none>,
1137 <3 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1139 <3 11 RK_FUNC_1 &pcfg_pull_none>,
1141 <3 10 RK_FUNC_1 &pcfg_pull_none>,
1143 <3 9 RK_FUNC_1 &pcfg_pull_none>,
1145 <3 8 RK_FUNC_1 &pcfg_pull_none>,
1147 <3 7 RK_FUNC_1 &pcfg_pull_none>,
1149 <3 6 RK_FUNC_1 &pcfg_pull_none>,
1151 <3 5 RK_FUNC_1 &pcfg_pull_none_12ma>,
1153 <3 4 RK_FUNC_1 &pcfg_pull_none_12ma>;
1158 i2c0_xfer: i2c0-xfer {
1160 <1 15 RK_FUNC_2 &pcfg_pull_none>,
1161 <1 16 RK_FUNC_2 &pcfg_pull_none>;
1166 i2c1_xfer: i2c1-xfer {
1168 <4 2 RK_FUNC_1 &pcfg_pull_none>,
1169 <4 1 RK_FUNC_1 &pcfg_pull_none>;
1174 i2c2_xfer: i2c2-xfer {
1176 <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1177 <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
1182 i2c3_xfer: i2c3-xfer {
1184 <4 17 RK_FUNC_1 &pcfg_pull_none>,
1185 <4 16 RK_FUNC_1 &pcfg_pull_none>;
1190 i2c4_xfer: i2c4-xfer {
1192 <1 12 RK_FUNC_1 &pcfg_pull_none>,
1193 <1 11 RK_FUNC_1 &pcfg_pull_none>;
1198 i2c5_xfer: i2c5-xfer {
1200 <3 11 RK_FUNC_2 &pcfg_pull_none>,
1201 <3 10 RK_FUNC_2 &pcfg_pull_none>;
1206 i2c6_xfer: i2c6-xfer {
1208 <2 10 RK_FUNC_2 &pcfg_pull_none>,
1209 <2 9 RK_FUNC_2 &pcfg_pull_none>;
1214 i2c7_xfer: i2c7-xfer {
1216 <2 8 RK_FUNC_2 &pcfg_pull_none>,
1217 <2 7 RK_FUNC_2 &pcfg_pull_none>;
1222 i2c8_xfer: i2c8-xfer {
1224 <1 21 RK_FUNC_1 &pcfg_pull_none>,
1225 <1 20 RK_FUNC_1 &pcfg_pull_none>;
1230 i2s0_8ch_bus: i2s0-8ch-bus {
1232 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1233 <3 25 RK_FUNC_1 &pcfg_pull_none>,
1234 <3 26 RK_FUNC_1 &pcfg_pull_none>,
1235 <3 27 RK_FUNC_1 &pcfg_pull_none>,
1236 <3 28 RK_FUNC_1 &pcfg_pull_none>,
1237 <3 29 RK_FUNC_1 &pcfg_pull_none>,
1238 <3 30 RK_FUNC_1 &pcfg_pull_none>,
1239 <3 31 RK_FUNC_1 &pcfg_pull_none>,
1240 <4 0 RK_FUNC_1 &pcfg_pull_none>;
1245 i2s1_2ch_bus: i2s1-2ch-bus {
1247 <4 3 RK_FUNC_1 &pcfg_pull_none>,
1248 <4 4 RK_FUNC_1 &pcfg_pull_none>,
1249 <4 5 RK_FUNC_1 &pcfg_pull_none>,
1250 <4 6 RK_FUNC_1 &pcfg_pull_none>,
1251 <4 7 RK_FUNC_1 &pcfg_pull_none>;
1256 sdio0_bus1: sdio0-bus1 {
1258 <2 20 RK_FUNC_1 &pcfg_pull_up>;
1261 sdio0_bus4: sdio0-bus4 {
1263 <2 20 RK_FUNC_1 &pcfg_pull_up>,
1264 <2 21 RK_FUNC_1 &pcfg_pull_up>,
1265 <2 22 RK_FUNC_1 &pcfg_pull_up>,
1266 <2 23 RK_FUNC_1 &pcfg_pull_up>;
1269 sdio0_cmd: sdio0-cmd {
1271 <2 24 RK_FUNC_1 &pcfg_pull_up>;
1274 sdio0_clk: sdio0-clk {
1276 <2 25 RK_FUNC_1 &pcfg_pull_none>;
1279 sdio0_cd: sdio0-cd {
1281 <2 26 RK_FUNC_1 &pcfg_pull_up>;
1284 sdio0_pwr: sdio0-pwr {
1286 <2 27 RK_FUNC_1 &pcfg_pull_up>;
1289 sdio0_bkpwr: sdio0-bkpwr {
1291 <2 28 RK_FUNC_1 &pcfg_pull_up>;
1294 sdio0_wp: sdio0-wp {
1296 <0 3 RK_FUNC_1 &pcfg_pull_up>;
1299 sdio0_int: sdio0-int {
1301 <0 4 RK_FUNC_1 &pcfg_pull_up>;
1306 sdmmc_bus1: sdmmc-bus1 {
1308 <4 8 RK_FUNC_1 &pcfg_pull_up>;
1311 sdmmc_bus4: sdmmc-bus4 {
1313 <4 8 RK_FUNC_1 &pcfg_pull_up>,
1314 <4 9 RK_FUNC_1 &pcfg_pull_up>,
1315 <4 10 RK_FUNC_1 &pcfg_pull_up>,
1316 <4 11 RK_FUNC_1 &pcfg_pull_up>;
1319 sdmmc_clk: sdmmc-clk {
1321 <4 12 RK_FUNC_1 &pcfg_pull_none>;
1324 sdmmc_cmd: sdmmc-cmd {
1326 <4 13 RK_FUNC_1 &pcfg_pull_up>;
1329 sdmmc_cd: sdmcc-cd {
1331 <0 7 RK_FUNC_1 &pcfg_pull_up>;
1334 sdmmc_wp: sdmmc-wp {
1336 <0 8 RK_FUNC_1 &pcfg_pull_up>;
1341 spdif_bus: spdif-bus {
1343 <4 21 RK_FUNC_1 &pcfg_pull_none>;
1348 spi0_clk: spi0-clk {
1350 <3 6 RK_FUNC_2 &pcfg_pull_up>;
1352 spi0_cs0: spi0-cs0 {
1354 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1356 spi0_cs1: spi0-cs1 {
1358 <3 8 RK_FUNC_2 &pcfg_pull_up>;
1362 <3 5 RK_FUNC_2 &pcfg_pull_up>;
1366 <3 4 RK_FUNC_2 &pcfg_pull_up>;
1371 spi1_clk: spi1-clk {
1373 <1 9 RK_FUNC_2 &pcfg_pull_up>;
1375 spi1_cs0: spi1-cs0 {
1377 <1 10 RK_FUNC_2 &pcfg_pull_up>;
1381 <1 7 RK_FUNC_2 &pcfg_pull_up>;
1385 <1 8 RK_FUNC_2 &pcfg_pull_up>;
1390 spi2_clk: spi2-clk {
1392 <2 11 RK_FUNC_1 &pcfg_pull_up>;
1394 spi2_cs0: spi2-cs0 {
1396 <2 12 RK_FUNC_1 &pcfg_pull_up>;
1400 <2 9 RK_FUNC_1 &pcfg_pull_up>;
1404 <2 10 RK_FUNC_1 &pcfg_pull_up>;
1409 spi3_clk: spi3-clk {
1411 <1 17 RK_FUNC_1 &pcfg_pull_up>;
1413 spi3_cs0: spi3-cs0 {
1415 <1 18 RK_FUNC_1 &pcfg_pull_up>;
1419 <1 15 RK_FUNC_1 &pcfg_pull_up>;
1423 <1 16 RK_FUNC_1 &pcfg_pull_up>;
1428 spi4_clk: spi4-clk {
1430 <3 2 RK_FUNC_2 &pcfg_pull_up>;
1432 spi4_cs0: spi4-cs0 {
1434 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1438 <3 0 RK_FUNC_2 &pcfg_pull_up>;
1442 <3 1 RK_FUNC_2 &pcfg_pull_up>;
1447 spi5_clk: spi5-clk {
1449 <2 22 RK_FUNC_2 &pcfg_pull_up>;
1451 spi5_cs0: spi5-cs0 {
1453 <2 23 RK_FUNC_2 &pcfg_pull_up>;
1457 <2 20 RK_FUNC_2 &pcfg_pull_up>;
1461 <2 21 RK_FUNC_2 &pcfg_pull_up>;
1466 otp_gpio: otp-gpio {
1467 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
1471 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
1476 uart0_xfer: uart0-xfer {
1478 <2 16 RK_FUNC_1 &pcfg_pull_up>,
1479 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1482 uart0_cts: uart0-cts {
1484 <2 18 RK_FUNC_1 &pcfg_pull_none>;
1487 uart0_rts: uart0-rts {
1489 <2 19 RK_FUNC_1 &pcfg_pull_none>;
1494 uart1_xfer: uart1-xfer {
1496 <3 12 RK_FUNC_2 &pcfg_pull_up>,
1497 <3 13 RK_FUNC_2 &pcfg_pull_none>;
1502 uart2a_xfer: uart2a-xfer {
1504 <4 8 RK_FUNC_2 &pcfg_pull_up>,
1505 <4 9 RK_FUNC_2 &pcfg_pull_none>;
1510 uart2b_xfer: uart2b-xfer {
1512 <4 16 RK_FUNC_2 &pcfg_pull_up>,
1513 <4 17 RK_FUNC_2 &pcfg_pull_none>;
1518 uart2c_xfer: uart2c-xfer {
1520 <4 19 RK_FUNC_1 &pcfg_pull_up>,
1521 <4 20 RK_FUNC_1 &pcfg_pull_none>;
1526 uart3_xfer: uart3-xfer {
1528 <3 14 RK_FUNC_2 &pcfg_pull_up>,
1529 <3 15 RK_FUNC_2 &pcfg_pull_none>;
1532 uart3_cts: uart3-cts {
1534 <3 18 RK_FUNC_2 &pcfg_pull_none>;
1537 uart3_rts: uart3-rts {
1539 <3 19 RK_FUNC_2 &pcfg_pull_none>;
1544 uart4_xfer: uart4-xfer {
1546 <1 7 RK_FUNC_1 &pcfg_pull_up>,
1547 <1 8 RK_FUNC_1 &pcfg_pull_none>;
1552 uarthdcp_xfer: uarthdcp-xfer {
1554 <4 21 RK_FUNC_2 &pcfg_pull_up>,
1555 <4 22 RK_FUNC_2 &pcfg_pull_none>;
1560 pwm0_pin: pwm0-pin {
1562 <4 18 RK_FUNC_1 &pcfg_pull_none>;
1565 vop0_pwm_pin: vop0-pwm-pin {
1567 <4 18 RK_FUNC_2 &pcfg_pull_none>;
1572 pwm1_pin: pwm1-pin {
1574 <4 22 RK_FUNC_1 &pcfg_pull_none>;
1577 vop1_pwm_pin: vop1-pwm-pin {
1579 <4 18 RK_FUNC_3 &pcfg_pull_none>;
1584 pwm2_pin: pwm2-pin {
1586 <1 19 RK_FUNC_1 &pcfg_pull_none>;
1591 pwm3a_pin: pwm3a-pin {
1593 <0 6 RK_FUNC_1 &pcfg_pull_none>;
1598 pwm3b_pin: pwm3b-pin {
1600 <1 14 RK_FUNC_1 &pcfg_pull_none>;
1605 pmic_int_l: pmic-int-l {
1607 <1 21 RK_FUNC_GPIO &pcfg_pull_up>;