2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/clock/rk3399-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/interrupt-controller/irq.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/power/rk3399-power.h>
49 #include <dt-bindings/soc/rockchip_boot-mode.h>
50 #include <dt-bindings/thermal/thermal.h>
53 compatible = "rockchip,rk3399";
55 interrupt-parent = <&gic>;
77 compatible = "arm,psci-1.0";
113 compatible = "arm,cortex-a53", "arm,armv8";
115 enable-method = "psci";
116 #cooling-cells = <2>; /* min followed by max */
117 dynamic-power-coefficient = <121>;
118 clocks = <&cru ARMCLKL>;
119 cpu-idle-states = <&cpu_sleep>;
120 operating-points-v2 = <&cluster0_opp>;
121 sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
126 compatible = "arm,cortex-a53", "arm,armv8";
128 enable-method = "psci";
129 clocks = <&cru ARMCLKL>;
130 cpu-idle-states = <&cpu_sleep>;
131 operating-points-v2 = <&cluster0_opp>;
132 sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
137 compatible = "arm,cortex-a53", "arm,armv8";
139 enable-method = "psci";
140 clocks = <&cru ARMCLKL>;
141 cpu-idle-states = <&cpu_sleep>;
142 operating-points-v2 = <&cluster0_opp>;
143 sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
148 compatible = "arm,cortex-a53", "arm,armv8";
150 enable-method = "psci";
151 clocks = <&cru ARMCLKL>;
152 cpu-idle-states = <&cpu_sleep>;
153 operating-points-v2 = <&cluster0_opp>;
154 sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
159 compatible = "arm,cortex-a72", "arm,armv8";
161 enable-method = "psci";
162 #cooling-cells = <2>; /* min followed by max */
163 dynamic-power-coefficient = <1068>;
164 clocks = <&cru ARMCLKB>;
165 cpu-idle-states = <&cpu_sleep>;
166 operating-points-v2 = <&cluster1_opp>;
167 sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>;
172 compatible = "arm,cortex-a72", "arm,armv8";
174 enable-method = "psci";
175 clocks = <&cru ARMCLKB>;
176 cpu-idle-states = <&cpu_sleep>;
177 operating-points-v2 = <&cluster1_opp>;
178 sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>;
182 entry-method = "psci";
183 cpu_sleep: cpu-sleep-0 {
184 compatible = "arm,idle-state";
186 arm,psci-suspend-param = <0x0010000>;
187 entry-latency-us = <350>;
188 exit-latency-us = <600>;
189 min-residency-us = <1150>;
193 /include/ "rk3399-sched-energy.dtsi"
197 cluster0_opp: opp_table0 {
198 compatible = "operating-points-v2";
202 opp-hz = /bits/ 64 <408000000>;
203 opp-microvolt = <800000>;
204 clock-latency-ns = <40000>;
207 opp-hz = /bits/ 64 <600000000>;
208 opp-microvolt = <800000>;
211 opp-hz = /bits/ 64 <816000000>;
212 opp-microvolt = <800000>;
215 opp-hz = /bits/ 64 <1008000000>;
216 opp-microvolt = <875000>;
219 opp-hz = /bits/ 64 <1200000000>;
220 opp-microvolt = <925000>;
223 opp-hz = /bits/ 64 <1416000000>;
224 opp-microvolt = <1025000>;
228 cluster1_opp: opp_table1 {
229 compatible = "operating-points-v2";
233 opp-hz = /bits/ 64 <408000000>;
234 opp-microvolt = <800000>;
235 clock-latency-ns = <40000>;
238 opp-hz = /bits/ 64 <600000000>;
239 opp-microvolt = <800000>;
242 opp-hz = /bits/ 64 <816000000>;
243 opp-microvolt = <800000>;
246 opp-hz = /bits/ 64 <1008000000>;
247 opp-microvolt = <850000>;
250 opp-hz = /bits/ 64 <1200000000>;
251 opp-microvolt = <925000>;
256 compatible = "arm,armv8-timer";
257 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
258 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
259 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
260 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
264 compatible = "arm,armv8-pmuv3";
265 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
269 compatible = "fixed-clock";
271 clock-frequency = <24000000>;
272 clock-output-names = "xin24m";
276 compatible = "arm,amba-bus";
277 #address-cells = <2>;
281 dmac_bus: dma-controller@ff6d0000 {
282 compatible = "arm,pl330", "arm,primecell";
283 reg = <0x0 0xff6d0000 0x0 0x4000>;
284 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
285 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
287 clocks = <&cru ACLK_DMAC0_PERILP>;
288 clock-names = "apb_pclk";
289 peripherals-req-type-burst;
292 dmac_peri: dma-controller@ff6e0000 {
293 compatible = "arm,pl330", "arm,primecell";
294 reg = <0x0 0xff6e0000 0x0 0x4000>;
295 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
296 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
298 clocks = <&cru ACLK_DMAC1_PERILP>;
299 clock-names = "apb_pclk";
300 peripherals-req-type-burst;
305 compatible = "rockchip,rk3399-gmac";
306 reg = <0x0 0xfe300000 0x0 0x10000>;
307 rockchip,grf = <&grf>;
308 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
309 interrupt-names = "macirq";
310 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
311 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
312 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
314 clock-names = "stmmaceth", "mac_clk_rx",
315 "mac_clk_tx", "clk_mac_ref",
316 "clk_mac_refout", "aclk_mac",
318 resets = <&cru SRST_A_GMAC>;
319 reset-names = "stmmaceth";
324 compatible = "rockchip,rk3399-emmc-phy";
325 reg-offset = <0xf780>;
327 rockchip,grf = <&grf>;
328 ctrl-base = <0xfe330000>;
332 sdio0: dwmmc@fe310000 {
333 compatible = "rockchip,rk3399-dw-mshc",
334 "rockchip,rk3288-dw-mshc";
335 reg = <0x0 0xfe310000 0x0 0x4000>;
336 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
337 clock-freq-min-max = <400000 150000000>;
338 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
339 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
340 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
341 fifo-depth = <0x100>;
345 sdmmc: dwmmc@fe320000 {
346 compatible = "rockchip,rk3399-dw-mshc",
347 "rockchip,rk3288-dw-mshc";
348 reg = <0x0 0xfe320000 0x0 0x4000>;
349 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
350 clock-freq-min-max = <400000 150000000>;
351 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
352 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
353 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
354 fifo-depth = <0x100>;
358 sdhci: sdhci@fe330000 {
359 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
360 reg = <0x0 0xfe330000 0x0 0x10000>;
361 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
362 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
363 clock-names = "clk_xin", "clk_ahb";
364 assigned-clocks = <&cru SCLK_EMMC>;
365 assigned-clock-parents = <&cru PLL_CPLL>;
366 assigned-clock-rates = <200000000>;
368 phy-names = "phy_arasan";
372 usb_host0_ehci: usb@fe380000 {
373 compatible = "generic-ehci";
374 reg = <0x0 0xfe380000 0x0 0x20000>;
375 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
376 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
377 clock-names = "hclk_host0", "hclk_host0_arb";
378 phys = <&u2phy0_host>;
383 usb_host0_ohci: usb@fe3a0000 {
384 compatible = "generic-ohci";
385 reg = <0x0 0xfe3a0000 0x0 0x20000>;
386 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
387 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
388 clock-names = "hclk_host0", "hclk_host0_arb";
392 usb_host1_ehci: usb@fe3c0000 {
393 compatible = "generic-ehci";
394 reg = <0x0 0xfe3c0000 0x0 0x20000>;
395 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
396 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
397 clock-names = "hclk_host1", "hclk_host1_arb";
398 phys = <&u2phy1_host>;
403 usb_host1_ohci: usb@fe3e0000 {
404 compatible = "generic-ohci";
405 reg = <0x0 0xfe3e0000 0x0 0x20000>;
406 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
407 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
408 clock-names = "hclk_host1", "hclk_host1_arb";
412 usbdrd3_0: usb@fe800000 {
413 compatible = "rockchip,dwc3";
414 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
415 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
416 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
417 clock-names = "clk_usb3otg0_ref", "clk_usb3otg0_suspend",
418 "aclk_usb3otg0", "aclk_usb3_rksoc_axi_perf",
419 "aclk_usb3", "aclk_usb3_grf";
420 #address-cells = <2>;
424 usbdrd_dwc3_0: dwc3@fe800000 {
425 compatible = "snps,dwc3";
426 reg = <0x0 0xfe800000 0x0 0x100000>;
427 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
429 snps,dis_enblslpm_quirk;
430 snps,phyif_utmi_16_bits;
431 snps,dis_u2_freeclk_exists_quirk;
432 snps,dis_del_phy_power_chg_quirk;
433 snps,xhci_slow_suspend_quirk;
438 usbdrd3_1: usb@fe900000 {
439 compatible = "rockchip,dwc3";
440 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
441 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
442 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
443 clock-names = "clk_usb3otg1_ref", "clk_usb3otg1_suspend",
444 "aclk_usb3otg1", "aclk_usb3_rksoc_axi_perf",
445 "aclk_usb3", "aclk_usb3_grf";
446 #address-cells = <2>;
450 usbdrd_dwc3_1: dwc3@fe900000 {
451 compatible = "snps,dwc3";
452 reg = <0x0 0xfe900000 0x0 0x100000>;
453 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
455 snps,dis_enblslpm_quirk;
456 snps,phyif_utmi_16_bits;
457 snps,dis_u2_freeclk_exists_quirk;
458 snps,dis_del_phy_power_chg_quirk;
459 snps,xhci_slow_suspend_quirk;
464 gic: interrupt-controller@fee00000 {
465 compatible = "arm,gic-v3";
466 #interrupt-cells = <3>;
467 #address-cells = <2>;
470 interrupt-controller;
472 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
473 <0x0 0xfef00000 0 0xc0000>, /* GICR */
474 <0x0 0xfff00000 0 0x10000>, /* GICC */
475 <0x0 0xfff10000 0 0x10000>, /* GICH */
476 <0x0 0xfff20000 0 0x10000>; /* GICV */
477 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
478 its: interrupt-controller@fee20000 {
479 compatible = "arm,gic-v3-its";
481 reg = <0x0 0xfee20000 0x0 0x20000>;
485 saradc: saradc@ff100000 {
486 compatible = "rockchip,rk3399-saradc";
487 reg = <0x0 0xff100000 0x0 0x100>;
488 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
489 #io-channel-cells = <1>;
490 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
491 clock-names = "saradc", "apb_pclk";
496 compatible = "rockchip,rk3399-i2c";
497 reg = <0x0 0xff3c0000 0x0 0x1000>;
498 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
499 clock-names = "i2c", "pclk";
500 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
501 pinctrl-names = "default";
502 pinctrl-0 = <&i2c0_xfer>;
503 #address-cells = <1>;
509 compatible = "rockchip,rk3399-i2c";
510 reg = <0x0 0xff110000 0x0 0x1000>;
511 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
512 clock-names = "i2c", "pclk";
513 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
514 pinctrl-names = "default";
515 pinctrl-0 = <&i2c1_xfer>;
516 #address-cells = <1>;
522 compatible = "rockchip,rk3399-i2c";
523 reg = <0x0 0xff120000 0x0 0x1000>;
524 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
525 clock-names = "i2c", "pclk";
526 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
527 pinctrl-names = "default";
528 pinctrl-0 = <&i2c2_xfer>;
529 #address-cells = <1>;
535 compatible = "rockchip,rk3399-i2c";
536 reg = <0x0 0xff130000 0x0 0x1000>;
537 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
538 clock-names = "i2c", "pclk";
539 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
540 pinctrl-names = "default";
541 pinctrl-0 = <&i2c3_xfer>;
542 #address-cells = <1>;
548 compatible = "rockchip,rk3399-i2c";
549 reg = <0x0 0xff140000 0x0 0x1000>;
550 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
551 clock-names = "i2c", "pclk";
552 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
553 pinctrl-names = "default";
554 pinctrl-0 = <&i2c5_xfer>;
555 #address-cells = <1>;
561 compatible = "rockchip,rk3399-i2c";
562 reg = <0x0 0xff150000 0x0 0x1000>;
563 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
564 clock-names = "i2c", "pclk";
565 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
566 pinctrl-names = "default";
567 pinctrl-0 = <&i2c6_xfer>;
568 #address-cells = <1>;
574 compatible = "rockchip,rk3399-i2c";
575 reg = <0x0 0xff160000 0x0 0x1000>;
576 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
577 clock-names = "i2c", "pclk";
578 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
579 pinctrl-names = "default";
580 pinctrl-0 = <&i2c7_xfer>;
581 #address-cells = <1>;
586 uart0: serial@ff180000 {
587 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
588 reg = <0x0 0xff180000 0x0 0x100>;
589 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
590 clock-names = "baudclk", "apb_pclk";
591 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
594 pinctrl-names = "default";
595 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
599 uart1: serial@ff190000 {
600 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
601 reg = <0x0 0xff190000 0x0 0x100>;
602 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
603 clock-names = "baudclk", "apb_pclk";
604 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
607 pinctrl-names = "default";
608 pinctrl-0 = <&uart1_xfer>;
612 uart2: serial@ff1a0000 {
613 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
614 reg = <0x0 0xff1a0000 0x0 0x100>;
615 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
616 clock-names = "baudclk", "apb_pclk";
617 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
620 pinctrl-names = "default";
621 pinctrl-0 = <&uart2c_xfer>;
625 uart3: serial@ff1b0000 {
626 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
627 reg = <0x0 0xff1b0000 0x0 0x100>;
628 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
629 clock-names = "baudclk", "apb_pclk";
630 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
633 pinctrl-names = "default";
634 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
639 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
640 reg = <0x0 0xff1c0000 0x0 0x1000>;
641 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
642 clock-names = "spiclk", "apb_pclk";
643 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
644 pinctrl-names = "default";
645 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
646 #address-cells = <1>;
652 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
653 reg = <0x0 0xff1d0000 0x0 0x1000>;
654 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
655 clock-names = "spiclk", "apb_pclk";
656 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
657 pinctrl-names = "default";
658 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
659 #address-cells = <1>;
665 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
666 reg = <0x0 0xff1e0000 0x0 0x1000>;
667 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
668 clock-names = "spiclk", "apb_pclk";
669 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
670 pinctrl-names = "default";
671 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
672 #address-cells = <1>;
678 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
679 reg = <0x0 0xff1f0000 0x0 0x1000>;
680 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
681 clock-names = "spiclk", "apb_pclk";
682 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
683 pinctrl-names = "default";
684 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
685 #address-cells = <1>;
691 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
692 reg = <0x0 0xff200000 0x0 0x1000>;
693 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
694 clock-names = "spiclk", "apb_pclk";
695 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
696 pinctrl-names = "default";
697 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
698 #address-cells = <1>;
704 soc_thermal: soc-thermal {
705 polling-delay-passive = <20>; /* milliseconds */
706 polling-delay = <1000>; /* milliseconds */
707 sustainable-power = <1600>; /* milliwatts */
709 thermal-sensors = <&tsadc 0>;
712 threshold: trip-point@0 {
713 temperature = <70000>; /* millicelsius */
714 hysteresis = <2000>; /* millicelsius */
717 target: trip-point@1 {
718 temperature = <85000>; /* millicelsius */
719 hysteresis = <2000>; /* millicelsius */
723 temperature = <95000>; /* millicelsius */
724 hysteresis = <2000>; /* millicelsius */
733 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
734 contribution = <10240>;
739 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
740 contribution = <1024>;
745 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
746 contribution = <10240>;
751 gpu_thermal: gpu-thermal {
752 polling-delay-passive = <100>; /* milliseconds */
753 polling-delay = <1000>; /* milliseconds */
755 thermal-sensors = <&tsadc 1>;
759 tsadc: tsadc@ff260000 {
760 compatible = "rockchip,rk3399-tsadc";
761 reg = <0x0 0xff260000 0x0 0x100>;
762 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
763 rockchip,grf = <&grf>;
764 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
765 clock-names = "tsadc", "apb_pclk";
766 assigned-clocks = <&cru SCLK_TSADC>;
767 assigned-clock-rates = <750000>;
768 resets = <&cru SRST_TSADC>;
769 reset-names = "tsadc-apb";
770 pinctrl-names = "init", "default", "sleep";
771 pinctrl-0 = <&otp_gpio>;
772 pinctrl-1 = <&otp_out>;
773 pinctrl-2 = <&otp_gpio>;
774 #thermal-sensor-cells = <1>;
775 rockchip,hw-tshut-temp = <95000>;
779 qos_hdcp: qos@ffa90000 {
780 compatible = "syscon";
781 reg = <0x0 0xffa90000 0x0 0x20>;
784 qos_iep: qos@ffa98000 {
785 compatible = "syscon";
786 reg = <0x0 0xffa98000 0x0 0x20>;
789 qos_isp0_m0: qos@ffaa0000 {
790 compatible = "syscon";
791 reg = <0x0 0xffaa0000 0x0 0x20>;
794 qos_isp0_m1: qos@ffaa0080 {
795 compatible = "syscon";
796 reg = <0x0 0xffaa0080 0x0 0x20>;
799 qos_isp1_m0: qos@ffaa8000 {
800 compatible = "syscon";
801 reg = <0x0 0xffaa8000 0x0 0x20>;
804 qos_isp1_m1: qos@ffaa8080 {
805 compatible = "syscon";
806 reg = <0x0 0xffaa8080 0x0 0x20>;
809 qos_rga_r: qos@ffab0000 {
810 compatible = "syscon";
811 reg = <0x0 0xffab0000 0x0 0x20>;
814 qos_rga_w: qos@ffab0080 {
815 compatible = "syscon";
816 reg = <0x0 0xffab0080 0x0 0x20>;
819 qos_video_m0: qos@ffab8000 {
820 compatible = "syscon";
821 reg = <0x0 0xffab8000 0x0 0x20>;
824 qos_video_m1_r: qos@ffac0000 {
825 compatible = "syscon";
826 reg = <0x0 0xffac0000 0x0 0x20>;
829 qos_video_m1_w: qos@ffac0080 {
830 compatible = "syscon";
831 reg = <0x0 0xffac0080 0x0 0x20>;
834 qos_vop_big_r: qos@ffac8000 {
835 compatible = "syscon";
836 reg = <0x0 0xffac8000 0x0 0x20>;
839 qos_vop_big_w: qos@ffac8080 {
840 compatible = "syscon";
841 reg = <0x0 0xffac8080 0x0 0x20>;
844 qos_vop_little: qos@ffad0000 {
845 compatible = "syscon";
846 reg = <0x0 0xffad0000 0x0 0x20>;
849 qos_gpu: qos@ffae0000 {
850 compatible = "syscon";
851 reg = <0x0 0xffae0000 0x0 0x20>;
854 pmu: power-management@ff310000 {
855 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
856 reg = <0x0 0xff310000 0x0 0x1000>;
859 * Note: RK3399 supports 6 voltage domains including VD_CORE_L,
860 * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
861 * Some of the power domains are grouped together for every
863 * The detail contents as below.
865 power: power-controller {
866 compatible = "rockchip,rk3399-power-controller";
867 #power-domain-cells = <1>;
868 #address-cells = <1>;
871 /* These power domains are grouped by VD_CENTER */
872 pd_iep@RK3399_PD_IEP {
873 reg = <RK3399_PD_IEP>;
874 clocks = <&cru ACLK_IEP>,
878 pd_rga@RK3399_PD_RGA {
879 reg = <RK3399_PD_RGA>;
880 clocks = <&cru ACLK_RGA>,
882 pm_qos = <&qos_rga_r>,
885 pd_vcodec@RK3399_PD_VCODEC {
886 reg = <RK3399_PD_VCODEC>;
887 clocks = <&cru ACLK_VCODEC>,
889 pm_qos = <&qos_video_m0>;
891 pd_vdu@RK3399_PD_VDU {
892 reg = <RK3399_PD_VDU>;
893 clocks = <&cru ACLK_VDU>,
895 pm_qos = <&qos_video_m1_r>,
899 /* These power domains are grouped by VD_GPU */
900 pd_gpu@RK3399_PD_GPU {
901 reg = <RK3399_PD_GPU>;
902 clocks = <&cru ACLK_GPU>;
906 /* These power domains are grouped by VD_LOGIC */
907 pd_vio@RK3399_PD_VIO {
908 reg = <RK3399_PD_VIO>;
909 #address-cells = <1>;
912 pd_hdcp@RK3399_PD_HDCP {
913 reg = <RK3399_PD_HDCP>;
914 clocks = <&cru ACLK_HDCP>,
917 pm_qos = <&qos_hdcp>;
919 pd_isp0@RK3399_PD_ISP0 {
920 reg = <RK3399_PD_ISP0>;
921 clocks = <&cru ACLK_ISP0>,
923 pm_qos = <&qos_isp0_m0>,
926 pd_isp1@RK3399_PD_ISP1 {
927 reg = <RK3399_PD_ISP1>;
928 clocks = <&cru ACLK_ISP1>,
930 pm_qos = <&qos_isp1_m0>,
934 reg = <RK3399_PD_VO>;
935 #address-cells = <1>;
938 pd_vopb@RK3399_PD_VOPB {
939 reg = <RK3399_PD_VOPB>;
940 clocks = <&cru ACLK_VOP0>,
942 pm_qos = <&qos_vop_big_r>,
945 pd_vopl@RK3399_PD_VOPL {
946 reg = <RK3399_PD_VOPL>;
947 clocks = <&cru ACLK_VOP1>,
949 pm_qos = <&qos_vop_little>;
956 pmugrf: syscon@ff320000 {
957 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
958 reg = <0x0 0xff320000 0x0 0x1000>;
961 compatible = "syscon-reboot-mode";
963 mode-normal = <BOOT_NORMAL>;
964 mode-recovery = <BOOT_RECOVERY>;
965 mode-bootloader = <BOOT_FASTBOOT>;
966 mode-loader = <BOOT_LOADER>;
971 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
972 reg = <0x0 0xff350000 0x0 0x1000>;
973 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
974 clock-names = "spiclk", "apb_pclk";
975 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
976 pinctrl-names = "default";
977 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
978 #address-cells = <1>;
983 uart4: serial@ff370000 {
984 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
985 reg = <0x0 0xff370000 0x0 0x100>;
986 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
987 clock-names = "baudclk", "apb_pclk";
988 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
991 pinctrl-names = "default";
992 pinctrl-0 = <&uart4_xfer>;
997 compatible = "rockchip,rk3399-i2c";
998 reg = <0x0 0xff3d0000 0x0 0x1000>;
999 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
1000 clock-names = "i2c", "pclk";
1001 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
1002 pinctrl-names = "default";
1003 pinctrl-0 = <&i2c4_xfer>;
1004 #address-cells = <1>;
1006 status = "disabled";
1009 i2c8: i2c@ff3e0000 {
1010 compatible = "rockchip,rk3399-i2c";
1011 reg = <0x0 0xff3e0000 0x0 0x1000>;
1012 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
1013 clock-names = "i2c", "pclk";
1014 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
1015 pinctrl-names = "default";
1016 pinctrl-0 = <&i2c8_xfer>;
1017 #address-cells = <1>;
1019 status = "disabled";
1022 pcie0: pcie@f8000000 {
1023 compatible = "rockchip,rk3399-pcie";
1024 #address-cells = <3>;
1026 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
1027 <&cru PCLK_PCIE>, <&cru SCLK_PCIEPHY_REF>;
1028 clock-names = "aclk_pcie", "aclk_perf_pcie",
1029 "hclk_pcie", "clk_pciephy_ref";
1030 bus-range = <0x0 0x1>;
1031 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
1032 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
1033 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
1034 interrupt-names = "pcie-sys", "pcie-legacy", "pcie-client";
1035 ranges = < 0x82000000 0 0xfa000000 0x0 0xfa000000 0 0x600000
1036 0x81000000 0 0xfa600000 0x0 0xfa600000 0 0x100000 >;
1037 reg = < 0x0 0xf8000000 0x0 0x2000000 >,
1038 < 0x0 0xfd000000 0x0 0x1000000 >;
1039 reg-name = "axi-base", "apb-base";
1040 resets = <&cru SRST_PCIEPHY>, <&cru SRST_PCIE_CORE>,
1041 <&cru SRST_PCIE_MGMT>, <&cru SRST_PCIE_MGMT_STICKY>,
1042 <&cru SRST_PCIE_PIPE>;
1043 reset-names = "phy-rst", "core-rst", "mgmt-rst",
1044 "mgmt-sticky-rst", "pipe-rst";
1045 rockchip,grf = <&grf>;
1046 pcie-conf = <0xe220>;
1047 pcie-status = <0xe2a4>;
1048 pcie-laneoff = <0xe214>;
1049 msi-parent = <&its>;
1050 #interrupt-cells = <1>;
1051 interrupt-map-mask = <0 0 0 7>;
1052 interrupt-map = <0 0 0 1 &pcie0 1>,
1056 status = "disabled";
1057 pcie_intc: interrupt-controller {
1058 interrupt-controller;
1059 #address-cells = <0>;
1060 #interrupt-cells = <1>;
1064 pwm0: pwm@ff420000 {
1065 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1066 reg = <0x0 0xff420000 0x0 0x10>;
1068 pinctrl-names = "default";
1069 pinctrl-0 = <&pwm0_pin>;
1070 clocks = <&pmucru PCLK_RKPWM_PMU>;
1071 clock-names = "pwm";
1072 status = "disabled";
1075 pwm1: pwm@ff420010 {
1076 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1077 reg = <0x0 0xff420010 0x0 0x10>;
1079 pinctrl-names = "default";
1080 pinctrl-0 = <&pwm1_pin>;
1081 clocks = <&pmucru PCLK_RKPWM_PMU>;
1082 clock-names = "pwm";
1083 status = "disabled";
1086 pwm2: pwm@ff420020 {
1087 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1088 reg = <0x0 0xff420020 0x0 0x10>;
1090 pinctrl-names = "default";
1091 pinctrl-0 = <&pwm2_pin>;
1092 clocks = <&pmucru PCLK_RKPWM_PMU>;
1093 clock-names = "pwm";
1094 status = "disabled";
1097 pwm3: pwm@ff420030 {
1098 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1099 reg = <0x0 0xff420030 0x0 0x10>;
1101 pinctrl-names = "default";
1102 pinctrl-0 = <&pwm3a_pin>;
1103 clocks = <&pmucru PCLK_RKPWM_PMU>;
1104 clock-names = "pwm";
1105 status = "disabled";
1109 compatible = "rockchip,rk3399-rga";
1110 reg = <0x0 0xff680000 0x0 0x10000>;
1111 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
1112 interrupt-names = "rga";
1113 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
1114 clock-names = "aclk", "hclk", "sclk";
1115 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
1116 reset-names = "core", "axi", "ahb";
1117 status = "disabled";
1120 pmucru: pmu-clock-controller@ff750000 {
1121 compatible = "rockchip,rk3399-pmucru";
1122 reg = <0x0 0xff750000 0x0 0x1000>;
1125 assigned-clocks = <&pmucru PLL_PPLL>;
1126 assigned-clock-rates = <676000000>;
1129 cru: clock-controller@ff760000 {
1130 compatible = "rockchip,rk3399-cru";
1131 reg = <0x0 0xff760000 0x0 0x1000>;
1135 <&cru ACLK_VOP0>, <&cru HCLK_VOP0>,
1136 <&cru ACLK_VOP1>, <&cru HCLK_VOP1>,
1137 <&cru ARMCLKL>, <&cru ARMCLKB>,
1138 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1140 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1142 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1143 <&cru PCLK_PERILP0>,
1144 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
1145 assigned-clock-rates =
1146 <400000000>, <200000000>,
1147 <400000000>, <200000000>,
1148 <816000000>, <816000000>,
1149 <594000000>, <800000000>,
1151 <150000000>, <75000000>,
1153 <100000000>, <100000000>,
1155 <100000000>, <50000000>;
1158 grf: syscon@ff770000 {
1159 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
1160 reg = <0x0 0xff770000 0x0 0x10000>;
1161 #address-cells = <1>;
1164 u2phy0: usb2-phy@e450 {
1165 compatible = "rockchip,rk3399-usb2phy";
1166 reg = <0xe450 0x10>;
1167 clocks = <&cru SCLK_USB2PHY0_REF>;
1168 clock-names = "phyclk";
1170 clock-output-names = "clk_usbphy0_480m";
1171 status = "disabled";
1173 u2phy0_otg: otg-port {
1175 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
1176 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1177 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
1178 interrupt-names = "otg-bvalid", "otg-id",
1180 status = "disabled";
1183 u2phy0_host: host-port {
1185 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
1186 interrupt-names = "linestate";
1187 status = "disabled";
1191 u2phy1: usb2-phy@e460 {
1192 compatible = "rockchip,rk3399-usb2phy";
1193 reg = <0xe460 0x10>;
1194 clocks = <&cru SCLK_USB2PHY1_REF>;
1195 clock-names = "phyclk";
1197 clock-output-names = "clk_usbphy1_480m";
1198 status = "disabled";
1200 u2phy1_host: host-port {
1202 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1203 interrupt-names = "linestate";
1204 status = "disabled";
1209 tcphy0: phy@ff7c0000 {
1210 compatible = "rockchip,rk3399-typec-phy";
1211 reg = <0x0 0xff7c0000 0x0 0x40000>;
1212 rockchip,grf = <&grf>;
1214 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1215 <&cru SCLK_UPHY0_TCPDPHY_REF>;
1216 clock-names = "tcpdcore", "tcpdphy-ref";
1217 resets = <&cru SRST_UPHY0>,
1218 <&cru SRST_UPHY0_PIPE_L00>,
1219 <&cru SRST_P_UPHY0_TCPHY>;
1220 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1221 rockchip,typec-conn-dir = <0xe580 0 16>;
1222 rockchip,usb3tousb2-en = <0xe580 3 19>;
1223 rockchip,external-psm = <0xe588 14 30>;
1224 rockchip,pipe-status = <0xe5c0 0 0>;
1225 rockchip,uphy-dp-sel = <0x6268 19 19>;
1226 status = "disabled";
1229 tcphy1: phy@ff800000 {
1230 compatible = "rockchip,rk3399-typec-phy";
1231 reg = <0x0 0xff800000 0x0 0x40000>;
1232 rockchip,grf = <&grf>;
1234 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1235 <&cru SCLK_UPHY1_TCPDPHY_REF>;
1236 clock-names = "tcpdcore", "tcpdphy-ref";
1237 resets = <&cru SRST_UPHY1>,
1238 <&cru SRST_UPHY1_PIPE_L00>,
1239 <&cru SRST_P_UPHY1_TCPHY>;
1240 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1241 rockchip,typec-conn-dir = <0xe58c 0 16>;
1242 rockchip,usb3tousb2-en = <0xe58c 3 19>;
1243 rockchip,external-psm = <0xe594 14 30>;
1244 rockchip,pipe-status = <0xe5c0 16 16>;
1245 rockchip,uphy-dp-sel = <0x6268 3 19>;
1246 status = "disabled";
1250 compatible = "snps,dw-wdt";
1251 reg = <0x0 0xff840000 0x0 0x100>;
1252 clocks = <&cru PCLK_WDT>;
1253 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1256 rktimer: rktimer@ff850000 {
1257 compatible = "rockchip,rk3399-timer";
1258 reg = <0x0 0xff850000 0x0 0x1000>;
1259 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1260 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1261 clock-names = "pclk", "timer";
1264 spdif: spdif@ff870000 {
1265 compatible = "rockchip,rk3399-spdif";
1266 reg = <0x0 0xff870000 0x0 0x1000>;
1267 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
1268 dmas = <&dmac_bus 7>;
1270 clock-names = "mclk", "hclk";
1271 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1272 pinctrl-names = "default";
1273 pinctrl-0 = <&spdif_bus>;
1274 status = "disabled";
1277 i2s0: i2s@ff880000 {
1278 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1279 reg = <0x0 0xff880000 0x0 0x1000>;
1280 rockchip,grf = <&grf>;
1281 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1282 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1283 dma-names = "tx", "rx";
1284 clock-names = "i2s_clk", "i2s_hclk";
1285 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1286 pinctrl-names = "default";
1287 pinctrl-0 = <&i2s0_8ch_bus>;
1288 status = "disabled";
1291 i2s1: i2s@ff890000 {
1292 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1293 reg = <0x0 0xff890000 0x0 0x1000>;
1294 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1295 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1296 dma-names = "tx", "rx";
1297 clock-names = "i2s_clk", "i2s_hclk";
1298 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1299 pinctrl-names = "default";
1300 pinctrl-0 = <&i2s1_2ch_bus>;
1301 status = "disabled";
1304 i2s2: i2s@ff8a0000 {
1305 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1306 reg = <0x0 0xff8a0000 0x0 0x1000>;
1307 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1308 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1309 dma-names = "tx", "rx";
1310 clock-names = "i2s_clk", "i2s_hclk";
1311 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1312 status = "disabled";
1316 compatible = "arm,malit860",
1321 reg = <0x0 0xff9a0000 0x0 0x10000>;
1323 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
1324 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
1325 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1326 interrupt-names = "GPU", "JOB", "MMU";
1328 clocks = <&cru ACLK_GPU>;
1329 clock-names = "clk_mali";
1330 #cooling-cells = <2>; /* min followed by max */
1331 operating-points-v2 = <&gpu_opp_table>;
1332 power-domains = <&power RK3399_PD_GPU>;
1333 power-off-delay-ms = <200>;
1334 status = "disabled";
1337 compatible = "arm,mali-simple-power-model";
1340 static-power = <300>;
1341 dynamic-power = <1780>;
1342 ts = <32000 4700 (-80) 2>;
1343 thermal-zone = "gpu-thermal";
1347 gpu_opp_table: gpu_opp_table {
1348 compatible = "operating-points-v2";
1352 opp-hz = /bits/ 64 <200000000>;
1353 opp-microvolt = <900000>;
1356 opp-hz = /bits/ 64 <300000000>;
1357 opp-microvolt = <900000>;
1360 opp-hz = /bits/ 64 <400000000>;
1361 opp-microvolt = <900000>;
1366 vopl: vop@ff8f0000 {
1367 compatible = "rockchip,rk3399-vop-lit";
1368 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1369 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
1370 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1371 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1372 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1373 reset-names = "axi", "ahb", "dclk";
1374 power-domains = <&power RK3399_PD_VOPL>;
1375 iommus = <&vopl_mmu>;
1376 status = "disabled";
1379 #address-cells = <1>;
1382 vopl_out_mipi: endpoint@0 {
1384 remote-endpoint = <&mipi_in_vopl>;
1387 vopl_out_edp: endpoint@1 {
1389 remote-endpoint = <&edp_in_vopl>;
1392 vopl_out_hdmi: endpoint@2 {
1394 remote-endpoint = <&hdmi_in_vopl>;
1399 vopl_mmu: iommu@ff8f3f00 {
1400 compatible = "rockchip,iommu";
1401 reg = <0x0 0xff8f3f00 0x0 0x100>;
1402 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
1403 interrupt-names = "vopl_mmu";
1405 status = "disabled";
1408 vopb: vop@ff900000 {
1409 compatible = "rockchip,rk3399-vop-big";
1410 reg = <0x0 0xff900000 0x0 0x3efc>;
1411 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1412 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1413 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1414 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1415 reset-names = "axi", "ahb", "dclk";
1416 power-domains = <&power RK3399_PD_VOPB>;
1417 iommus = <&vopb_mmu>;
1418 status = "disabled";
1421 #address-cells = <1>;
1424 vopb_out_edp: endpoint@0 {
1426 remote-endpoint = <&edp_in_vopb>;
1429 vopb_out_mipi: endpoint@1 {
1431 remote-endpoint = <&mipi_in_vopb>;
1434 vopb_out_hdmi: endpoint@2 {
1436 remote-endpoint = <&hdmi_in_vopb>;
1441 vopb_mmu: iommu@ff903f00 {
1442 compatible = "rockchip,iommu";
1443 reg = <0x0 0xff903f00 0x0 0x100>;
1444 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1445 interrupt-names = "vopb_mmu";
1447 status = "disabled";
1450 hdmi: hdmi@ff940000 {
1451 compatible = "rockchip,rk3399-dw-hdmi";
1452 reg = <0x0 0xff940000 0x0 0x20000>;
1454 rockchip,grf = <&grf>;
1455 power-domains = <&power RK3399_PD_HDCP>;
1456 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1457 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_SFR>, <&cru SCLK_HDMI_SFR>, <&cru PCLK_EDP_CTRL>;
1458 clock-names = "iahb", "isfr", "vpll", "grf";
1459 status = "disabled";
1463 #address-cells = <1>;
1465 hdmi_in_vopb: endpoint@0 {
1467 remote-endpoint = <&vopb_out_hdmi>;
1469 hdmi_in_vopl: endpoint@1 {
1471 remote-endpoint = <&vopl_out_hdmi>;
1477 mipi_dsi: mipi@ff960000 {
1478 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1479 reg = <0x0 0xff960000 0x0 0x8000>;
1480 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1481 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
1482 <&cru SCLK_DPHY_TX0_CFG>;
1483 clock-names = "ref", "pclk", "phy_cfg";
1484 power-domains = <&power RK3399_PD_VIO>;
1485 rockchip,grf = <&grf>;
1486 #address-cells = <1>;
1488 status = "disabled";
1491 #address-cells = <1>;
1496 #address-cells = <1>;
1499 mipi_in_vopb: endpoint@0 {
1501 remote-endpoint = <&vopb_out_mipi>;
1503 mipi_in_vopl: endpoint@1 {
1505 remote-endpoint = <&vopl_out_mipi>;
1512 compatible = "rockchip,rk3399-edp";
1513 reg = <0x0 0xff970000 0x0 0x8000>;
1514 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1515 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1516 clock-names = "dp", "pclk";
1517 resets = <&cru SRST_P_EDP_CTRL>;
1519 rockchip,grf = <&grf>;
1520 status = "disabled";
1521 pinctrl-names = "default";
1522 pinctrl-0 = <&edp_hpd>;
1525 #address-cells = <1>;
1530 #address-cells = <1>;
1533 edp_in_vopb: endpoint@0 {
1535 remote-endpoint = <&vopb_out_edp>;
1538 edp_in_vopl: endpoint@1 {
1540 remote-endpoint = <&vopl_out_edp>;
1546 display_subsystem: display-subsystem {
1547 compatible = "rockchip,display-subsystem";
1548 ports = <&vopl_out>, <&vopb_out>;
1549 status = "disabled";
1553 compatible = "rockchip,rk3399-pinctrl";
1554 rockchip,grf = <&grf>;
1555 rockchip,pmu = <&pmugrf>;
1556 #address-cells = <0x2>;
1557 #size-cells = <0x2>;
1560 gpio0: gpio0@ff720000 {
1561 compatible = "rockchip,gpio-bank";
1562 reg = <0x0 0xff720000 0x0 0x100>;
1563 clocks = <&pmucru PCLK_GPIO0_PMU>;
1564 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1567 #gpio-cells = <0x2>;
1569 interrupt-controller;
1570 #interrupt-cells = <0x2>;
1573 gpio1: gpio1@ff730000 {
1574 compatible = "rockchip,gpio-bank";
1575 reg = <0x0 0xff730000 0x0 0x100>;
1576 clocks = <&pmucru PCLK_GPIO1_PMU>;
1577 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1580 #gpio-cells = <0x2>;
1582 interrupt-controller;
1583 #interrupt-cells = <0x2>;
1586 gpio2: gpio2@ff780000 {
1587 compatible = "rockchip,gpio-bank";
1588 reg = <0x0 0xff780000 0x0 0x100>;
1589 clocks = <&cru PCLK_GPIO2>;
1590 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1593 #gpio-cells = <0x2>;
1595 interrupt-controller;
1596 #interrupt-cells = <0x2>;
1599 gpio3: gpio3@ff788000 {
1600 compatible = "rockchip,gpio-bank";
1601 reg = <0x0 0xff788000 0x0 0x100>;
1602 clocks = <&cru PCLK_GPIO3>;
1603 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1606 #gpio-cells = <0x2>;
1608 interrupt-controller;
1609 #interrupt-cells = <0x2>;
1612 gpio4: gpio4@ff790000 {
1613 compatible = "rockchip,gpio-bank";
1614 reg = <0x0 0xff790000 0x0 0x100>;
1615 clocks = <&cru PCLK_GPIO4>;
1616 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1619 #gpio-cells = <0x2>;
1621 interrupt-controller;
1622 #interrupt-cells = <0x2>;
1625 pcfg_pull_up: pcfg-pull-up {
1629 pcfg_pull_down: pcfg-pull-down {
1633 pcfg_pull_none: pcfg-pull-none {
1637 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1639 drive-strength = <12>;
1642 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1644 drive-strength = <8>;
1647 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1649 drive-strength = <4>;
1652 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1654 drive-strength = <2>;
1657 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
1659 drive-strength = <12>;
1662 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
1664 drive-strength = <13>;
1668 emmc_pwr: emmc-pwr {
1670 <0 5 RK_FUNC_1 &pcfg_pull_up>;
1675 rgmii_pins: rgmii-pins {
1678 <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
1680 <3 14 RK_FUNC_1 &pcfg_pull_none>,
1682 <3 13 RK_FUNC_1 &pcfg_pull_none>,
1684 <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1686 <3 11 RK_FUNC_1 &pcfg_pull_none>,
1688 <3 9 RK_FUNC_1 &pcfg_pull_none>,
1690 <3 8 RK_FUNC_1 &pcfg_pull_none>,
1692 <3 7 RK_FUNC_1 &pcfg_pull_none>,
1694 <3 6 RK_FUNC_1 &pcfg_pull_none>,
1696 <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1698 <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
1700 <3 3 RK_FUNC_1 &pcfg_pull_none>,
1702 <3 2 RK_FUNC_1 &pcfg_pull_none>,
1704 <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
1706 <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
1709 rmii_pins: rmii-pins {
1712 <3 13 RK_FUNC_1 &pcfg_pull_none>,
1714 <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1716 <3 11 RK_FUNC_1 &pcfg_pull_none>,
1718 <3 10 RK_FUNC_1 &pcfg_pull_none>,
1720 <3 9 RK_FUNC_1 &pcfg_pull_none>,
1722 <3 8 RK_FUNC_1 &pcfg_pull_none>,
1724 <3 7 RK_FUNC_1 &pcfg_pull_none>,
1726 <3 6 RK_FUNC_1 &pcfg_pull_none>,
1728 <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1730 <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
1735 i2c0_xfer: i2c0-xfer {
1737 <1 15 RK_FUNC_2 &pcfg_pull_none>,
1738 <1 16 RK_FUNC_2 &pcfg_pull_none>;
1743 i2c1_xfer: i2c1-xfer {
1745 <4 2 RK_FUNC_1 &pcfg_pull_none>,
1746 <4 1 RK_FUNC_1 &pcfg_pull_none>;
1751 i2c2_xfer: i2c2-xfer {
1753 <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1754 <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
1759 i2c3_xfer: i2c3-xfer {
1761 <4 17 RK_FUNC_1 &pcfg_pull_none>,
1762 <4 16 RK_FUNC_1 &pcfg_pull_none>;
1765 i2c3_gpio: i2c3_gpio {
1767 <4 17 RK_FUNC_GPIO &pcfg_pull_none>,
1768 <4 16 RK_FUNC_GPIO &pcfg_pull_none>;
1774 i2c4_xfer: i2c4-xfer {
1776 <1 12 RK_FUNC_1 &pcfg_pull_none>,
1777 <1 11 RK_FUNC_1 &pcfg_pull_none>;
1782 i2c5_xfer: i2c5-xfer {
1784 <3 11 RK_FUNC_2 &pcfg_pull_none>,
1785 <3 10 RK_FUNC_2 &pcfg_pull_none>;
1790 i2c6_xfer: i2c6-xfer {
1792 <2 10 RK_FUNC_2 &pcfg_pull_none>,
1793 <2 9 RK_FUNC_2 &pcfg_pull_none>;
1798 i2c7_xfer: i2c7-xfer {
1800 <2 8 RK_FUNC_2 &pcfg_pull_none>,
1801 <2 7 RK_FUNC_2 &pcfg_pull_none>;
1806 i2c8_xfer: i2c8-xfer {
1808 <1 21 RK_FUNC_1 &pcfg_pull_none>,
1809 <1 20 RK_FUNC_1 &pcfg_pull_none>;
1814 i2s0_8ch_bus: i2s0-8ch-bus {
1816 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1817 <3 25 RK_FUNC_1 &pcfg_pull_none>,
1818 <3 26 RK_FUNC_1 &pcfg_pull_none>,
1819 <3 27 RK_FUNC_1 &pcfg_pull_none>,
1820 <3 28 RK_FUNC_1 &pcfg_pull_none>,
1821 <3 29 RK_FUNC_1 &pcfg_pull_none>,
1822 <3 30 RK_FUNC_1 &pcfg_pull_none>,
1823 <3 31 RK_FUNC_1 &pcfg_pull_none>,
1824 <4 0 RK_FUNC_1 &pcfg_pull_none>;
1829 i2s1_2ch_bus: i2s1-2ch-bus {
1831 <4 3 RK_FUNC_1 &pcfg_pull_none>,
1832 <4 4 RK_FUNC_1 &pcfg_pull_none>,
1833 <4 5 RK_FUNC_1 &pcfg_pull_none>,
1834 <4 6 RK_FUNC_1 &pcfg_pull_none>,
1835 <4 7 RK_FUNC_1 &pcfg_pull_none>;
1840 sdio0_bus1: sdio0-bus1 {
1842 <2 20 RK_FUNC_1 &pcfg_pull_up>;
1845 sdio0_bus4: sdio0-bus4 {
1847 <2 20 RK_FUNC_1 &pcfg_pull_up>,
1848 <2 21 RK_FUNC_1 &pcfg_pull_up>,
1849 <2 22 RK_FUNC_1 &pcfg_pull_up>,
1850 <2 23 RK_FUNC_1 &pcfg_pull_up>;
1853 sdio0_cmd: sdio0-cmd {
1855 <2 24 RK_FUNC_1 &pcfg_pull_up>;
1858 sdio0_clk: sdio0-clk {
1860 <2 25 RK_FUNC_1 &pcfg_pull_none>;
1863 sdio0_cd: sdio0-cd {
1865 <2 26 RK_FUNC_1 &pcfg_pull_up>;
1868 sdio0_pwr: sdio0-pwr {
1870 <2 27 RK_FUNC_1 &pcfg_pull_up>;
1873 sdio0_bkpwr: sdio0-bkpwr {
1875 <2 28 RK_FUNC_1 &pcfg_pull_up>;
1878 sdio0_wp: sdio0-wp {
1880 <0 3 RK_FUNC_1 &pcfg_pull_up>;
1883 sdio0_int: sdio0-int {
1885 <0 4 RK_FUNC_1 &pcfg_pull_up>;
1890 sdmmc_bus1: sdmmc-bus1 {
1892 <4 8 RK_FUNC_1 &pcfg_pull_up>;
1895 sdmmc_bus4: sdmmc-bus4 {
1897 <4 8 RK_FUNC_1 &pcfg_pull_up>,
1898 <4 9 RK_FUNC_1 &pcfg_pull_up>,
1899 <4 10 RK_FUNC_1 &pcfg_pull_up>,
1900 <4 11 RK_FUNC_1 &pcfg_pull_up>;
1903 sdmmc_clk: sdmmc-clk {
1905 <4 12 RK_FUNC_1 &pcfg_pull_none>;
1908 sdmmc_cmd: sdmmc-cmd {
1910 <4 13 RK_FUNC_1 &pcfg_pull_up>;
1913 sdmmc_cd: sdmcc-cd {
1915 <0 7 RK_FUNC_1 &pcfg_pull_up>;
1918 sdmmc_wp: sdmmc-wp {
1920 <0 8 RK_FUNC_1 &pcfg_pull_up>;
1925 spdif_bus: spdif-bus {
1927 <4 21 RK_FUNC_1 &pcfg_pull_none>;
1930 spdif_bus_1: spdif-bus-1 {
1932 <3 16 RK_FUNC_3 &pcfg_pull_none>;
1937 spi0_clk: spi0-clk {
1939 <3 6 RK_FUNC_2 &pcfg_pull_up>;
1941 spi0_cs0: spi0-cs0 {
1943 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1945 spi0_cs1: spi0-cs1 {
1947 <3 8 RK_FUNC_2 &pcfg_pull_up>;
1951 <3 5 RK_FUNC_2 &pcfg_pull_up>;
1955 <3 4 RK_FUNC_2 &pcfg_pull_up>;
1960 spi1_clk: spi1-clk {
1962 <1 9 RK_FUNC_2 &pcfg_pull_up>;
1964 spi1_cs0: spi1-cs0 {
1966 <1 10 RK_FUNC_2 &pcfg_pull_up>;
1970 <1 7 RK_FUNC_2 &pcfg_pull_up>;
1974 <1 8 RK_FUNC_2 &pcfg_pull_up>;
1979 spi2_clk: spi2-clk {
1981 <2 11 RK_FUNC_1 &pcfg_pull_up>;
1983 spi2_cs0: spi2-cs0 {
1985 <2 12 RK_FUNC_1 &pcfg_pull_up>;
1989 <2 9 RK_FUNC_1 &pcfg_pull_up>;
1993 <2 10 RK_FUNC_1 &pcfg_pull_up>;
1998 spi3_clk: spi3-clk {
2000 <1 17 RK_FUNC_1 &pcfg_pull_up>;
2002 spi3_cs0: spi3-cs0 {
2004 <1 18 RK_FUNC_1 &pcfg_pull_up>;
2008 <1 15 RK_FUNC_1 &pcfg_pull_up>;
2012 <1 16 RK_FUNC_1 &pcfg_pull_up>;
2017 spi4_clk: spi4-clk {
2019 <3 2 RK_FUNC_2 &pcfg_pull_up>;
2021 spi4_cs0: spi4-cs0 {
2023 <3 3 RK_FUNC_2 &pcfg_pull_up>;
2027 <3 0 RK_FUNC_2 &pcfg_pull_up>;
2031 <3 1 RK_FUNC_2 &pcfg_pull_up>;
2036 spi5_clk: spi5-clk {
2038 <2 22 RK_FUNC_2 &pcfg_pull_up>;
2040 spi5_cs0: spi5-cs0 {
2042 <2 23 RK_FUNC_2 &pcfg_pull_up>;
2046 <2 20 RK_FUNC_2 &pcfg_pull_up>;
2050 <2 21 RK_FUNC_2 &pcfg_pull_up>;
2055 otp_gpio: otp-gpio {
2056 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
2060 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
2065 uart0_xfer: uart0-xfer {
2067 <2 16 RK_FUNC_1 &pcfg_pull_up>,
2068 <2 17 RK_FUNC_1 &pcfg_pull_none>;
2071 uart0_cts: uart0-cts {
2073 <2 18 RK_FUNC_1 &pcfg_pull_none>;
2076 uart0_rts: uart0-rts {
2078 <2 19 RK_FUNC_1 &pcfg_pull_none>;
2083 uart1_xfer: uart1-xfer {
2085 <3 12 RK_FUNC_2 &pcfg_pull_up>,
2086 <3 13 RK_FUNC_2 &pcfg_pull_none>;
2091 uart2a_xfer: uart2a-xfer {
2093 <4 8 RK_FUNC_2 &pcfg_pull_up>,
2094 <4 9 RK_FUNC_2 &pcfg_pull_none>;
2099 uart2b_xfer: uart2b-xfer {
2101 <4 16 RK_FUNC_2 &pcfg_pull_up>,
2102 <4 17 RK_FUNC_2 &pcfg_pull_none>;
2107 uart2c_xfer: uart2c-xfer {
2109 <4 19 RK_FUNC_1 &pcfg_pull_up>,
2110 <4 20 RK_FUNC_1 &pcfg_pull_none>;
2115 uart3_xfer: uart3-xfer {
2117 <3 14 RK_FUNC_2 &pcfg_pull_up>,
2118 <3 15 RK_FUNC_2 &pcfg_pull_none>;
2121 uart3_cts: uart3-cts {
2123 <3 18 RK_FUNC_2 &pcfg_pull_none>;
2126 uart3_rts: uart3-rts {
2128 <3 19 RK_FUNC_2 &pcfg_pull_none>;
2133 uart4_xfer: uart4-xfer {
2135 <1 7 RK_FUNC_1 &pcfg_pull_up>,
2136 <1 8 RK_FUNC_1 &pcfg_pull_none>;
2141 uarthdcp_xfer: uarthdcp-xfer {
2143 <4 21 RK_FUNC_2 &pcfg_pull_up>,
2144 <4 22 RK_FUNC_2 &pcfg_pull_none>;
2149 pwm0_pin: pwm0-pin {
2151 <4 18 RK_FUNC_1 &pcfg_pull_none>;
2154 vop0_pwm_pin: vop0-pwm-pin {
2156 <4 18 RK_FUNC_2 &pcfg_pull_none>;
2161 pwm1_pin: pwm1-pin {
2163 <4 22 RK_FUNC_1 &pcfg_pull_none>;
2166 vop1_pwm_pin: vop1-pwm-pin {
2168 <4 18 RK_FUNC_3 &pcfg_pull_none>;
2173 pwm2_pin: pwm2-pin {
2175 <1 19 RK_FUNC_1 &pcfg_pull_none>;
2180 pwm3a_pin: pwm3a-pin {
2182 <0 6 RK_FUNC_1 &pcfg_pull_none>;
2187 pwm3b_pin: pwm3b-pin {
2189 <1 14 RK_FUNC_1 &pcfg_pull_none>;
2196 <4 23 RK_FUNC_2 &pcfg_pull_none>;
2201 hdmi_i2c_xfer: hdmi-i2c-xfer {
2203 <4 17 RK_FUNC_3 &pcfg_pull_none>,
2204 <4 16 RK_FUNC_3 &pcfg_pull_none>;
2207 hdmi_cec: hdmi-cec {
2209 <4 23 RK_FUNC_1 &pcfg_pull_none>;
2214 pcie_clkreqn: pci-clkreqn {
2216 <2 26 RK_FUNC_2 &pcfg_pull_none>;
2219 pcie_clkreqnb: pci-clkreqnb {
2221 <4 24 RK_FUNC_1 &pcfg_pull_none>;