arch/arm64/boot/dts/rockchip/rk3399.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3399-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/interrupt-controller/irq.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/power/rk3399-power.h>
  49 #include <dt-bindings/soc/rockchip_boot-mode.h>
  50 #include <dt-bindings/thermal/thermal.h>
  51
  52 / {
  53         compatible = "rockchip,rk3399";
  54
  55         interrupt-parent = <&gic>;
  56         #address-cells = <2>;
  57         #size-cells = <2>;
  58
  59         aliases {
  60                 i2c0 = &i2c0;
  61                 i2c1 = &i2c1;
  62                 i2c2 = &i2c2;
  63                 i2c3 = &i2c3;
  64                 i2c4 = &i2c4;
  65                 i2c5 = &i2c5;
  66                 i2c6 = &i2c6;
  67                 i2c7 = &i2c7;
  68                 i2c8 = &i2c8;
  69                 serial0 = &uart0;
  70                 serial1 = &uart1;
  71                 serial2 = &uart2;
  72                 serial3 = &uart3;
  73                 serial4 = &uart4;
  74         };
  75
  76         psci {
  77                 compatible = "arm,psci-1.0";
  78                 method = "smc";
  79         };
  80
  81         cpus {
  82                 #address-cells = <2>;
  83                 #size-cells = <0>;
  84
  85                 cpu-map {
  86                         cluster0 {
  87                                 core0 {
  88                                         cpu = <&cpu_l0>;
  89                                 };
  90                                 core1 {
  91                                         cpu = <&cpu_l1>;
  92                                 };
  93                                 core2 {
  94                                         cpu = <&cpu_l2>;
  95                                 };
  96                                 core3 {
  97                                         cpu = <&cpu_l3>;
  98                                 };
  99                         };
 100
 101                         cluster1 {
 102                                 core0 {
 103                                         cpu = <&cpu_b0>;
 104                                 };
 105                                 core1 {
 106                                         cpu = <&cpu_b1>;
 107                                 };
 108                         };
 109                 };
 110
 111                 cpu_l0: cpu@0 {
 112                         device_type = "cpu";
 113                         compatible = "arm,cortex-a53", "arm,armv8";
 114                         reg = <0x0 0x0>;
 115                         enable-method = "psci";
 116                         #cooling-cells = <2>; /* min followed by max */
 117                         dynamic-power-coefficient = <121>;
 118                         clocks = <&cru ARMCLKL>;
 119                         cpu-idle-states = <&cpu_sleep>;
 120                         operating-points-v2 = <&cluster0_opp>;
 121                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
 122                 };
 123
 124                 cpu_l1: cpu@1 {
 125                         device_type = "cpu";
 126                         compatible = "arm,cortex-a53", "arm,armv8";
 127                         reg = <0x0 0x1>;
 128                         enable-method = "psci";
 129                         clocks = <&cru ARMCLKL>;
 130                         cpu-idle-states = <&cpu_sleep>;
 131                         operating-points-v2 = <&cluster0_opp>;
 132                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
 133                 };
 134
 135                 cpu_l2: cpu@2 {
 136                         device_type = "cpu";
 137                         compatible = "arm,cortex-a53", "arm,armv8";
 138                         reg = <0x0 0x2>;
 139                         enable-method = "psci";
 140                         clocks = <&cru ARMCLKL>;
 141                         cpu-idle-states = <&cpu_sleep>;
 142                         operating-points-v2 = <&cluster0_opp>;
 143                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
 144                 };
 145
 146                 cpu_l3: cpu@3 {
 147                         device_type = "cpu";
 148                         compatible = "arm,cortex-a53", "arm,armv8";
 149                         reg = <0x0 0x3>;
 150                         enable-method = "psci";
 151                         clocks = <&cru ARMCLKL>;
 152                         cpu-idle-states = <&cpu_sleep>;
 153                         operating-points-v2 = <&cluster0_opp>;
 154                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
 155                 };
 156
 157                 cpu_b0: cpu@100 {
 158                         device_type = "cpu";
 159                         compatible = "arm,cortex-a72", "arm,armv8";
 160                         reg = <0x0 0x100>;
 161                         enable-method = "psci";
 162                         #cooling-cells = <2>; /* min followed by max */
 163                         dynamic-power-coefficient = <1068>;
 164                         clocks = <&cru ARMCLKB>;
 165                         cpu-idle-states = <&cpu_sleep>;
 166                         operating-points-v2 = <&cluster1_opp>;
 167                         sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>;
 168                 };
 169
 170                 cpu_b1: cpu@101 {
 171                         device_type = "cpu";
 172                         compatible = "arm,cortex-a72", "arm,armv8";
 173                         reg = <0x0 0x101>;
 174                         enable-method = "psci";
 175                         clocks = <&cru ARMCLKB>;
 176                         cpu-idle-states = <&cpu_sleep>;
 177                         operating-points-v2 = <&cluster1_opp>;
 178                         sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>;
 179                 };
 180
 181                 idle-states {
 182                         entry-method = "psci";
 183                         cpu_sleep: cpu-sleep-0 {
 184                                 compatible = "arm,idle-state";
 185                                 local-timer-stop;
 186                                 arm,psci-suspend-param = <0x0010000>;
 187                                 entry-latency-us = <350>;
 188                                 exit-latency-us = <600>;
 189                                 min-residency-us = <1150>;
 190                         };
 191                 };
 192
 193                 /include/ "rk3399-sched-energy.dtsi"
 194
 195         };
 196
 197         cluster0_opp: opp_table0 {
 198                 compatible = "operating-points-v2";
 199                 opp-shared;
 200
 201                 opp00 {
 202                         opp-hz = /bits/ 64 <408000000>;
 203                         opp-microvolt = <800000>;
 204                         clock-latency-ns = <40000>;
 205                 };
 206                 opp01 {
 207                         opp-hz = /bits/ 64 <600000000>;
 208                         opp-microvolt = <800000>;
 209                 };
 210                 opp02 {
 211                         opp-hz = /bits/ 64 <816000000>;
 212                         opp-microvolt = <800000>;
 213                 };
 214                 opp03 {
 215                         opp-hz = /bits/ 64 <1008000000>;
 216                         opp-microvolt = <875000>;
 217                 };
 218                 opp04 {
 219                         opp-hz = /bits/ 64 <1200000000>;
 220                         opp-microvolt = <925000>;
 221                 };
 222                 opp05 {
 223                         opp-hz = /bits/ 64 <1416000000>;
 224                         opp-microvolt = <1025000>;
 225                 };
 226         };
 227
 228         cluster1_opp: opp_table1 {
 229                 compatible = "operating-points-v2";
 230                 opp-shared;
 231
 232                 opp00 {
 233                         opp-hz = /bits/ 64 <408000000>;
 234                         opp-microvolt = <800000>;
 235                         clock-latency-ns = <40000>;
 236                 };
 237                 opp01 {
 238                         opp-hz = /bits/ 64 <600000000>;
 239                         opp-microvolt = <800000>;
 240                 };
 241                 opp02 {
 242                         opp-hz = /bits/ 64 <816000000>;
 243                         opp-microvolt = <800000>;
 244                 };
 245                 opp03 {
 246                         opp-hz = /bits/ 64 <1008000000>;
 247                         opp-microvolt = <850000>;
 248                 };
 249                 opp04 {
 250                         opp-hz = /bits/ 64 <1200000000>;
 251                         opp-microvolt = <925000>;
 252                 };
 253         };
 254
 255         timer {
 256                 compatible = "arm,armv8-timer";
 257                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
 258                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
 259                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
 260                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
 261         };
 262
 263         arm-pmu {
 264                 compatible = "arm,armv8-pmuv3";
 265                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
 266         };
 267
 268         xin24m: xin24m {
 269                 compatible = "fixed-clock";
 270                 #clock-cells = <0>;
 271                 clock-frequency = <24000000>;
 272                 clock-output-names = "xin24m";
 273         };
 274
 275         amba {
 276                 compatible = "arm,amba-bus";
 277                 #address-cells = <2>;
 278                 #size-cells = <2>;
 279                 ranges;
 280
 281                 dmac_bus: dma-controller@ff6d0000 {
 282                         compatible = "arm,pl330", "arm,primecell";
 283                         reg = <0x0 0xff6d0000 0x0 0x4000>;
 284                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 285                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 286                         #dma-cells = <1>;
 287                         clocks = <&cru ACLK_DMAC0_PERILP>;
 288                         clock-names = "apb_pclk";
 289                         peripherals-req-type-burst;
 290                 };
 291
 292                 dmac_peri: dma-controller@ff6e0000 {
 293                         compatible = "arm,pl330", "arm,primecell";
 294                         reg = <0x0 0xff6e0000 0x0 0x4000>;
 295                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 296                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 297                         #dma-cells = <1>;
 298                         clocks = <&cru ACLK_DMAC1_PERILP>;
 299                         clock-names = "apb_pclk";
 300                         peripherals-req-type-burst;
 301                 };
 302         };
 303
 304         gmac: eth@fe300000 {
 305                 compatible = "rockchip,rk3399-gmac";
 306                 reg = <0x0 0xfe300000 0x0 0x10000>;
 307                 rockchip,grf = <&grf>;
 308                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 309                 interrupt-names = "macirq";
 310                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
 311                          <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
 312                          <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
 313                          <&cru PCLK_GMAC>;
 314                 clock-names = "stmmaceth", "mac_clk_rx",
 315                               "mac_clk_tx", "clk_mac_ref",
 316                               "clk_mac_refout", "aclk_mac",
 317                               "pclk_mac";
 318                 resets = <&cru SRST_A_GMAC>;
 319                 reset-names = "stmmaceth";
 320                 status = "disabled";
 321         };
 322
 323         emmc_phy: phy {
 324                 compatible = "rockchip,rk3399-emmc-phy";
 325                 reg-offset = <0xf780>;
 326                 #phy-cells = <0>;
 327                 rockchip,grf = <&grf>;
 328                 ctrl-base = <0xfe330000>;
 329                 status = "disabled";
 330         };
 331
 332         sdio0: dwmmc@fe310000 {
 333                 compatible = "rockchip,rk3399-dw-mshc",
 334                              "rockchip,rk3288-dw-mshc";
 335                 reg = <0x0 0xfe310000 0x0 0x4000>;
 336                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 337                 clock-freq-min-max = <400000 150000000>;
 338                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 339                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 340                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 341                 fifo-depth = <0x100>;
 342                 status = "disabled";
 343         };
 344
 345         sdmmc: dwmmc@fe320000 {
 346                 compatible = "rockchip,rk3399-dw-mshc",
 347                              "rockchip,rk3288-dw-mshc";
 348                 reg = <0x0 0xfe320000 0x0 0x4000>;
 349                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 350                 clock-freq-min-max = <400000 150000000>;
 351                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 352                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 353                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 354                 fifo-depth = <0x100>;
 355                 status = "disabled";
 356         };
 357
 358         sdhci: sdhci@fe330000 {
 359                 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
 360                 reg = <0x0 0xfe330000 0x0 0x10000>;
 361                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 362                 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
 363                 clock-names = "clk_xin", "clk_ahb";
 364                 assigned-clocks = <&cru SCLK_EMMC>;
 365                 assigned-clock-parents = <&cru PLL_CPLL>;
 366                 assigned-clock-rates = <200000000>;
 367                 phys = <&emmc_phy>;
 368                 phy-names = "phy_arasan";
 369                 status = "disabled";
 370         };
 371
 372         usb2phy: usb2phy {
 373                 compatible = "rockchip,rk3399-usb-phy";
 374                 rockchip,grf = <&grf>;
 375                 #address-cells = <1>;
 376                 #size-cells = <0>;
 377
 378                 usb2phy0: usb2-phy0 {
 379                         #phy-cells = <0>;
 380                         #clock-cells = <0>;
 381                         reg = <0xe458>;
 382                 };
 383
 384                 usb2phy1: usb2-phy1 {
 385                         #phy-cells = <0>;
 386                         #clock-cells = <0>;
 387                         reg = <0xe468>;
 388                 };
 389         };
 390
 391         usb_host0_ehci: usb@fe380000 {
 392                 compatible = "generic-ehci";
 393                 reg = <0x0 0xfe380000 0x0 0x20000>;
 394                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 395                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
 396                 clock-names = "hclk_host0", "hclk_host0_arb";
 397                 phys = <&usb2phy0>;
 398                 phy-names = "usb2_phy0";
 399                 status = "disabled";
 400         };
 401
 402         usb_host0_ohci: usb@fe3a0000 {
 403                 compatible = "generic-ohci";
 404                 reg = <0x0 0xfe3a0000 0x0 0x20000>;
 405                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 406                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
 407                 clock-names = "hclk_host0", "hclk_host0_arb";
 408                 status = "disabled";
 409         };
 410
 411         usb_host1_ehci: usb@fe3c0000 {
 412                 compatible = "generic-ehci";
 413                 reg = <0x0 0xfe3c0000 0x0 0x20000>;
 414                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 415                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
 416                 clock-names = "hclk_host1", "hclk_host1_arb";
 417                 phys = <&usb2phy1>;
 418                 phy-names = "usb2_phy1";
 419                 status = "disabled";
 420         };
 421
 422         usb_host1_ohci: usb@fe3e0000 {
 423                 compatible = "generic-ohci";
 424                 reg = <0x0 0xfe3e0000 0x0 0x20000>;
 425                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 426                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
 427                 clock-names = "hclk_host1", "hclk_host1_arb";
 428                 status = "disabled";
 429         };
 430
 431         usbdrd3_0: usb@fe800000 {
 432                 compatible = "rockchip,dwc3";
 433                 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
 434                          <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
 435                          <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
 436                 clock-names = "clk_usb3otg0_ref", "clk_usb3otg0_suspend",
 437                               "aclk_usb3otg0", "aclk_usb3_rksoc_axi_perf",
 438                               "aclk_usb3", "aclk_usb3_grf";
 439                 #address-cells = <2>;
 440                 #size-cells = <2>;
 441                 ranges;
 442                 status = "disabled";
 443                 usbdrd_dwc3_0: dwc3@fe800000 {
 444                         compatible = "snps,dwc3";
 445                         reg = <0x0 0xfe800000 0x0 0x100000>;
 446                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 447                         dr_mode = "otg";
 448                         snps,dis_enblslpm_quirk;
 449                         snps,phyif_utmi_16_bits;
 450                         snps,dis_u2_freeclk_exists_quirk;
 451                         snps,dis_del_phy_power_chg_quirk;
 452                         snps,xhci_slow_suspend_quirk;
 453                         status = "disabled";
 454                 };
 455         };
 456
 457         usbdrd3_1: usb@fe900000 {
 458                 compatible = "rockchip,dwc3";
 459                 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
 460                          <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
 461                          <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
 462                 clock-names = "clk_usb3otg1_ref", "clk_usb3otg1_suspend",
 463                               "aclk_usb3otg1", "aclk_usb3_rksoc_axi_perf",
 464                               "aclk_usb3", "aclk_usb3_grf";
 465                 #address-cells = <2>;
 466                 #size-cells = <2>;
 467                 ranges;
 468                 status = "disabled";
 469                 usbdrd_dwc3_1: dwc3@fe900000 {
 470                         compatible = "snps,dwc3";
 471                         reg = <0x0 0xfe900000 0x0 0x100000>;
 472                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 473                         dr_mode = "otg";
 474                         snps,dis_enblslpm_quirk;
 475                         snps,phyif_utmi_16_bits;
 476                         snps,dis_u2_freeclk_exists_quirk;
 477                         snps,dis_del_phy_power_chg_quirk;
 478                         snps,xhci_slow_suspend_quirk;
 479                         status = "disabled";
 480                 };
 481         };
 482
 483         gic: interrupt-controller@fee00000 {
 484                 compatible = "arm,gic-v3";
 485                 #interrupt-cells = <3>;
 486                 #address-cells = <2>;
 487                 #size-cells = <2>;
 488                 ranges;
 489                 interrupt-controller;
 490
 491                 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
 492                       <0x0 0xfef00000 0 0xc0000>, /* GICR */
 493                       <0x0 0xfff00000 0 0x10000>, /* GICC */
 494                       <0x0 0xfff10000 0 0x10000>, /* GICH */
 495                       <0x0 0xfff20000 0 0x10000>; /* GICV */
 496                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 497                 its: interrupt-controller@fee20000 {
 498                         compatible = "arm,gic-v3-its";
 499                         msi-controller;
 500                         reg = <0x0 0xfee20000 0x0 0x20000>;
 501                 };
 502         };
 503
 504         saradc: saradc@ff100000 {
 505                 compatible = "rockchip,rk3399-saradc";
 506                 reg = <0x0 0xff100000 0x0 0x100>;
 507                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 508                 #io-channel-cells = <1>;
 509                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 510                 clock-names = "saradc", "apb_pclk";
 511                 status = "disabled";
 512         };
 513
 514         i2c0: i2c@ff3c0000 {
 515                 compatible = "rockchip,rk3399-i2c";
 516                 reg = <0x0 0xff3c0000 0x0 0x1000>;
 517                 clocks =  <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
 518                 clock-names = "i2c", "pclk";
 519                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 520                 pinctrl-names = "default";
 521                 pinctrl-0 = <&i2c0_xfer>;
 522                 #address-cells = <1>;
 523                 #size-cells = <0>;
 524                 status = "disabled";
 525         };
 526
 527         i2c1: i2c@ff110000 {
 528                 compatible = "rockchip,rk3399-i2c";
 529                 reg = <0x0 0xff110000 0x0 0x1000>;
 530                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 531                 clock-names = "i2c", "pclk";
 532                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 533                 pinctrl-names = "default";
 534                 pinctrl-0 = <&i2c1_xfer>;
 535                 #address-cells = <1>;
 536                 #size-cells = <0>;
 537                 status = "disabled";
 538         };
 539
 540         i2c2: i2c@ff120000 {
 541                 compatible = "rockchip,rk3399-i2c";
 542                 reg = <0x0 0xff120000 0x0 0x1000>;
 543                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 544                 clock-names = "i2c", "pclk";
 545                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 546                 pinctrl-names = "default";
 547                 pinctrl-0 = <&i2c2_xfer>;
 548                 #address-cells = <1>;
 549                 #size-cells = <0>;
 550                 status = "disabled";
 551         };
 552
 553         i2c3: i2c@ff130000 {
 554                 compatible = "rockchip,rk3399-i2c";
 555                 reg = <0x0 0xff130000 0x0 0x1000>;
 556                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 557                 clock-names = "i2c", "pclk";
 558                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 559                 pinctrl-names = "default";
 560                 pinctrl-0 = <&i2c3_xfer>;
 561                 #address-cells = <1>;
 562                 #size-cells = <0>;
 563                 status = "disabled";
 564         };
 565
 566         i2c5: i2c@ff140000 {
 567                 compatible = "rockchip,rk3399-i2c";
 568                 reg = <0x0 0xff140000 0x0 0x1000>;
 569                 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
 570                 clock-names = "i2c", "pclk";
 571                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 572                 pinctrl-names = "default";
 573                 pinctrl-0 = <&i2c5_xfer>;
 574                 #address-cells = <1>;
 575                 #size-cells = <0>;
 576                 status = "disabled";
 577         };
 578
 579         i2c6: i2c@ff150000 {
 580                 compatible = "rockchip,rk3399-i2c";
 581                 reg = <0x0 0xff150000 0x0 0x1000>;
 582                 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
 583                 clock-names = "i2c", "pclk";
 584                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 585                 pinctrl-names = "default";
 586                 pinctrl-0 = <&i2c6_xfer>;
 587                 #address-cells = <1>;
 588                 #size-cells = <0>;
 589                 status = "disabled";
 590         };
 591
 592         i2c7: i2c@ff160000 {
 593                 compatible = "rockchip,rk3399-i2c";
 594                 reg = <0x0 0xff160000 0x0 0x1000>;
 595                 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
 596                 clock-names = "i2c", "pclk";
 597                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 598                 pinctrl-names = "default";
 599                 pinctrl-0 = <&i2c7_xfer>;
 600                 #address-cells = <1>;
 601                 #size-cells = <0>;
 602                 status = "disabled";
 603         };
 604
 605         uart0: serial@ff180000 {
 606                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 607                 reg = <0x0 0xff180000 0x0 0x100>;
 608                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 609                 clock-names = "baudclk", "apb_pclk";
 610                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 611                 reg-shift = <2>;
 612                 reg-io-width = <4>;
 613                 pinctrl-names = "default";
 614                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 615                 status = "disabled";
 616         };
 617
 618         uart1: serial@ff190000 {
 619                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 620                 reg = <0x0 0xff190000 0x0 0x100>;
 621                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 622                 clock-names = "baudclk", "apb_pclk";
 623                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 624                 reg-shift = <2>;
 625                 reg-io-width = <4>;
 626                 pinctrl-names = "default";
 627                 pinctrl-0 = <&uart1_xfer>;
 628                 status = "disabled";
 629         };
 630
 631         uart2: serial@ff1a0000 {
 632                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 633                 reg = <0x0 0xff1a0000 0x0 0x100>;
 634                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 635                 clock-names = "baudclk", "apb_pclk";
 636                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 637                 reg-shift = <2>;
 638                 reg-io-width = <4>;
 639                 pinctrl-names = "default";
 640                 pinctrl-0 = <&uart2c_xfer>;
 641                 status = "disabled";
 642         };
 643
 644         uart3: serial@ff1b0000 {
 645                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 646                 reg = <0x0 0xff1b0000 0x0 0x100>;
 647                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 648                 clock-names = "baudclk", "apb_pclk";
 649                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 650                 reg-shift = <2>;
 651                 reg-io-width = <4>;
 652                 pinctrl-names = "default";
 653                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 654                 status = "disabled";
 655         };
 656
 657         spi0: spi@ff1c0000 {
 658                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 659                 reg = <0x0 0xff1c0000 0x0 0x1000>;
 660                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 661                 clock-names = "spiclk", "apb_pclk";
 662                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 663                 pinctrl-names = "default";
 664                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 665                 #address-cells = <1>;
 666                 #size-cells = <0>;
 667                 status = "disabled";
 668         };
 669
 670         spi1: spi@ff1d0000 {
 671                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 672                 reg = <0x0 0xff1d0000 0x0 0x1000>;
 673                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 674                 clock-names = "spiclk", "apb_pclk";
 675                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 676                 pinctrl-names = "default";
 677                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 678                 #address-cells = <1>;
 679                 #size-cells = <0>;
 680                 status = "disabled";
 681         };
 682
 683         spi2: spi@ff1e0000 {
 684                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 685                 reg = <0x0 0xff1e0000 0x0 0x1000>;
 686                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 687                 clock-names = "spiclk", "apb_pclk";
 688                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 689                 pinctrl-names = "default";
 690                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 691                 #address-cells = <1>;
 692                 #size-cells = <0>;
 693                 status = "disabled";
 694         };
 695
 696         spi4: spi@ff1f0000 {
 697                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 698                 reg = <0x0 0xff1f0000 0x0 0x1000>;
 699                 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
 700                 clock-names = "spiclk", "apb_pclk";
 701                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 702                 pinctrl-names = "default";
 703                 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
 704                 #address-cells = <1>;
 705                 #size-cells = <0>;
 706                 status = "disabled";
 707         };
 708
 709         spi5: spi@ff200000 {
 710                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 711                 reg = <0x0 0xff200000 0x0 0x1000>;
 712                 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
 713                 clock-names = "spiclk", "apb_pclk";
 714                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
 715                 pinctrl-names = "default";
 716                 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
 717                 #address-cells = <1>;
 718                 #size-cells = <0>;
 719                 status = "disabled";
 720         };
 721
 722         thermal-zones {
 723                 soc_thermal: soc-thermal {
 724                         polling-delay-passive = <100>; /* milliseconds */
 725                         polling-delay = <1000>; /* milliseconds */
 726                         sustainable-power = <2600>; /* milliwatts */
 727
 728                         thermal-sensors = <&tsadc 0>;
 729
 730                         trips {
 731                                 threshold: trip-point@0 {
 732                                         temperature = <70000>; /* millicelsius */
 733                                         hysteresis = <2000>; /* millicelsius */
 734                                         type = "passive";
 735                                 };
 736                                 target: trip-point@1 {
 737                                         temperature = <85000>; /* millicelsius */
 738                                         hysteresis = <2000>; /* millicelsius */
 739                                         type = "passive";
 740                                 };
 741                                 soc_crit: soc-crit {
 742                                         temperature = <95000>; /* millicelsius */
 743                                         hysteresis = <2000>; /* millicelsius */
 744                                         type = "critical";
 745                                 };
 746                         };
 747
 748                         cooling-maps {
 749                                 map0 {
 750                                         trip = <&target>;
 751                                         cooling-device =
 752                                                 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 753                                 };
 754                                 map1 {
 755                                         trip = <&target>;
 756                                         cooling-device =
 757                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 758                                 };
 759                                 map2 {
 760                                         trip = <&target>;
 761                                         cooling-device =
 762                                                 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 763                                 };
 764                         };
 765                 };
 766
 767                 gpu_thermal: gpu-thermal {
 768                         polling-delay-passive = <100>; /* milliseconds */
 769                         polling-delay = <1000>; /* milliseconds */
 770
 771                         thermal-sensors = <&tsadc 1>;
 772                 };
 773         };
 774
 775         tsadc: tsadc@ff260000 {
 776                 compatible = "rockchip,rk3399-tsadc";
 777                 reg = <0x0 0xff260000 0x0 0x100>;
 778                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 779                 rockchip,grf = <&grf>;
 780                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 781                 clock-names = "tsadc", "apb_pclk";
 782                 assigned-clocks = <&cru SCLK_TSADC>;
 783                 assigned-clock-rates = <750000>;
 784                 resets = <&cru SRST_TSADC>;
 785                 reset-names = "tsadc-apb";
 786                 pinctrl-names = "init", "default", "sleep";
 787                 pinctrl-0 = <&otp_gpio>;
 788                 pinctrl-1 = <&otp_out>;
 789                 pinctrl-2 = <&otp_gpio>;
 790                 #thermal-sensor-cells = <1>;
 791                 rockchip,hw-tshut-temp = <95000>;
 792                 status = "disabled";
 793         };
 794
 795         qos_gpu: qos_gpu@0xffae0000 {
 796                 compatible ="syscon";
 797                 reg = <0x0 0xffae0000 0x0 0x20>;
 798         };
 799         qos_video_m0: qos_video_m0@0xffab8000 {
 800                 compatible ="syscon";
 801                 reg = <0x0 0xffab8000 0x0 0x20>;
 802         };
 803         qos_video_m1_r: qos_video_m1_r@0xffac0000 {
 804                 compatible ="syscon";
 805                 reg = <0x0 0xffac0000 0x0 0x20>;
 806         };
 807         qos_video_m1_w: qos_video_m1_w@0xffac0080 {
 808                 compatible ="syscon";
 809                 reg = <0x0 0xffac0080 0x0 0x20>;
 810         };
 811         qos_rga_r: qos_rga_r@0xffab0000 {
 812                 compatible ="syscon";
 813                 reg = <0x0 0xffab0000 0x0 0x20>;
 814         };
 815         qos_rga_w: qos_rga_w@0xffab0080 {
 816                 compatible ="syscon";
 817                 reg = <0x0 0xffab0000 0x0 0x20>;
 818         };
 819         qos_iep: qos_iep@0xffa98000 {
 820                 compatible ="syscon";
 821                 reg = <0x0 0xffa98000 0x0 0x20>;
 822         };
 823         qos_vop_big_r: qos_vop_big_r@0xffac8000 {
 824                 compatible ="syscon";
 825                 reg = <0x0 0xffac8000 0x0 0x20>;
 826         };
 827         qos_vop_big_w: qos_vop_big_w@0xffac8080 {
 828                 compatible ="syscon";
 829                 reg = <0x0 0xffac8080 0x0 0x20>;
 830         };
 831         qos_vop_little: qos_vop_little@0xffad0000 {
 832                 compatible ="syscon";
 833                 reg = <0x0 0xffad0000 0x0 0x20>;
 834         };
 835         qos_isp0_m0: qos_isp0_m0@0xffaa0000 {
 836                 compatible ="syscon";
 837                 reg = <0x0 0xffaa0000 0x0 0x20>;
 838         };
 839         qos_isp0_m1: qos_isp0_m1@0xffaa0080 {
 840                 compatible ="syscon";
 841                 reg = <0x0 0xffaa0080 0x0 0x20>;
 842         };
 843         qos_isp1_m0: qos_isp1_m0@0xffaa8000 {
 844                 compatible ="syscon";
 845                 reg = <0x0 0xffaa8000 0x0 0x20>;
 846         };
 847         qos_isp1_m1: qos_isp1_m1@0xffaa8080 {
 848                 compatible ="syscon";
 849                 reg = <0x0 0xffaa8080 0x0 0x20>;
 850         };
 851         qos_hdcp: qos_hdcp@0xffa90000 {
 852                 compatible ="syscon";
 853                 reg = <0x0 0xffa90000 0x0 0x20>;
 854         };
 855
 856         pmu: power-management@ff310000 {
 857                 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
 858                 reg = <0x0 0xff310000 0x0 0x1000>;
 859
 860                 power: power-controller {
 861                         status = "okay";
 862                         compatible = "rockchip,rk3399-power-controller";
 863                         #power-domain-cells = <1>;
 864                         #address-cells = <1>;
 865                         #size-cells = <0>;
 866
 867
 868                         pd_vdu {
 869                                 reg = <RK3399_PD_VDU>;
 870                                 pm_qos = <&qos_video_m1_r>,
 871                                          <&qos_video_m1_w>;
 872                         };
 873                         pd_vcodec {
 874                                 reg = <RK3399_PD_VCODEC>;
 875                                 pm_qos = <&qos_video_m0>;
 876                         };
 877                         pd_iep {
 878                                 reg = <RK3399_PD_IEP>;
 879                                 pm_qos = <&qos_iep>;
 880                         };
 881                         pd_rga {
 882                                 reg = <RK3399_PD_RGA>;
 883                                 pm_qos = <&qos_rga_r>,
 884                                          <&qos_rga_w>;
 885                         };
 886                         pd_vio {
 887                                 reg = <RK3399_PD_VIO>;
 888                                 #address-cells = <1>;
 889                                 #size-cells = <0>;
 890
 891                                 pd_isp0 {
 892                                         reg = <RK3399_PD_ISP0>;
 893                                         pm_qos = <&qos_isp0_m0>,
 894                                                  <&qos_isp0_m1>;
 895                                 };
 896                                 pd_isp1 {
 897                                         reg = <RK3399_PD_ISP1>;
 898                                         pm_qos = <&qos_isp1_m0>,
 899                                                  <&qos_isp1_m1>;
 900                                 };
 901                                 pd_hdcp {
 902                                         reg = <RK3399_PD_HDCP>;
 903                                         pm_qos = <&qos_hdcp>;
 904                                 };
 905                                 pd_vo {
 906                                         reg = <RK3399_PD_VO>;
 907                                         #address-cells = <1>;
 908                                         #size-cells = <0>;
 909
 910                                         pd_vopb {
 911                                                 reg = <RK3399_PD_VOPB>;
 912                                                 pm_qos = <&qos_vop_big_r>,
 913                                                          <&qos_vop_big_w>;
 914                                         };
 915                                         pd_vopl {
 916                                                 reg = <RK3399_PD_VOPL>;
 917                                                 pm_qos = <&qos_vop_little>;
 918                                         };
 919                                 };
 920                         };
 921                         pd_gpu {
 922                                 reg = <RK3399_PD_GPU>;
 923                                 pm_qos = <&qos_gpu>;
 924                         };
 925                 };
 926         };
 927
 928         pmugrf: syscon@ff320000 {
 929                 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
 930                 reg = <0x0 0xff320000 0x0 0x1000>;
 931
 932                 reboot-mode {
 933                         compatible = "syscon-reboot-mode";
 934                         offset = <0x300>;
 935                         mode-normal = <BOOT_NORMAL>;
 936                         mode-recovery = <BOOT_RECOVERY>;
 937                         mode-bootloader = <BOOT_FASTBOOT>;
 938                         mode-loader = <BOOT_LOADER>;
 939                 };
 940         };
 941
 942         spi3: spi@ff350000 {
 943                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 944                 reg = <0x0 0xff350000 0x0 0x1000>;
 945                 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
 946                 clock-names = "spiclk", "apb_pclk";
 947                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 948                 pinctrl-names = "default";
 949                 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
 950                 #address-cells = <1>;
 951                 #size-cells = <0>;
 952                 status = "disabled";
 953         };
 954
 955         uart4: serial@ff370000 {
 956                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 957                 reg = <0x0 0xff370000 0x0 0x100>;
 958                 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
 959                 clock-names = "baudclk", "apb_pclk";
 960                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 961                 reg-shift = <2>;
 962                 reg-io-width = <4>;
 963                 pinctrl-names = "default";
 964                 pinctrl-0 = <&uart4_xfer>;
 965                 status = "disabled";
 966         };
 967
 968         i2c4: i2c@ff3d0000 {
 969                 compatible = "rockchip,rk3399-i2c";
 970                 reg = <0x0 0xff3d0000 0x0 0x1000>;
 971                 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
 972                 clock-names = "i2c", "pclk";
 973                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 974                 pinctrl-names = "default";
 975                 pinctrl-0 = <&i2c4_xfer>;
 976                 #address-cells = <1>;
 977                 #size-cells = <0>;
 978                 status = "disabled";
 979         };
 980
 981         i2c8: i2c@ff3e0000 {
 982                 compatible = "rockchip,rk3399-i2c";
 983                 reg = <0x0 0xff3e0000 0x0 0x1000>;
 984                 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
 985                 clock-names = "i2c", "pclk";
 986                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 987                 pinctrl-names = "default";
 988                 pinctrl-0 = <&i2c8_xfer>;
 989                 #address-cells = <1>;
 990                 #size-cells = <0>;
 991                 status = "disabled";
 992         };
 993
 994         pcie0: pcie@f8000000 {
 995                 compatible = "rockchip,rk3399-pcie";
 996                 #address-cells = <3>;
 997                 #size-cells = <2>;
 998                 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
 999                          <&cru PCLK_PCIE>, <&cru SCLK_PCIEPHY_REF>;
1000                 clock-names = "aclk_pcie", "aclk_perf_pcie",
1001                               "hclk_pcie", "clk_pciephy_ref";
1002                 bus-range = <0x0 0x1>;
1003                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
1004                              <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
1005                              <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
1006                 interrupt-names = "pcie-sys", "pcie-legacy", "pcie-client";
1007                 ranges = < 0x82000000 0 0xfa000000 0x0 0xfa000000 0 0x600000
1008                            0x81000000 0 0xfa600000 0x0 0xfa600000 0 0x100000 >;
1009                 reg = < 0x0 0xf8000000 0x0 0x2000000 >,
1010                       < 0x0 0xfd000000 0x0 0x1000000 >;
1011                 reg-name = "axi-base", "apb-base";
1012                 resets = <&cru SRST_PCIEPHY>, <&cru SRST_PCIE_CORE>,
1013                          <&cru SRST_PCIE_MGMT>, <&cru SRST_PCIE_MGMT_STICKY>,
1014                          <&cru SRST_PCIE_PIPE>;
1015                 reset-names = "phy-rst", "core-rst", "mgmt-rst",
1016                               "mgmt-sticky-rst", "pipe-rst";
1017                 rockchip,grf = <&grf>;
1018                 pcie-conf = <0xe220>;
1019                 pcie-status = <0xe2a4>;
1020                 pcie-laneoff = <0xe214>;
1021                 msi-parent = <&its>;
1022                 #interrupt-cells = <1>;
1023                 interrupt-map-mask = <0 0 0 7>;
1024                 interrupt-map = <0 0 0 1 &pcie0 1>,
1025                                 <0 0 0 2 &pcie0 2>,
1026                                 <0 0 0 3 &pcie0 3>,
1027                                 <0 0 0 4 &pcie0 4>;
1028                 status = "disabled";
1029                 pcie_intc: interrupt-controller {
1030                         interrupt-controller;
1031                         #address-cells = <0>;
1032                         #interrupt-cells = <1>;
1033                 };
1034         };
1035
1036         pwm0: pwm@ff420000 {
1037                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1038                 reg = <0x0 0xff420000 0x0 0x10>;
1039                 #pwm-cells = <3>;
1040                 pinctrl-names = "default";
1041                 pinctrl-0 = <&pwm0_pin>;
1042                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1043                 clock-names = "pwm";
1044                 status = "disabled";
1045         };
1046
1047         pwm1: pwm@ff420010 {
1048                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1049                 reg = <0x0 0xff420010 0x0 0x10>;
1050                 #pwm-cells = <3>;
1051                 pinctrl-names = "default";
1052                 pinctrl-0 = <&pwm1_pin>;
1053                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1054                 clock-names = "pwm";
1055                 status = "disabled";
1056         };
1057
1058         pwm2: pwm@ff420020 {
1059                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1060                 reg = <0x0 0xff420020 0x0 0x10>;
1061                 #pwm-cells = <3>;
1062                 pinctrl-names = "default";
1063                 pinctrl-0 = <&pwm2_pin>;
1064                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1065                 clock-names = "pwm";
1066                 status = "disabled";
1067         };
1068
1069         pwm3: pwm@ff420030 {
1070                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1071                 reg = <0x0 0xff420030 0x0 0x10>;
1072                 #pwm-cells = <3>;
1073                 pinctrl-names = "default";
1074                 pinctrl-0 = <&pwm3a_pin>;
1075                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1076                 clock-names = "pwm";
1077                 status = "disabled";
1078         };
1079
1080         rga: rga@ff680000 {
1081                 compatible = "rockchip,rk3399-rga";
1082                 reg = <0x0 0xff680000 0x0 0x10000>;
1083                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
1084                 interrupt-names = "rga";
1085                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
1086                 clock-names = "aclk", "hclk", "sclk";
1087                 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
1088                 reset-names = "core", "axi", "ahb";
1089                 status = "disabled";
1090         };
1091
1092         pmucru: pmu-clock-controller@ff750000 {
1093                 compatible = "rockchip,rk3399-pmucru";
1094                 reg = <0x0 0xff750000 0x0 0x1000>;
1095                 #clock-cells = <1>;
1096                 #reset-cells = <1>;
1097                 assigned-clocks = <&pmucru PLL_PPLL>;
1098                 assigned-clock-rates = <676000000>;
1099         };
1100
1101         cru: clock-controller@ff760000 {
1102                 compatible = "rockchip,rk3399-cru";
1103                 reg = <0x0 0xff760000 0x0 0x1000>;
1104                 #clock-cells = <1>;
1105                 #reset-cells = <1>;
1106                 assigned-clocks =
1107                         <&cru ACLK_VOP0>, <&cru HCLK_VOP0>,
1108                         <&cru ACLK_VOP1>, <&cru HCLK_VOP1>,
1109                         <&cru ARMCLKL>, <&cru ARMCLKB>,
1110                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1111                         <&cru PLL_NPLL>,
1112                         <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1113                         <&cru PCLK_PERIHP>,
1114                         <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1115                         <&cru PCLK_PERILP0>,
1116                         <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
1117                 assigned-clock-rates =
1118                          <400000000>,  <200000000>,
1119                          <400000000>,  <200000000>,
1120                          <816000000>, <816000000>,
1121                          <594000000>,  <800000000>,
1122                         <1000000000>,
1123                          <150000000>,   <75000000>,
1124                           <37500000>,
1125                          <100000000>,  <100000000>,
1126                           <50000000>,
1127                          <100000000>,   <50000000>;
1128         };
1129
1130         grf: syscon@ff770000 {
1131                 compatible = "rockchip,rk3399-grf", "syscon";
1132                 reg = <0x0 0xff770000 0x0 0x10000>;
1133         };
1134
1135         watchdog@ff840000 {
1136                 compatible = "snps,dw-wdt";
1137                 reg = <0x0 0xff840000 0x0 0x100>;
1138                 clocks = <&cru PCLK_WDT>;
1139                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1140         };
1141
1142         rktimer: rktimer@ff850000 {
1143                 compatible = "rockchip,rk3399-timer";
1144                 reg = <0x0 0xff850000 0x0 0x1000>;
1145                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1146                 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1147                 clock-names = "pclk", "timer";
1148         };
1149
1150         spdif: spdif@ff870000 {
1151                 compatible = "rockchip,rk3399-spdif";
1152                 reg = <0x0 0xff870000 0x0 0x1000>;
1153                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
1154                 dmas = <&dmac_bus 7>;
1155                 dma-names = "tx";
1156                 clock-names = "mclk", "hclk";
1157                 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1158                 pinctrl-names = "default";
1159                 pinctrl-0 = <&spdif_bus>;
1160                 status = "disabled";
1161         };
1162
1163         i2s0: i2s@ff880000 {
1164                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1165                 reg = <0x0 0xff880000 0x0 0x1000>;
1166                 rockchip,grf = <&grf>;
1167                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1168                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1169                 dma-names = "tx", "rx";
1170                 clock-names = "i2s_clk", "i2s_hclk";
1171                 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1172                 pinctrl-names = "default";
1173                 pinctrl-0 = <&i2s0_8ch_bus>;
1174                 status = "disabled";
1175         };
1176
1177         i2s1: i2s@ff890000 {
1178                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1179                 reg = <0x0 0xff890000 0x0 0x1000>;
1180                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1181                 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1182                 dma-names = "tx", "rx";
1183                 clock-names = "i2s_clk", "i2s_hclk";
1184                 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1185                 pinctrl-names = "default";
1186                 pinctrl-0 = <&i2s1_2ch_bus>;
1187                 status = "disabled";
1188         };
1189
1190         i2s2: i2s@ff8a0000 {
1191                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1192                 reg = <0x0 0xff8a0000 0x0 0x1000>;
1193                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1194                 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1195                 dma-names = "tx", "rx";
1196                 clock-names = "i2s_clk", "i2s_hclk";
1197                 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1198                 status = "disabled";
1199         };
1200
1201         gpu: gpu@ff9a0000 {
1202                 compatible = "arm,malit860",
1203                              "arm,malit86x",
1204                              "arm,malit8xx",
1205                              "arm,mali-midgard";
1206
1207                 reg = <0x0 0xff9a0000 0x0 0x10000>;
1208
1209                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
1210                              <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
1211                              <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1212                 interrupt-names = "GPU", "JOB", "MMU";
1213
1214                 clocks = <&cru ACLK_GPU>;
1215                 clock-names = "clk_mali";
1216                 #cooling-cells = <2>; /* min followed by max */
1217                 operating-points-v2 = <&gpu_opp_table>;
1218                 power-domains = <&power RK3399_PD_GPU>;
1219                 status = "disabled";
1220
1221                 power_model {
1222                         compatible = "arm,mali-simple-power-model";
1223                         voltage = <900>;
1224                         frequency = <500>;
1225                         static-power = <300>;
1226                         dynamic-power = <1780>;
1227                         ts = <32000 4700 (-80) 2>;
1228                         thermal-zone = "gpu-thermal";
1229                 };
1230         };
1231
1232         gpu_opp_table: gpu_opp_table {
1233                 compatible = "operating-points-v2";
1234                 opp-shared;
1235
1236                 opp00 {
1237                         opp-hz = /bits/ 64 <200000000>;
1238                         opp-microvolt = <900000>;
1239                 };
1240                 opp01 {
1241                         opp-hz = /bits/ 64 <300000000>;
1242                         opp-microvolt = <900000>;
1243                 };
1244                 opp02 {
1245                         opp-hz = /bits/ 64 <400000000>;
1246                         opp-microvolt = <900000>;
1247                 };
1248
1249         };
1250
1251         vopl: vop@ff8f0000 {
1252                 compatible = "rockchip,rk3399-vop-lit";
1253                 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1254                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
1255                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1256                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1257                 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1258                 reset-names = "axi", "ahb", "dclk";
1259                 iommus = <&vopl_mmu>;
1260                 status = "disabled";
1261
1262                 vopl_out: port {
1263                         #address-cells = <1>;
1264                         #size-cells = <0>;
1265
1266                         vopl_out_mipi: endpoint@0 {
1267                                 reg = <0>;
1268                                 remote-endpoint = <&mipi_in_vopl>;
1269                         };
1270
1271                         vopl_out_edp: endpoint@1 {
1272                                 reg = <1>;
1273                                 remote-endpoint = <&edp_in_vopl>;
1274                         };
1275                 };
1276         };
1277
1278         vopl_mmu: iommu@ff8f3f00 {
1279                 compatible = "rockchip,iommu";
1280                 reg = <0x0 0xff8f3f00 0x0 0x100>;
1281                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
1282                 interrupt-names = "vopl_mmu";
1283                 #iommu-cells = <0>;
1284                 status = "disabled";
1285         };
1286
1287         vopb: vop@ff900000 {
1288                 compatible = "rockchip,rk3399-vop-big";
1289                 reg = <0x0 0xff900000 0x0 0x3efc>;
1290                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1291                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1292                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1293                 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1294                 reset-names = "axi", "ahb", "dclk";
1295                 iommus = <&vopb_mmu>;
1296                 status = "disabled";
1297
1298                 vopb_out: port {
1299                         #address-cells = <1>;
1300                         #size-cells = <0>;
1301
1302                         vopb_out_edp: endpoint@0 {
1303                                 reg = <0>;
1304                                 remote-endpoint = <&edp_in_vopb>;
1305                         };
1306
1307                         vopb_out_mipi: endpoint@1 {
1308                                 reg = <1>;
1309                                 remote-endpoint = <&mipi_in_vopb>;
1310                         };
1311                 };
1312         };
1313
1314         vopb_mmu: iommu@ff903f00 {
1315                 compatible = "rockchip,iommu";
1316                 reg = <0x0 0xff903f00 0x0 0x100>;
1317                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1318                 interrupt-names = "vopb_mmu";
1319                 #iommu-cells = <0>;
1320                 status = "disabled";
1321         };
1322
1323         mipi_dsi: mipi@ff960000 {
1324                 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1325                 reg = <0x0 0xff960000 0x0 0x8000>;
1326                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1327                 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
1328                          <&cru SCLK_DPHY_TX0_CFG>;
1329                 clock-names = "ref", "pclk", "phy_cfg";
1330                 rockchip,grf = <&grf>;
1331                 #address-cells = <1>;
1332                 #size-cells = <0>;
1333                 status = "disabled";
1334
1335                 ports {
1336                         #address-cells = <1>;
1337                         #size-cells = <0>;
1338                         reg = <1>;
1339
1340                         mipi_in: port {
1341                                 #address-cells = <1>;
1342                                 #size-cells = <0>;
1343
1344                                 mipi_in_vopb: endpoint@0 {
1345                                         reg = <0>;
1346                                         remote-endpoint = <&vopb_out_mipi>;
1347                                 };
1348                                 mipi_in_vopl: endpoint@1 {
1349                                         reg = <1>;
1350                                         remote-endpoint = <&vopl_out_mipi>;
1351                                 };
1352                         };
1353                 };
1354         };
1355
1356         edp: edp@ff970000 {
1357                 compatible = "rockchip,rk3399-edp";
1358                 reg = <0x0 0xff970000 0x0 0x8000>;
1359                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1360                 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1361                 clock-names = "dp", "pclk";
1362                 resets = <&cru SRST_P_EDP_CTRL>;
1363                 reset-names = "dp";
1364                 rockchip,grf = <&grf>;
1365                 status = "disabled";
1366                 pinctrl-names = "default";
1367                 pinctrl-0 = <&edp_hpd>;
1368
1369                 ports {
1370                         #address-cells = <1>;
1371                         #size-cells = <0>;
1372
1373                         edp_in: port@0 {
1374                                 reg = <0>;
1375                                 #address-cells = <1>;
1376                                 #size-cells = <0>;
1377
1378                                 edp_in_vopb: endpoint@0 {
1379                                         reg = <0>;
1380                                         remote-endpoint = <&vopb_out_edp>;
1381                                 };
1382
1383                                 edp_in_vopl: endpoint@1 {
1384                                         reg = <1>;
1385                                         remote-endpoint = <&vopl_out_edp>;
1386                                 };
1387                         };
1388                 };
1389         };
1390
1391         display_subsystem: display-subsystem {
1392                 compatible = "rockchip,display-subsystem";
1393                 ports = <&vopl_out>, <&vopb_out>;
1394                 status = "disabled";
1395         };
1396
1397         pinctrl: pinctrl {
1398                 compatible = "rockchip,rk3399-pinctrl";
1399                 rockchip,grf = <&grf>;
1400                 rockchip,pmu = <&pmugrf>;
1401                 #address-cells = <0x2>;
1402                 #size-cells = <0x2>;
1403                 ranges;
1404
1405                 gpio0: gpio0@ff720000 {
1406                         compatible = "rockchip,gpio-bank";
1407                         reg = <0x0 0xff720000 0x0 0x100>;
1408                         clocks = <&pmucru PCLK_GPIO0_PMU>;
1409                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1410
1411                         gpio-controller;
1412                         #gpio-cells = <0x2>;
1413
1414                         interrupt-controller;
1415                         #interrupt-cells = <0x2>;
1416                 };
1417
1418                 gpio1: gpio1@ff730000 {
1419                         compatible = "rockchip,gpio-bank";
1420                         reg = <0x0 0xff730000 0x0 0x100>;
1421                         clocks = <&pmucru PCLK_GPIO1_PMU>;
1422                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1423
1424                         gpio-controller;
1425                         #gpio-cells = <0x2>;
1426
1427                         interrupt-controller;
1428                         #interrupt-cells = <0x2>;
1429                 };
1430
1431                 gpio2: gpio2@ff780000 {
1432                         compatible = "rockchip,gpio-bank";
1433                         reg = <0x0 0xff780000 0x0 0x100>;
1434                         clocks = <&cru PCLK_GPIO2>;
1435                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1436
1437                         gpio-controller;
1438                         #gpio-cells = <0x2>;
1439
1440                         interrupt-controller;
1441                         #interrupt-cells = <0x2>;
1442                 };
1443
1444                 gpio3: gpio3@ff788000 {
1445                         compatible = "rockchip,gpio-bank";
1446                         reg = <0x0 0xff788000 0x0 0x100>;
1447                         clocks = <&cru PCLK_GPIO3>;
1448                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1449
1450                         gpio-controller;
1451                         #gpio-cells = <0x2>;
1452
1453                         interrupt-controller;
1454                         #interrupt-cells = <0x2>;
1455                 };
1456
1457                 gpio4: gpio4@ff790000 {
1458                         compatible = "rockchip,gpio-bank";
1459                         reg = <0x0 0xff790000 0x0 0x100>;
1460                         clocks = <&cru PCLK_GPIO4>;
1461                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1462
1463                         gpio-controller;
1464                         #gpio-cells = <0x2>;
1465
1466                         interrupt-controller;
1467                         #interrupt-cells = <0x2>;
1468                 };
1469
1470                 pcfg_pull_up: pcfg-pull-up {
1471                         bias-pull-up;
1472                 };
1473
1474                 pcfg_pull_down: pcfg-pull-down {
1475                         bias-pull-down;
1476                 };
1477
1478                 pcfg_pull_none: pcfg-pull-none {
1479                         bias-disable;
1480                 };
1481
1482                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1483                         bias-disable;
1484                         drive-strength = <12>;
1485                 };
1486
1487                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1488                         bias-pull-up;
1489                         drive-strength = <8>;
1490                 };
1491
1492                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1493                         bias-pull-down;
1494                         drive-strength = <4>;
1495                 };
1496
1497                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1498                         bias-pull-up;
1499                         drive-strength = <2>;
1500                 };
1501
1502                 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
1503                         bias-pull-down;
1504                         drive-strength = <12>;
1505                 };
1506
1507                 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
1508                         bias-disable;
1509                         drive-strength = <13>;
1510                 };
1511
1512                 emmc {
1513                         emmc_pwr: emmc-pwr {
1514                                 rockchip,pins =
1515                                         <0 5 RK_FUNC_1 &pcfg_pull_up>;
1516                         };
1517                 };
1518
1519                 gmac {
1520                         rgmii_pins: rgmii-pins {
1521                                 rockchip,pins =
1522                                         /* mac_txclk */
1523                                         <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
1524                                         /* mac_rxclk */
1525                                         <3 14 RK_FUNC_1 &pcfg_pull_none>,
1526                                         /* mac_mdio */
1527                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
1528                                         /* mac_txen */
1529                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1530                                         /* mac_clk */
1531                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
1532                                         /* mac_rxdv */
1533                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
1534                                         /* mac_mdc */
1535                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
1536                                         /* mac_rxd1 */
1537                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
1538                                         /* mac_rxd0 */
1539                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
1540                                         /* mac_txd1 */
1541                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1542                                         /* mac_txd0 */
1543                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
1544                                         /* mac_rxd3 */
1545                                         <3 3 RK_FUNC_1 &pcfg_pull_none>,
1546                                         /* mac_rxd2 */
1547                                         <3 2 RK_FUNC_1 &pcfg_pull_none>,
1548                                         /* mac_txd3 */
1549                                         <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
1550                                         /* mac_txd2 */
1551                                         <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
1552                         };
1553
1554                         rmii_pins: rmii-pins {
1555                                 rockchip,pins =
1556                                         /* mac_mdio */
1557                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
1558                                         /* mac_txen */
1559                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1560                                         /* mac_clk */
1561                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
1562                                         /* mac_rxer */
1563                                         <3 10 RK_FUNC_1 &pcfg_pull_none>,
1564                                         /* mac_rxdv */
1565                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
1566                                         /* mac_mdc */
1567                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
1568                                         /* mac_rxd1 */
1569                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
1570                                         /* mac_rxd0 */
1571                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
1572                                         /* mac_txd1 */
1573                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1574                                         /* mac_txd0 */
1575                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
1576                         };
1577                 };
1578
1579                 i2c0 {
1580                         i2c0_xfer: i2c0-xfer {
1581                                 rockchip,pins =
1582                                         <1 15 RK_FUNC_2 &pcfg_pull_none>,
1583                                         <1 16 RK_FUNC_2 &pcfg_pull_none>;
1584                         };
1585                 };
1586
1587                 i2c1 {
1588                         i2c1_xfer: i2c1-xfer {
1589                                 rockchip,pins =
1590                                         <4 2 RK_FUNC_1 &pcfg_pull_none>,
1591                                         <4 1 RK_FUNC_1 &pcfg_pull_none>;
1592                         };
1593                 };
1594
1595                 i2c2 {
1596                         i2c2_xfer: i2c2-xfer {
1597                                 rockchip,pins =
1598                                         <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1599                                         <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
1600                         };
1601                 };
1602
1603                 i2c3 {
1604                         i2c3_xfer: i2c3-xfer {
1605                                 rockchip,pins =
1606                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
1607                                         <4 16 RK_FUNC_1 &pcfg_pull_none>;
1608                         };
1609
1610                         i2c3_gpio: i2c3_gpio {
1611                                 rockchip,pins =
1612                                         <4 17 RK_FUNC_GPIO &pcfg_pull_none>,
1613                                         <4 16 RK_FUNC_GPIO &pcfg_pull_none>;
1614                         };
1615
1616                 };
1617
1618                 i2c4 {
1619                         i2c4_xfer: i2c4-xfer {
1620                                 rockchip,pins =
1621                                         <1 12 RK_FUNC_1 &pcfg_pull_none>,
1622                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
1623                         };
1624                 };
1625
1626                 i2c5 {
1627                         i2c5_xfer: i2c5-xfer {
1628                                 rockchip,pins =
1629                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
1630                                         <3 10 RK_FUNC_2 &pcfg_pull_none>;
1631                         };
1632                 };
1633
1634                 i2c6 {
1635                         i2c6_xfer: i2c6-xfer {
1636                                 rockchip,pins =
1637                                         <2 10 RK_FUNC_2 &pcfg_pull_none>,
1638                                         <2 9 RK_FUNC_2 &pcfg_pull_none>;
1639                         };
1640                 };
1641
1642                 i2c7 {
1643                         i2c7_xfer: i2c7-xfer {
1644                                 rockchip,pins =
1645                                         <2 8 RK_FUNC_2 &pcfg_pull_none>,
1646                                         <2 7 RK_FUNC_2 &pcfg_pull_none>;
1647                         };
1648                 };
1649
1650                 i2c8 {
1651                         i2c8_xfer: i2c8-xfer {
1652                                 rockchip,pins =
1653                                         <1 21 RK_FUNC_1 &pcfg_pull_none>,
1654                                         <1 20 RK_FUNC_1 &pcfg_pull_none>;
1655                         };
1656                 };
1657
1658                 i2s0 {
1659                         i2s0_8ch_bus: i2s0-8ch-bus {
1660                                 rockchip,pins =
1661                                         <3 24 RK_FUNC_1 &pcfg_pull_none>,
1662                                         <3 25 RK_FUNC_1 &pcfg_pull_none>,
1663                                         <3 26 RK_FUNC_1 &pcfg_pull_none>,
1664                                         <3 27 RK_FUNC_1 &pcfg_pull_none>,
1665                                         <3 28 RK_FUNC_1 &pcfg_pull_none>,
1666                                         <3 29 RK_FUNC_1 &pcfg_pull_none>,
1667                                         <3 30 RK_FUNC_1 &pcfg_pull_none>,
1668                                         <3 31 RK_FUNC_1 &pcfg_pull_none>,
1669                                         <4 0 RK_FUNC_1 &pcfg_pull_none>;
1670                         };
1671                 };
1672
1673                 i2s1 {
1674                         i2s1_2ch_bus: i2s1-2ch-bus {
1675                                 rockchip,pins =
1676                                         <4 3 RK_FUNC_1 &pcfg_pull_none>,
1677                                         <4 4 RK_FUNC_1 &pcfg_pull_none>,
1678                                         <4 5 RK_FUNC_1 &pcfg_pull_none>,
1679                                         <4 6 RK_FUNC_1 &pcfg_pull_none>,
1680                                         <4 7 RK_FUNC_1 &pcfg_pull_none>;
1681                         };
1682                 };
1683
1684                 sdio0 {
1685                         sdio0_bus1: sdio0-bus1 {
1686                                 rockchip,pins =
1687                                         <2 20 RK_FUNC_1 &pcfg_pull_up>;
1688                         };
1689
1690                         sdio0_bus4: sdio0-bus4 {
1691                                 rockchip,pins =
1692                                         <2 20 RK_FUNC_1 &pcfg_pull_up>,
1693                                         <2 21 RK_FUNC_1 &pcfg_pull_up>,
1694                                         <2 22 RK_FUNC_1 &pcfg_pull_up>,
1695                                         <2 23 RK_FUNC_1 &pcfg_pull_up>;
1696                         };
1697
1698                         sdio0_cmd: sdio0-cmd {
1699                                 rockchip,pins =
1700                                         <2 24 RK_FUNC_1 &pcfg_pull_up>;
1701                         };
1702
1703                         sdio0_clk: sdio0-clk {
1704                                 rockchip,pins =
1705                                         <2 25 RK_FUNC_1 &pcfg_pull_none>;
1706                         };
1707
1708                         sdio0_cd: sdio0-cd {
1709                                 rockchip,pins =
1710                                         <2 26 RK_FUNC_1 &pcfg_pull_up>;
1711                         };
1712
1713                         sdio0_pwr: sdio0-pwr {
1714                                 rockchip,pins =
1715                                         <2 27 RK_FUNC_1 &pcfg_pull_up>;
1716                         };
1717
1718                         sdio0_bkpwr: sdio0-bkpwr {
1719                                 rockchip,pins =
1720                                         <2 28 RK_FUNC_1 &pcfg_pull_up>;
1721                         };
1722
1723                         sdio0_wp: sdio0-wp {
1724                                 rockchip,pins =
1725                                         <0 3 RK_FUNC_1 &pcfg_pull_up>;
1726                         };
1727
1728                         sdio0_int: sdio0-int {
1729                                 rockchip,pins =
1730                                         <0 4 RK_FUNC_1 &pcfg_pull_up>;
1731                         };
1732                 };
1733
1734                 sdmmc {
1735                         sdmmc_bus1: sdmmc-bus1 {
1736                                 rockchip,pins =
1737                                         <4 8 RK_FUNC_1 &pcfg_pull_up>;
1738                         };
1739
1740                         sdmmc_bus4: sdmmc-bus4 {
1741                                 rockchip,pins =
1742                                         <4 8 RK_FUNC_1 &pcfg_pull_up>,
1743                                         <4 9 RK_FUNC_1 &pcfg_pull_up>,
1744                                         <4 10 RK_FUNC_1 &pcfg_pull_up>,
1745                                         <4 11 RK_FUNC_1 &pcfg_pull_up>;
1746                         };
1747
1748                         sdmmc_clk: sdmmc-clk {
1749                                 rockchip,pins =
1750                                         <4 12 RK_FUNC_1 &pcfg_pull_none>;
1751                         };
1752
1753                         sdmmc_cmd: sdmmc-cmd {
1754                                 rockchip,pins =
1755                                         <4 13 RK_FUNC_1 &pcfg_pull_up>;
1756                         };
1757
1758                         sdmmc_cd: sdmcc-cd {
1759                                 rockchip,pins =
1760                                         <0 7 RK_FUNC_1 &pcfg_pull_up>;
1761                         };
1762
1763                         sdmmc_wp: sdmmc-wp {
1764                                 rockchip,pins =
1765                                         <0 8 RK_FUNC_1 &pcfg_pull_up>;
1766                         };
1767                 };
1768
1769                 spdif {
1770                         spdif_bus: spdif-bus {
1771                                 rockchip,pins =
1772                                         <4 21 RK_FUNC_1 &pcfg_pull_none>;
1773                         };
1774                 };
1775
1776                 spi0 {
1777                         spi0_clk: spi0-clk {
1778                                 rockchip,pins =
1779                                         <3 6 RK_FUNC_2 &pcfg_pull_up>;
1780                         };
1781                         spi0_cs0: spi0-cs0 {
1782                                 rockchip,pins =
1783                                         <3 7 RK_FUNC_2 &pcfg_pull_up>;
1784                         };
1785                         spi0_cs1: spi0-cs1 {
1786                                 rockchip,pins =
1787                                         <3 8 RK_FUNC_2 &pcfg_pull_up>;
1788                         };
1789                         spi0_tx: spi0-tx {
1790                                 rockchip,pins =
1791                                         <3 5 RK_FUNC_2 &pcfg_pull_up>;
1792                         };
1793                         spi0_rx: spi0-rx {
1794                                 rockchip,pins =
1795                                         <3 4 RK_FUNC_2 &pcfg_pull_up>;
1796                         };
1797                 };
1798
1799                 spi1 {
1800                         spi1_clk: spi1-clk {
1801                                 rockchip,pins =
1802                                         <1 9 RK_FUNC_2 &pcfg_pull_up>;
1803                         };
1804                         spi1_cs0: spi1-cs0 {
1805                                 rockchip,pins =
1806                                         <1 10 RK_FUNC_2 &pcfg_pull_up>;
1807                         };
1808                         spi1_rx: spi1-rx {
1809                                 rockchip,pins =
1810                                         <1 7 RK_FUNC_2 &pcfg_pull_up>;
1811                         };
1812                         spi1_tx: spi1-tx {
1813                                 rockchip,pins =
1814                                         <1 8 RK_FUNC_2 &pcfg_pull_up>;
1815                         };
1816                 };
1817
1818                 spi2 {
1819                         spi2_clk: spi2-clk {
1820                                 rockchip,pins =
1821                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
1822                         };
1823                         spi2_cs0: spi2-cs0 {
1824                                 rockchip,pins =
1825                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
1826                         };
1827                         spi2_rx: spi2-rx {
1828                                 rockchip,pins =
1829                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
1830                         };
1831                         spi2_tx: spi2-tx {
1832                                 rockchip,pins =
1833                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
1834                         };
1835                 };
1836
1837                 spi3 {
1838                         spi3_clk: spi3-clk {
1839                                 rockchip,pins =
1840                                         <1 17 RK_FUNC_1 &pcfg_pull_up>;
1841                         };
1842                         spi3_cs0: spi3-cs0 {
1843                                 rockchip,pins =
1844                                         <1 18 RK_FUNC_1 &pcfg_pull_up>;
1845                         };
1846                         spi3_rx: spi3-rx {
1847                                 rockchip,pins =
1848                                         <1 15 RK_FUNC_1 &pcfg_pull_up>;
1849                         };
1850                         spi3_tx: spi3-tx {
1851                                 rockchip,pins =
1852                                         <1 16 RK_FUNC_1 &pcfg_pull_up>;
1853                         };
1854                 };
1855
1856                 spi4 {
1857                         spi4_clk: spi4-clk {
1858                                 rockchip,pins =
1859                                         <3 2 RK_FUNC_2 &pcfg_pull_up>;
1860                         };
1861                         spi4_cs0: spi4-cs0 {
1862                                 rockchip,pins =
1863                                         <3 3 RK_FUNC_2 &pcfg_pull_up>;
1864                         };
1865                         spi4_rx: spi4-rx {
1866                                 rockchip,pins =
1867                                         <3 0 RK_FUNC_2 &pcfg_pull_up>;
1868                         };
1869                         spi4_tx: spi4-tx {
1870                                 rockchip,pins =
1871                                         <3 1 RK_FUNC_2 &pcfg_pull_up>;
1872                         };
1873                 };
1874
1875                 spi5 {
1876                         spi5_clk: spi5-clk {
1877                                 rockchip,pins =
1878                                         <2 22 RK_FUNC_2 &pcfg_pull_up>;
1879                         };
1880                         spi5_cs0: spi5-cs0 {
1881                                 rockchip,pins =
1882                                         <2 23 RK_FUNC_2 &pcfg_pull_up>;
1883                         };
1884                         spi5_rx: spi5-rx {
1885                                 rockchip,pins =
1886                                         <2 20 RK_FUNC_2 &pcfg_pull_up>;
1887                         };
1888                         spi5_tx: spi5-tx {
1889                                 rockchip,pins =
1890                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
1891                         };
1892                 };
1893
1894                 tsadc {
1895                         otp_gpio: otp-gpio {
1896                                 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
1897                         };
1898
1899                         otp_out: otp-out {
1900                                 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
1901                         };
1902                 };
1903
1904                 uart0 {
1905                         uart0_xfer: uart0-xfer {
1906                                 rockchip,pins =
1907                                         <2 16 RK_FUNC_1 &pcfg_pull_up>,
1908                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
1909                         };
1910
1911                         uart0_cts: uart0-cts {
1912                                 rockchip,pins =
1913                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
1914                         };
1915
1916                         uart0_rts: uart0-rts {
1917                                 rockchip,pins =
1918                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
1919                         };
1920                 };
1921
1922                 uart1 {
1923                         uart1_xfer: uart1-xfer {
1924                                 rockchip,pins =
1925                                         <3 12 RK_FUNC_2 &pcfg_pull_up>,
1926                                         <3 13 RK_FUNC_2 &pcfg_pull_none>;
1927                         };
1928                 };
1929
1930                 uart2a {
1931                         uart2a_xfer: uart2a-xfer {
1932                                 rockchip,pins =
1933                                         <4 8 RK_FUNC_2 &pcfg_pull_up>,
1934                                         <4 9 RK_FUNC_2 &pcfg_pull_none>;
1935                         };
1936                 };
1937
1938                 uart2b {
1939                         uart2b_xfer: uart2b-xfer {
1940                                 rockchip,pins =
1941                                         <4 16 RK_FUNC_2 &pcfg_pull_up>,
1942                                         <4 17 RK_FUNC_2 &pcfg_pull_none>;
1943                         };
1944                 };
1945
1946                 uart2c {
1947                         uart2c_xfer: uart2c-xfer {
1948                                 rockchip,pins =
1949                                         <4 19 RK_FUNC_1 &pcfg_pull_up>,
1950                                         <4 20 RK_FUNC_1 &pcfg_pull_none>;
1951                         };
1952                 };
1953
1954                 uart3 {
1955                         uart3_xfer: uart3-xfer {
1956                                 rockchip,pins =
1957                                         <3 14 RK_FUNC_2 &pcfg_pull_up>,
1958                                         <3 15 RK_FUNC_2 &pcfg_pull_none>;
1959                         };
1960
1961                         uart3_cts: uart3-cts {
1962                                 rockchip,pins =
1963                                         <3 18 RK_FUNC_2 &pcfg_pull_none>;
1964                         };
1965
1966                         uart3_rts: uart3-rts {
1967                                 rockchip,pins =
1968                                         <3 19 RK_FUNC_2 &pcfg_pull_none>;
1969                         };
1970                 };
1971
1972                 uart4 {
1973                         uart4_xfer: uart4-xfer {
1974                                 rockchip,pins =
1975                                         <1 7 RK_FUNC_1 &pcfg_pull_up>,
1976                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
1977                         };
1978                 };
1979
1980                 uarthdcp {
1981                         uarthdcp_xfer: uarthdcp-xfer {
1982                                 rockchip,pins =
1983                                         <4 21 RK_FUNC_2 &pcfg_pull_up>,
1984                                         <4 22 RK_FUNC_2 &pcfg_pull_none>;
1985                         };
1986                 };
1987
1988                 pwm0 {
1989                         pwm0_pin: pwm0-pin {
1990                                 rockchip,pins =
1991                                         <4 18 RK_FUNC_1 &pcfg_pull_none>;
1992                         };
1993
1994                         vop0_pwm_pin: vop0-pwm-pin {
1995                                 rockchip,pins =
1996                                         <4 18 RK_FUNC_2 &pcfg_pull_none>;
1997                         };
1998                 };
1999
2000                 pwm1 {
2001                         pwm1_pin: pwm1-pin {
2002                                 rockchip,pins =
2003                                         <4 22 RK_FUNC_1 &pcfg_pull_none>;
2004                         };
2005
2006                         vop1_pwm_pin: vop1-pwm-pin {
2007                                 rockchip,pins =
2008                                         <4 18 RK_FUNC_3 &pcfg_pull_none>;
2009                         };
2010                 };
2011
2012                 pwm2 {
2013                         pwm2_pin: pwm2-pin {
2014                                 rockchip,pins =
2015                                         <1 19 RK_FUNC_1 &pcfg_pull_none>;
2016                         };
2017                 };
2018
2019                 pwm3a {
2020                         pwm3a_pin: pwm3a-pin {
2021                                 rockchip,pins =
2022                                         <0 6 RK_FUNC_1 &pcfg_pull_none>;
2023                         };
2024                 };
2025
2026                 pwm3b {
2027                         pwm3b_pin: pwm3b-pin {
2028                                 rockchip,pins =
2029                                         <1 14 RK_FUNC_1 &pcfg_pull_none>;
2030                         };
2031                 };
2032
2033                 edp {
2034                         edp_hpd: edp-hpd {
2035                                 rockchip,pins =
2036                                         <4 23 RK_FUNC_2 &pcfg_pull_none>;
2037                         };
2038                 };
2039
2040                 hdmi {
2041                         hdmi_i2c_xfer: hdmi-i2c-xfer {
2042                                 rockchip,pins =
2043                                         <4 17 RK_FUNC_3 &pcfg_pull_none>,
2044                                         <4 16 RK_FUNC_3 &pcfg_pull_none>;
2045                         };
2046
2047                         hdmi_cec: hdmi-cec {
2048                                 rockchip,pins =
2049                                         <4 23 RK_FUNC_1 &pcfg_pull_none>;
2050                         };
2051                 };
2052
2053                 pcie {
2054                         pcie_clkreqn: pci-clkreqn {
2055                                 rockchip,pins =
2056                                         <2 26 RK_FUNC_2 &pcfg_pull_none>;
2057                         };
2058
2059                         pcie_clkreqnb: pci-clkreqnb {
2060                                 rockchip,pins =
2061                                         <4 24 RK_FUNC_1 &pcfg_pull_none>;
2062                         };
2063                 };
2064         };
2065 };