arch/arm64/boot/dts/rockchip/rk3399.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3399-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/interrupt-controller/irq.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/power/rk3399-power.h>
  49 #include <dt-bindings/thermal/thermal.h>
  50
  51 / {
  52         compatible = "rockchip,rk3399";
  53         interrupt-parent = <&gic>;
  54         #address-cells = <2>;
  55         #size-cells = <2>;
  56
  57         aliases {
  58                 i2c0 = &i2c0;
  59                 i2c1 = &i2c1;
  60                 i2c2 = &i2c2;
  61                 i2c3 = &i2c3;
  62                 i2c4 = &i2c4;
  63                 i2c5 = &i2c5;
  64                 i2c6 = &i2c6;
  65                 i2c7 = &i2c7;
  66                 i2c8 = &i2c8;
  67                 serial0 = &uart0;
  68                 serial1 = &uart1;
  69                 serial2 = &uart2;
  70                 serial3 = &uart3;
  71                 serial4 = &uart4;
  72         };
  73
  74         psci {
  75                 compatible = "arm,psci-1.0";
  76                 method = "smc";
  77         };
  78
  79         cpus {
  80                 #address-cells = <2>;
  81                 #size-cells = <0>;
  82
  83                 cpu-map {
  84                         cluster0 {
  85                                 core0 {
  86                                         cpu = <&cpu_l0>;
  87                                 };
  88                                 core1 {
  89                                         cpu = <&cpu_l1>;
  90                                 };
  91                                 core2 {
  92                                         cpu = <&cpu_l2>;
  93                                 };
  94                                 core3 {
  95                                         cpu = <&cpu_l3>;
  96                                 };
  97                         };
  98
  99                         cluster1 {
 100                                 core0 {
 101                                         cpu = <&cpu_b0>;
 102                                 };
 103                                 core1 {
 104                                         cpu = <&cpu_b1>;
 105                                 };
 106                         };
 107                 };
 108
 109                 cpu_l0: cpu@0 {
 110                         device_type = "cpu";
 111                         compatible = "arm,cortex-a53", "arm,armv8";
 112                         reg = <0x0 0x0>;
 113                         enable-method = "psci";
 114                         #cooling-cells = <2>; /* min followed by max */
 115                         clocks = <&cru ARMCLKL>;
 116                         operating-points-v2 = <&cluster0_opp>;
 117                 };
 118
 119                 cpu_l1: cpu@1 {
 120                         device_type = "cpu";
 121                         compatible = "arm,cortex-a53", "arm,armv8";
 122                         reg = <0x0 0x1>;
 123                         enable-method = "psci";
 124                         clocks = <&cru ARMCLKL>;
 125                         operating-points-v2 = <&cluster0_opp>;
 126                 };
 127
 128                 cpu_l2: cpu@2 {
 129                         device_type = "cpu";
 130                         compatible = "arm,cortex-a53", "arm,armv8";
 131                         reg = <0x0 0x2>;
 132                         enable-method = "psci";
 133                         clocks = <&cru ARMCLKL>;
 134                         operating-points-v2 = <&cluster0_opp>;
 135                 };
 136
 137                 cpu_l3: cpu@3 {
 138                         device_type = "cpu";
 139                         compatible = "arm,cortex-a53", "arm,armv8";
 140                         reg = <0x0 0x3>;
 141                         enable-method = "psci";
 142                         clocks = <&cru ARMCLKL>;
 143                         operating-points-v2 = <&cluster0_opp>;
 144                 };
 145
 146                 cpu_b0: cpu@100 {
 147                         device_type = "cpu";
 148                         compatible = "arm,cortex-a72", "arm,armv8";
 149                         reg = <0x0 0x100>;
 150                         enable-method = "psci";
 151                         #cooling-cells = <2>; /* min followed by max */
 152                         clocks = <&cru ARMCLKB>;
 153                         operating-points-v2 = <&cluster1_opp>;
 154                 };
 155
 156                 cpu_b1: cpu@101 {
 157                         device_type = "cpu";
 158                         compatible = "arm,cortex-a72", "arm,armv8";
 159                         reg = <0x0 0x101>;
 160                         enable-method = "psci";
 161                         clocks = <&cru ARMCLKB>;
 162                         operating-points-v2 = <&cluster1_opp>;
 163                 };
 164         };
 165
 166         cluster0_opp: opp_table0 {
 167                 compatible = "operating-points-v2";
 168                 opp-shared;
 169
 170                 opp00 {
 171                         opp-hz = /bits/ 64 <408000000>;
 172                         opp-microvolt = <900000>;
 173                         clock-latency-ns = <40000>;
 174                 };
 175                 opp01 {
 176                         opp-hz = /bits/ 64 <600000000>;
 177                         opp-microvolt = <900000>;
 178                 };
 179                 opp02 {
 180                         opp-hz = /bits/ 64 <816000000>;
 181                         opp-microvolt = <900000>;
 182                 };
 183                 opp03 {
 184                         opp-hz = /bits/ 64 <1008000000>;
 185                         opp-microvolt = <900000>;
 186                 };
 187         };
 188
 189         cluster1_opp: opp_table1 {
 190                 compatible = "operating-points-v2";
 191                 opp-shared;
 192
 193                 opp00 {
 194                         opp-hz = /bits/ 64 <408000000>;
 195                         opp-microvolt = <900000>;
 196                         clock-latency-ns = <40000>;
 197                 };
 198                 opp01 {
 199                         opp-hz = /bits/ 64 <600000000>;
 200                         opp-microvolt = <900000>;
 201                 };
 202                 opp02 {
 203                         opp-hz = /bits/ 64 <816000000>;
 204                         opp-microvolt = <900000>;
 205                 };
 206                 opp03 {
 207                         opp-hz = /bits/ 64 <1008000000>;
 208                         opp-microvolt = <900000>;
 209                 };
 210                 opp04 {
 211                         opp-hz = /bits/ 64 <1200000000>;
 212                         opp-microvolt = <900000>;
 213                 };
 214         };
 215
 216         timer {
 217                 compatible = "arm,armv8-timer";
 218                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
 219                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
 220                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
 221                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
 222         };
 223
 224         arm-pmu {
 225                 compatible = "arm,armv8-pmuv3";
 226                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
 227         };
 228
 229         xin24m: xin24m {
 230                 compatible = "fixed-clock";
 231                 #clock-cells = <0>;
 232                 clock-frequency = <24000000>;
 233                 clock-output-names = "xin24m";
 234         };
 235
 236         amba {
 237                 compatible = "arm,amba-bus";
 238                 #address-cells = <2>;
 239                 #size-cells = <2>;
 240                 ranges;
 241
 242                 dmac_bus: dma-controller@ff6d0000 {
 243                         compatible = "arm,pl330", "arm,primecell";
 244                         reg = <0x0 0xff6d0000 0x0 0x4000>;
 245                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 246                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 247                         #dma-cells = <1>;
 248                         clocks = <&cru ACLK_DMAC0_PERILP>;
 249                         clock-names = "apb_pclk";
 250                 };
 251
 252                 dmac_peri: dma-controller@ff6e0000 {
 253                         compatible = "arm,pl330", "arm,primecell";
 254                         reg = <0x0 0xff6e0000 0x0 0x4000>;
 255                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 256                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 257                         #dma-cells = <1>;
 258                         clocks = <&cru ACLK_DMAC1_PERILP>;
 259                         clock-names = "apb_pclk";
 260                 };
 261         };
 262
 263         gmac: eth@fe300000 {
 264                 compatible = "rockchip,rk3399-gmac";
 265                 reg = <0x0 0xfe300000 0x0 0x10000>;
 266                 rockchip,grf = <&grf>;
 267                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 268                 interrupt-names = "macirq";
 269                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
 270                          <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
 271                          <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
 272                          <&cru PCLK_GMAC>;
 273                 clock-names = "stmmaceth", "mac_clk_rx",
 274                               "mac_clk_tx", "clk_mac_ref",
 275                               "clk_mac_refout", "aclk_mac",
 276                               "pclk_mac";
 277                 resets = <&cru SRST_A_GMAC>;
 278                 reset-names = "stmmaceth";
 279                 status = "disabled";
 280         };
 281
 282         emmc_phy: phy {
 283                 compatible = "rockchip,rk3399-emmc-phy";
 284                 reg-offset = <0xf780>;
 285                 #phy-cells = <0>;
 286                 rockchip,grf = <&grf>;
 287                 status = "disabled";
 288         };
 289
 290         sdio0: dwmmc@fe310000 {
 291                 compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc";
 292                 reg = <0x0 0xfe310000 0x0 0x4000>;
 293                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 294                 clock-freq-min-max = <400000 150000000>;
 295                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 296                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 297                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 298                 fifo-depth = <0x100>;
 299                 status = "disabled";
 300         };
 301
 302         sdmmc: dwmmc@fe320000 {
 303                 compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc";
 304                 reg = <0x0 0xfe320000 0x0 0x4000>;
 305                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 306                 clock-freq-min-max = <400000 150000000>;
 307                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 308                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 309                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 310                 fifo-depth = <0x100>;
 311                 status = "disabled";
 312         };
 313
 314         sdhci: sdhci@fe330000 {
 315                 compatible = "arasan,sdhci-5.1";
 316                 reg = <0x0 0xfe330000 0x0 0x10000>;
 317                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 318                 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
 319                 clock-names = "clk_xin", "clk_ahb";
 320                 phys = <&emmc_phy>;
 321                 phy-names = "phy_arasan";
 322                 status = "disabled";
 323         };
 324
 325         usb2phy {
 326                 compatible = "rockchip,rk3399-usb-phy";
 327                 rockchip,grf = <&grf>;
 328                 vbus_drv-gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>;
 329                 #address-cells = <1>;
 330                 #size-cells = <0>;
 331
 332                 usb2phy0: usb2-phy0 {
 333                         #phy-cells = <0>;
 334                         #clock-cells = <0>;
 335                         reg = <0xe458>;
 336                 };
 337
 338                 usb2phy1: usb2-phy1 {
 339                         #phy-cells = <0>;
 340                         #clock-cells = <0>;
 341                         reg = <0xe468>;
 342                 };
 343         };
 344
 345         usb_host0_echi: usb@fe380000 {
 346                 compatible = "generic-ehci";
 347                 reg = <0x0 0xfe380000 0x0 0x20000>;
 348                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 349                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
 350                 clock-names = "hclk_host0", "hclk_host0_arb";
 351                 phys = <&usb2phy0>;
 352                 phy-names = "usb2_phy0";
 353                 status = "disabled";
 354         };
 355
 356         usb_host0_ohci: usb@fe3a0000 {
 357                 compatible = "generic-ohci";
 358                 reg = <0x0 0xfe3a0000 0x0 0x20000>;
 359                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 360                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
 361                 clock-names = "hclk_host0", "hclk_host0_arb";
 362                 status = "disabled";
 363         };
 364
 365         usb_host1_echi: usb@fe3c0000 {
 366                 compatible = "generic-ehci";
 367                 reg = <0x0 0xfe3c0000 0x0 0x20000>;
 368                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 369                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
 370                 clock-names = "hclk_host1", "hclk_host1_arb";
 371                 phys = <&usb2phy1>;
 372                 phy-names = "usb2_phy1";
 373                 status = "disabled";
 374         };
 375
 376         usb_host1_ohci: usb@fe3e0000 {
 377                 compatible = "generic-ohci";
 378                 reg = <0x0 0xfe3e0000 0x0 0x20000>;
 379                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 380                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
 381                 clock-names = "hclk_host1", "hclk_host1_arb";
 382                 status = "disabled";
 383         };
 384
 385         usbdrd3_0: usb@fe800000 {
 386                 compatible = "rockchip,dwc3";
 387                 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
 388                          <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
 389                          <&cru ACLK_USB3>, <&cru ACLK_USB3_NOC>,
 390                          <&cru ACLK_USB3_GRF>;
 391                 clock-names = "clk_usb3otg0_ref", "clk_usb3otg0_suspend",
 392                               "aclk_usb3otg0", "aclk_usb3_rksoc_axi_perf",
 393                               "aclk_usb3", "aclk_usb3_noc",
 394                               "aclk_usb3_grf";
 395                 #address-cells = <2>;
 396                 #size-cells = <2>;
 397                 ranges;
 398                 status = "disabled";
 399                 usbdrd_dwc3_0: dwc3 {
 400                         compatible = "snps,dwc3";
 401                         reg = <0x0 0xfe800000 0x0 0x100000>;
 402                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 403                         dr_mode = "otg";
 404                         tx-fifo-resize;
 405                         snps,dis_enblslpm_quirk;
 406                         snps,phyif_utmi_16_bits;
 407                         snps,dis_u2_freeclk_exists_quirk;
 408                         snps,dis_del_phy_power_chg_quirk;
 409                         status = "disabled";
 410                 };
 411         };
 412
 413         usbdrd3_1: usb@fe900000 {
 414                 compatible = "rockchip,dwc3";
 415                 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
 416                          <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
 417                          <&cru ACLK_USB3>, <&cru ACLK_USB3_NOC>,
 418                          <&cru ACLK_USB3_GRF>;
 419                 clock-names = "clk_usb3otg1_ref", "clk_usb3otg1_suspend",
 420                               "aclk_usb3otg1", "aclk_usb3_rksoc_axi_perf",
 421                               "aclk_usb3", "aclk_usb3_noc",
 422                               "aclk_usb3_grf";
 423                 #address-cells = <2>;
 424                 #size-cells = <2>;
 425                 ranges;
 426                 status = "disabled";
 427                 usbdrd_dwc3_1: dwc3 {
 428                         compatible = "snps,dwc3";
 429                         reg = <0x0 0xfe900000 0x0 0x100000>;
 430                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 431                         dr_mode = "otg";
 432                         tx-fifo-resize;
 433                         snps,dis_enblslpm_quirk;
 434                         snps,phyif_utmi_16_bits;
 435                         snps,dis_u2_freeclk_exists_quirk;
 436                         snps,dis_del_phy_power_chg_quirk;
 437                         status = "disabled";
 438                 };
 439         };
 440
 441         gic: interrupt-controller@fee00000 {
 442                 compatible = "arm,gic-v3";
 443                 #interrupt-cells = <3>;
 444                 #address-cells = <2>;
 445                 #size-cells = <2>;
 446                 ranges;
 447                 interrupt-controller;
 448
 449                 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
 450                       <0x0 0xfef00000 0 0xc0000>, /* GICR */
 451                       <0x0 0xfff00000 0 0x10000>, /* GICC */
 452                       <0x0 0xfff10000 0 0x10000>, /* GICH */
 453                       <0x0 0xfff20000 0 0x10000>; /* GICV */
 454                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 455                 its: interrupt-controller@fee20000 {
 456                         compatible = "arm,gic-v3-its";
 457                         msi-controller;
 458                         reg = <0x0 0xfee20000 0x0 0x20000>;
 459                 };
 460         };
 461
 462         saradc: saradc@ff100000 {
 463                 compatible = "rockchip,rk3399-saradc";
 464                 reg = <0x0 0xff100000 0x0 0x100>;
 465                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 466                 #io-channel-cells = <1>;
 467                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 468                 clock-names = "saradc", "apb_pclk";
 469                 status = "disabled";
 470         };
 471
 472         i2c0: i2c@ff3c0000 {
 473                 compatible = "rockchip,rk3399-i2c";
 474                 reg = <0x0 0xff3c0000 0x0 0x1000>;
 475                 clocks =  <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
 476                 clock-names = "i2c", "pclk";
 477                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 478                 pinctrl-names = "default";
 479                 pinctrl-0 = <&i2c0_xfer>;
 480                 #address-cells = <1>;
 481                 #size-cells = <0>;
 482                 status = "disabled";
 483         };
 484
 485         i2c1: i2c@ff110000 {
 486                 compatible = "rockchip,rk3399-i2c";
 487                 reg = <0x0 0xff110000 0x0 0x1000>;
 488                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 489                 clock-names = "i2c", "pclk";
 490                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 491                 pinctrl-names = "default";
 492                 pinctrl-0 = <&i2c1_xfer>;
 493                 #address-cells = <1>;
 494                 #size-cells = <0>;
 495                 status = "disabled";
 496         };
 497
 498         i2c2: i2c@ff120000 {
 499                 compatible = "rockchip,rk3399-i2c";
 500                 reg = <0x0 0xff120000 0x0 0x1000>;
 501                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 502                 clock-names = "i2c", "pclk";
 503                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 504                 pinctrl-names = "default";
 505                 pinctrl-0 = <&i2c2_xfer>;
 506                 #address-cells = <1>;
 507                 #size-cells = <0>;
 508                 status = "disabled";
 509         };
 510
 511         i2c3: i2c@ff130000 {
 512                 compatible = "rockchip,rk3399-i2c";
 513                 reg = <0x0 0xff130000 0x0 0x1000>;
 514                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 515                 clock-names = "i2c", "pclk";
 516                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 517                 pinctrl-names = "default";
 518                 pinctrl-0 = <&i2c3_xfer>;
 519                 #address-cells = <1>;
 520                 #size-cells = <0>;
 521                 status = "disabled";
 522         };
 523
 524         i2c5: i2c@ff140000 {
 525                 compatible = "rockchip,rk3399-i2c";
 526                 reg = <0x0 0xff140000 0x0 0x1000>;
 527                 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
 528                 clock-names = "i2c", "pclk";
 529                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 530                 pinctrl-names = "default";
 531                 pinctrl-0 = <&i2c5_xfer>;
 532                 #address-cells = <1>;
 533                 #size-cells = <0>;
 534                 status = "disabled";
 535         };
 536
 537         i2c6: i2c@ff150000 {
 538                 compatible = "rockchip,rk3399-i2c";
 539                 reg = <0x0 0xff150000 0x0 0x1000>;
 540                 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
 541                 clock-names = "i2c", "pclk";
 542                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 543                 pinctrl-names = "default";
 544                 pinctrl-0 = <&i2c6_xfer>;
 545                 #address-cells = <1>;
 546                 #size-cells = <0>;
 547                 status = "disabled";
 548         };
 549
 550         i2c7: i2c@ff160000 {
 551                 compatible = "rockchip,rk3399-i2c";
 552                 reg = <0x0 0xff160000 0x0 0x1000>;
 553                 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
 554                 clock-names = "i2c", "pclk";
 555                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 556                 pinctrl-names = "default";
 557                 pinctrl-0 = <&i2c7_xfer>;
 558                 #address-cells = <1>;
 559                 #size-cells = <0>;
 560                 status = "disabled";
 561         };
 562
 563         uart0: serial@ff180000 {
 564                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 565                 reg = <0x0 0xff180000 0x0 0x100>;
 566                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 567                 clock-names = "baudclk", "apb_pclk";
 568                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 569                 reg-shift = <2>;
 570                 reg-io-width = <4>;
 571                 pinctrl-names = "default";
 572                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 573                 status = "disabled";
 574         };
 575
 576         uart1: serial@ff190000 {
 577                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 578                 reg = <0x0 0xff190000 0x0 0x100>;
 579                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 580                 clock-names = "baudclk", "apb_pclk";
 581                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 582                 reg-shift = <2>;
 583                 reg-io-width = <4>;
 584                 pinctrl-names = "default";
 585                 pinctrl-0 = <&uart1_xfer>;
 586                 status = "disabled";
 587         };
 588
 589         uart2: serial@ff1a0000 {
 590                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 591                 reg = <0x0 0xff1a0000 0x0 0x100>;
 592                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 593                 clock-names = "baudclk", "apb_pclk";
 594                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 595                 reg-shift = <2>;
 596                 reg-io-width = <4>;
 597                 pinctrl-names = "default";
 598                 pinctrl-0 = <&uart2c_xfer>;
 599                 status = "disabled";
 600         };
 601
 602         uart3: serial@ff1b0000 {
 603                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 604                 reg = <0x0 0xff1b0000 0x0 0x100>;
 605                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 606                 clock-names = "baudclk", "apb_pclk";
 607                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 608                 reg-shift = <2>;
 609                 reg-io-width = <4>;
 610                 pinctrl-names = "default";
 611                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 612                 status = "disabled";
 613         };
 614
 615         spi0: spi@ff1c0000 {
 616                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 617                 reg = <0x0 0xff1c0000 0x0 0x1000>;
 618                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 619                 clock-names = "spiclk", "apb_pclk";
 620                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 621                 pinctrl-names = "default";
 622                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 623                 #address-cells = <1>;
 624                 #size-cells = <0>;
 625                 status = "disabled";
 626         };
 627
 628         spi1: spi@ff1d0000 {
 629                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 630                 reg = <0x0 0xff1d0000 0x0 0x1000>;
 631                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 632                 clock-names = "spiclk", "apb_pclk";
 633                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 634                 pinctrl-names = "default";
 635                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 636                 #address-cells = <1>;
 637                 #size-cells = <0>;
 638                 status = "disabled";
 639         };
 640
 641         spi2: spi@ff1e0000 {
 642                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 643                 reg = <0x0 0xff1e0000 0x0 0x1000>;
 644                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 645                 clock-names = "spiclk", "apb_pclk";
 646                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 647                 pinctrl-names = "default";
 648                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 649                 #address-cells = <1>;
 650                 #size-cells = <0>;
 651                 status = "disabled";
 652         };
 653
 654         spi4: spi@ff1f0000 {
 655                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 656                 reg = <0x0 0xff1f0000 0x0 0x1000>;
 657                 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
 658                 clock-names = "spiclk", "apb_pclk";
 659                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 660                 pinctrl-names = "default";
 661                 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
 662                 #address-cells = <1>;
 663                 #size-cells = <0>;
 664                 status = "disabled";
 665         };
 666
 667         spi5: spi@ff200000 {
 668                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 669                 reg = <0x0 0xff200000 0x0 0x1000>;
 670                 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
 671                 clock-names = "spiclk", "apb_pclk";
 672                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
 673                 pinctrl-names = "default";
 674                 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
 675                 #address-cells = <1>;
 676                 #size-cells = <0>;
 677                 status = "disabled";
 678         };
 679
 680         thermal-zones {
 681                 #include "rk3368-thermal.dtsi"
 682         };
 683
 684         tsadc: tsadc@ff260000 {
 685                 compatible = "rockchip,rk3399-tsadc";
 686                 reg = <0x0 0xff260000 0x0 0x100>;
 687                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 688                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 689                 clock-names = "tsadc", "apb_pclk";
 690                 resets = <&cru SRST_TSADC>;
 691                 reset-names = "tsadc-apb";
 692                 pinctrl-names = "init", "default", "sleep";
 693                 pinctrl-0 = <&otp_gpio>;
 694                 pinctrl-1 = <&otp_out>;
 695                 pinctrl-2 = <&otp_gpio>;
 696                 #thermal-sensor-cells = <1>;
 697                 rockchip,hw-tshut-temp = <95000>;
 698                 status = "disabled";
 699         };
 700
 701         pmu: power-management@ff31000 {
 702                 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
 703                 reg = <0x0 0xff310000 0x0 0x1000>;
 704
 705                 power: power-controller {
 706                         status = "disabled";
 707                         compatible = "rockchip,rk3399-power-controller";
 708                         #power-domain-cells = <1>;
 709                         #address-cells = <1>;
 710                         #size-cells = <0>;
 711
 712                         pd_center {
 713                                 reg = <RK3399_PD_CENTER>;
 714                                 #address-cells = <1>;
 715                                 #size-cells = <0>;
 716
 717                                 pd_vdu {
 718                                         reg = <RK3399_PD_VDU>;
 719                                 };
 720                                 pd_vcodec {
 721                                         reg = <RK3399_PD_VCODEC>;
 722                                 };
 723                                 pd_iep {
 724                                         reg = <RK3399_PD_IEP>;
 725                                 };
 726                                 pd_rga {
 727                                         reg = <RK3399_PD_RGA>;
 728                                 };
 729                         };
 730                         pd_vio {
 731                                 reg = <RK3399_PD_VIO>;
 732                                 #address-cells = <1>;
 733                                 #size-cells = <0>;
 734
 735                                 pd_isp0 {
 736                                         reg = <RK3399_PD_ISP0>;
 737                                 };
 738                                 pd_isp1 {
 739                                         reg = <RK3399_PD_ISP1>;
 740                                 };
 741                                 pd_hdcp {
 742                                         reg = <RK3399_PD_HDCP>;
 743                                 };
 744                                 pd_vo {
 745                                         reg = <RK3399_PD_VO>;
 746                                         #address-cells = <1>;
 747                                         #size-cells = <0>;
 748
 749                                         pd_vopb {
 750                                                 reg = <RK3399_PD_VOPB>;
 751                                         };
 752                                         pd_vopl {
 753                                                 reg = <RK3399_PD_VOPL>;
 754                                         };
 755                                 };
 756                         };
 757                         pd_gpu {
 758                                 reg = <RK3399_PD_GPU>;
 759                         };
 760                 };
 761         };
 762
 763         pmugrf: syscon@ff320000 {
 764                 compatible = "rockchip,rk3399-pmugrf", "syscon";
 765                 reg = <0x0 0xff320000 0x0 0x1000>;
 766         };
 767
 768         spi3: spi@ff350000 {
 769                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 770                 reg = <0x0 0xff350000 0x0 0x1000>;
 771                 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
 772                 clock-names = "spiclk", "apb_pclk";
 773                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 774                 pinctrl-names = "default";
 775                 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
 776                 #address-cells = <1>;
 777                 #size-cells = <0>;
 778                 status = "disabled";
 779         };
 780
 781         uart4: serial@ff370000 {
 782                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 783                 reg = <0x0 0xff370000 0x0 0x100>;
 784                 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
 785                 clock-names = "baudclk", "apb_pclk";
 786                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 787                 reg-shift = <2>;
 788                 reg-io-width = <4>;
 789                 pinctrl-names = "default";
 790                 pinctrl-0 = <&uart4_xfer>;
 791                 status = "disabled";
 792         };
 793
 794         i2c4: i2c@ff3d0000 {
 795                 compatible = "rockchip,rk3399-i2c";
 796                 reg = <0x0 0xff3d0000 0x0 0x1000>;
 797                 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
 798                 clock-names = "i2c", "pclk";
 799                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 800                 pinctrl-names = "default";
 801                 pinctrl-0 = <&i2c4_xfer>;
 802                 #address-cells = <1>;
 803                 #size-cells = <0>;
 804                 status = "disabled";
 805         };
 806
 807         i2c8: i2c@ff3e0000 {
 808                 compatible = "rockchip,rk3399-i2c";
 809                 reg = <0x0 0xff3e0000 0x0 0x1000>;
 810                 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
 811                 clock-names = "i2c", "pclk";
 812                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 813                 pinctrl-names = "default";
 814                 pinctrl-0 = <&i2c8_xfer>;
 815                 #address-cells = <1>;
 816                 #size-cells = <0>;
 817                 status = "disabled";
 818         };
 819
 820         pwm0: pwm@ff420000 {
 821                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 822                 reg = <0x0 0xff420000 0x0 0x10>;
 823                 #pwm-cells = <3>;
 824                 pinctrl-names = "default";
 825                 pinctrl-0 = <&pwm0_pin>;
 826                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 827                 clock-names = "pwm";
 828                 status = "disabled";
 829         };
 830
 831         pwm1: pwm@ff420010 {
 832                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 833                 reg = <0x0 0xff420010 0x0 0x10>;
 834                 #pwm-cells = <3>;
 835                 pinctrl-names = "default";
 836                 pinctrl-0 = <&pwm1_pin>;
 837                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 838                 clock-names = "pwm";
 839                 status = "disabled";
 840         };
 841
 842         pwm2: pwm@ff420020 {
 843                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 844                 reg = <0x0 0xff420020 0x0 0x10>;
 845                 #pwm-cells = <3>;
 846                 pinctrl-names = "default";
 847                 pinctrl-0 = <&pwm2_pin>;
 848                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 849                 clock-names = "pwm";
 850                 status = "disabled";
 851         };
 852
 853         pwm3: pwm@ff420030 {
 854                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 855                 reg = <0x0 0xff420030 0x0 0x10>;
 856                 #pwm-cells = <3>;
 857                 pinctrl-names = "default";
 858                 pinctrl-0 = <&pwm3a_pin>;
 859                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 860                 clock-names = "pwm";
 861                 status = "disabled";
 862         };
 863
 864         pmucru: pmu-clock-controller@ff750000 {
 865                 compatible = "rockchip,rk3399-pmucru";
 866                 reg = <0x0 0xff750000 0x0 0x1000>;
 867                 rockchip,grf = <&pmugrf>;
 868                 #clock-cells = <1>;
 869                 #reset-cells = <1>;
 870                 assigned-clocks = <&pmucru PLL_PPLL>;
 871                 assigned-clock-rates = <676000000>;
 872         };
 873
 874         cru: clock-controller@ff760000 {
 875                 compatible = "rockchip,rk3399-cru";
 876                 reg = <0x0 0xff760000 0x0 0x1000>;
 877                 rockchip,grf = <&grf>;
 878                 #clock-cells = <1>;
 879                 #reset-cells = <1>;
 880                 assigned-clocks =
 881                         <&cru ARMCLKL>, <&cru ARMCLKB>,
 882                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 883                         <&cru PLL_NPLL>,
 884                         <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
 885                         <&cru PCLK_PERIHP>,
 886                         <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
 887                         <&cru PCLK_PERILP0>,
 888                         <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
 889                 assigned-clock-rates =
 890                          <816000000>, <1008000000>,
 891                          <594000000>,  <800000000>,
 892                         <1000000000>,
 893                          <150000000>,   <75000000>,
 894                           <37500000>,
 895                          <100000000>,  <100000000>,
 896                           <50000000>,
 897                          <100000000>,   <50000000>;
 898         };
 899
 900         grf: syscon@ff770000 {
 901                 compatible = "rockchip,rk3399-grf", "syscon";
 902                 reg = <0x0 0xff770000 0x0 0x10000>;
 903         };
 904
 905         wdt0: watchdog@ff840000 {
 906                 compatible = "snps,dw-wdt";
 907                 reg = <0x0 0xff840000 0x0 0x100>;
 908                 clocks = <&cru PCLK_WDT>;
 909                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 910                 status = "disabled";
 911         };
 912
 913         spdif: spdif@ff870000 {
 914                 compatible = "rockchip,rk3399-spdif";
 915                 reg = <0x0 0xff870000 0x0 0x1000>;
 916                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 917                 dmas = <&dmac_bus 7>;
 918                 dma-names = "tx";
 919                 clock-names = "hclk", "mclk";
 920                 clocks = <&cru HCLK_SPDIF>, <&cru SCLK_SPDIF_8CH>;
 921                 pinctrl-names = "default";
 922                 pinctrl-0 = <&spdif_bus>;
 923                 status = "disabled";
 924         };
 925
 926         i2s0: i2s@ff880000 {
 927                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
 928                 reg = <0x0 0xff880000 0x0 0x1000>;
 929                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 930                 #address-cells = <1>;
 931                 #size-cells = <0>;
 932                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
 933                 dma-names = "tx", "rx";
 934                 clock-names = "i2s_hclk", "i2s_clk";
 935                 clocks = <&cru HCLK_I2S0_8CH>, <&cru SCLK_I2S0_8CH>;
 936                 pinctrl-names = "default";
 937                 pinctrl-0 = <&i2s0_8ch_bus>;
 938                 status = "disabled";
 939         };
 940
 941         i2s1: i2s@ff890000 {
 942                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
 943                 reg = <0x0 0xff890000 0x0 0x1000>;
 944                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 945                 #address-cells = <1>;
 946                 #size-cells = <0>;
 947                 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
 948                 dma-names = "tx", "rx";
 949                 clock-names = "i2s_hclk", "i2s_clk";
 950                 clocks = <&cru HCLK_I2S1_8CH>, <&cru SCLK_I2S1_8CH>;
 951                 pinctrl-names = "default";
 952                 pinctrl-0 = <&i2s1_2ch_bus>;
 953                 status = "disabled";
 954         };
 955
 956         i2s2: i2s@ff8a0000 {
 957                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
 958                 reg = <0x0 0xff8a0000 0x0 0x1000>;
 959                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 960                 #address-cells = <1>;
 961                 #size-cells = <0>;
 962                 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
 963                 dma-names = "tx", "rx";
 964                 clock-names = "i2s_hclk", "i2s_clk";
 965                 clocks = <&cru HCLK_I2S2_8CH>, <&cru SCLK_I2S2_8CH>;
 966                 status = "disabled";
 967         };
 968
 969         pinctrl: pinctrl {
 970                 compatible = "rockchip,rk3399-pinctrl";
 971                 rockchip,grf = <&grf>;
 972                 rockchip,pmu = <&pmugrf>;
 973                 #address-cells = <0x2>;
 974                 #size-cells = <0x2>;
 975                 ranges;
 976
 977                 gpio0: gpio0@ff720000 {
 978                         compatible = "rockchip,gpio-bank";
 979                         reg = <0x0 0xff720000 0x0 0x100>;
 980                         clocks = <&pmucru PCLK_GPIO0_PMU>;
 981                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 982
 983                         gpio-controller;
 984                         #gpio-cells = <0x2>;
 985
 986                         interrupt-controller;
 987                         #interrupt-cells = <0x2>;
 988                 };
 989
 990                 gpio1: gpio1@ff730000 {
 991                         compatible = "rockchip,gpio-bank";
 992                         reg = <0x0 0xff730000 0x0 0x100>;
 993                         clocks = <&pmucru PCLK_GPIO1_PMU>;
 994                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 995
 996                         gpio-controller;
 997                         #gpio-cells = <0x2>;
 998
 999                         interrupt-controller;
1000                         #interrupt-cells = <0x2>;
1001                 };
1002
1003                 gpio2: gpio2@ff780000 {
1004                         compatible = "rockchip,gpio-bank";
1005                         reg = <0x0 0xff780000 0x0 0x100>;
1006                         clocks = <&cru PCLK_GPIO2>;
1007                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1008
1009                         gpio-controller;
1010                         #gpio-cells = <0x2>;
1011
1012                         interrupt-controller;
1013                         #interrupt-cells = <0x2>;
1014                 };
1015
1016                 gpio3: gpio3@ff788000 {
1017                         compatible = "rockchip,gpio-bank";
1018                         reg = <0x0 0xff788000 0x0 0x100>;
1019                         clocks = <&cru PCLK_GPIO3>;
1020                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1021
1022                         gpio-controller;
1023                         #gpio-cells = <0x2>;
1024
1025                         interrupt-controller;
1026                         #interrupt-cells = <0x2>;
1027                 };
1028
1029                 gpio4: gpio4@ff790000 {
1030                         compatible = "rockchip,gpio-bank";
1031                         reg = <0x0 0xff790000 0x0 0x100>;
1032                         clocks = <&cru PCLK_GPIO4>;
1033                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1034
1035                         gpio-controller;
1036                         #gpio-cells = <0x2>;
1037
1038                         interrupt-controller;
1039                         #interrupt-cells = <0x2>;
1040                 };
1041
1042                 pcfg_pull_up: pcfg-pull-up {
1043                         bias-pull-up;
1044                 };
1045
1046                 pcfg_pull_down: pcfg-pull-down {
1047                         bias-pull-down;
1048                 };
1049
1050                 pcfg_pull_none: pcfg-pull-none {
1051                         bias-disable;
1052                 };
1053
1054                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1055                         bias-disable;
1056                         drive-strength = <12>;
1057                 };
1058
1059                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1060                         bias-pull-up;
1061                         drive-strength = <8>;
1062                 };
1063
1064                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1065                         bias-pull-down;
1066                         drive-strength = <4>;
1067                 };
1068
1069                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1070                         bias-pull-up;
1071                         drive-strength = <2>;
1072                 };
1073
1074                 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
1075                         bias-pull-down;
1076                         drive-strength = <12>;
1077                 };
1078
1079                 emmc {
1080                         emmc_pwr: emmc-pwr {
1081                                 rockchip,pins =
1082                                         <0 5 RK_FUNC_1 &pcfg_pull_up>;
1083                         };
1084                 };
1085
1086                 gmac {
1087                         rgmii_pins: rgmii-pins {
1088                                 rockchip,pins =
1089                                         /* mac_txclk */
1090                                         <3 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
1091                                         /* mac_rxclk */
1092                                         <3 14 RK_FUNC_1 &pcfg_pull_none>,
1093                                         /* mac_mdio */
1094                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
1095                                         /* mac_txen */
1096                                         <3 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1097                                         /* mac_clk */
1098                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
1099                                         /* mac_rxdv */
1100                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
1101                                         /* mac_mdc */
1102                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
1103                                         /* mac_rxd1 */
1104                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
1105                                         /* mac_rxd0 */
1106                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
1107                                         /* mac_txd1 */
1108                                         <3 5 RK_FUNC_1 &pcfg_pull_none_12ma>,
1109                                         /* mac_txd0 */
1110                                         <3 4 RK_FUNC_1 &pcfg_pull_none_12ma>,
1111                                         /* mac_rxd3 */
1112                                         <3 3 RK_FUNC_1 &pcfg_pull_none>,
1113                                         /* mac_rxd2 */
1114                                         <3 2 RK_FUNC_1 &pcfg_pull_none>,
1115                                         /* mac_txd3 */
1116                                         <3 1 RK_FUNC_1 &pcfg_pull_none_12ma>,
1117                                         /* mac_txd2 */
1118                                         <3 0 RK_FUNC_1 &pcfg_pull_none_12ma>;
1119                         };
1120
1121                         rmii_pins: rmii-pins {
1122                                 rockchip,pins =
1123                                         /* mac_mdio */
1124                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
1125                                         /* mac_txen */
1126                                         <3 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1127                                         /* mac_clk */
1128                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
1129                                         /* mac_rxer */
1130                                         <3 10 RK_FUNC_1 &pcfg_pull_none>,
1131                                         /* mac_rxdv */
1132                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
1133                                         /* mac_mdc */
1134                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
1135                                         /* mac_rxd1 */
1136                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
1137                                         /* mac_rxd0 */
1138                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
1139                                         /* mac_txd1 */
1140                                         <3 5 RK_FUNC_1 &pcfg_pull_none_12ma>,
1141                                         /* mac_txd0 */
1142                                         <3 4 RK_FUNC_1 &pcfg_pull_none_12ma>;
1143                         };
1144                 };
1145
1146                 i2c0 {
1147                         i2c0_xfer: i2c0-xfer {
1148                                 rockchip,pins =
1149                                         <1 15 RK_FUNC_2 &pcfg_pull_none>,
1150                                         <1 16 RK_FUNC_2 &pcfg_pull_none>;
1151                         };
1152                 };
1153
1154                 i2c1 {
1155                         i2c1_xfer: i2c1-xfer {
1156                                 rockchip,pins =
1157                                         <4 2 RK_FUNC_1 &pcfg_pull_none>,
1158                                         <4 1 RK_FUNC_1 &pcfg_pull_none>;
1159                         };
1160                 };
1161
1162                 i2c2 {
1163                         i2c2_xfer: i2c2-xfer {
1164                                 rockchip,pins =
1165                                         <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1166                                         <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
1167                         };
1168                 };
1169
1170                 i2c3 {
1171                         i2c3_xfer: i2c3-xfer {
1172                                 rockchip,pins =
1173                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
1174                                         <4 16 RK_FUNC_1 &pcfg_pull_none>;
1175                         };
1176                 };
1177
1178                 i2c4 {
1179                         i2c4_xfer: i2c4-xfer {
1180                                 rockchip,pins =
1181                                         <1 12 RK_FUNC_1 &pcfg_pull_none>,
1182                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
1183                         };
1184                 };
1185
1186                 i2c5 {
1187                         i2c5_xfer: i2c5-xfer {
1188                                 rockchip,pins =
1189                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
1190                                         <3 10 RK_FUNC_2 &pcfg_pull_none>;
1191                         };
1192                 };
1193
1194                 i2c6 {
1195                         i2c6_xfer: i2c6-xfer {
1196                                 rockchip,pins =
1197                                         <2 10 RK_FUNC_2 &pcfg_pull_none>,
1198                                         <2 9 RK_FUNC_2 &pcfg_pull_none>;
1199                         };
1200                 };
1201
1202                 i2c7 {
1203                         i2c7_xfer: i2c7-xfer {
1204                                 rockchip,pins =
1205                                         <2 8 RK_FUNC_2 &pcfg_pull_none>,
1206                                         <2 7 RK_FUNC_2 &pcfg_pull_none>;
1207                         };
1208                 };
1209
1210                 i2c8 {
1211                         i2c8_xfer: i2c8-xfer {
1212                                 rockchip,pins =
1213                                         <1 21 RK_FUNC_1 &pcfg_pull_none>,
1214                                         <1 20 RK_FUNC_1 &pcfg_pull_none>;
1215                         };
1216                 };
1217
1218                 i2s0 {
1219                         i2s0_8ch_bus: i2s0-8ch-bus {
1220                                 rockchip,pins =
1221                                         <3 24 RK_FUNC_1 &pcfg_pull_none>,
1222                                         <3 25 RK_FUNC_1 &pcfg_pull_none>,
1223                                         <3 26 RK_FUNC_1 &pcfg_pull_none>,
1224                                         <3 27 RK_FUNC_1 &pcfg_pull_none>,
1225                                         <3 28 RK_FUNC_1 &pcfg_pull_none>,
1226                                         <3 29 RK_FUNC_1 &pcfg_pull_none>,
1227                                         <3 30 RK_FUNC_1 &pcfg_pull_none>,
1228                                         <3 31 RK_FUNC_1 &pcfg_pull_none>,
1229                                         <4 0 RK_FUNC_1 &pcfg_pull_none>;
1230                         };
1231                 };
1232
1233                 i2s1 {
1234                         i2s1_2ch_bus: i2s1-2ch-bus {
1235                                 rockchip,pins =
1236                                         <4 3 RK_FUNC_1 &pcfg_pull_none>,
1237                                         <4 4 RK_FUNC_1 &pcfg_pull_none>,
1238                                         <4 5 RK_FUNC_1 &pcfg_pull_none>,
1239                                         <4 6 RK_FUNC_1 &pcfg_pull_none>,
1240                                         <4 7 RK_FUNC_1 &pcfg_pull_none>;
1241                         };
1242                 };
1243
1244                 sdio0 {
1245                         sdio0_bus1: sdio0-bus1 {
1246                                 rockchip,pins =
1247                                         <2 20 RK_FUNC_1 &pcfg_pull_up>;
1248                         };
1249
1250                         sdio0_bus4: sdio0-bus4 {
1251                                 rockchip,pins =
1252                                         <2 20 RK_FUNC_1 &pcfg_pull_up>,
1253                                         <2 21 RK_FUNC_1 &pcfg_pull_up>,
1254                                         <2 22 RK_FUNC_1 &pcfg_pull_up>,
1255                                         <2 23 RK_FUNC_1 &pcfg_pull_up>;
1256                         };
1257
1258                         sdio0_cmd: sdio0-cmd {
1259                                 rockchip,pins =
1260                                         <2 24 RK_FUNC_1 &pcfg_pull_up>;
1261                         };
1262
1263                         sdio0_clk: sdio0-clk {
1264                                 rockchip,pins =
1265                                         <2 25 RK_FUNC_1 &pcfg_pull_none>;
1266                         };
1267
1268                         sdio0_cd: sdio0-cd {
1269                                 rockchip,pins =
1270                                         <2 26 RK_FUNC_1 &pcfg_pull_up>;
1271                         };
1272
1273                         sdio0_pwr: sdio0-pwr {
1274                                 rockchip,pins =
1275                                         <2 27 RK_FUNC_1 &pcfg_pull_up>;
1276                         };
1277
1278                         sdio0_bkpwr: sdio0-bkpwr {
1279                                 rockchip,pins =
1280                                         <2 28 RK_FUNC_1 &pcfg_pull_up>;
1281                         };
1282
1283                         sdio0_wp: sdio0-wp {
1284                                 rockchip,pins =
1285                                         <0 3 RK_FUNC_1 &pcfg_pull_up>;
1286                         };
1287
1288                         sdio0_int: sdio0-int {
1289                                 rockchip,pins =
1290                                         <0 4 RK_FUNC_1 &pcfg_pull_up>;
1291                         };
1292                 };
1293
1294                 sdmmc {
1295                         sdmmc_bus1: sdmmc-bus1 {
1296                                 rockchip,pins =
1297                                         <4 8 RK_FUNC_1 &pcfg_pull_up>;
1298                         };
1299
1300                         sdmmc_bus4: sdmmc-bus4 {
1301                                 rockchip,pins =
1302                                         <4 8 RK_FUNC_1 &pcfg_pull_up>,
1303                                         <4 9 RK_FUNC_1 &pcfg_pull_up>,
1304                                         <4 10 RK_FUNC_1 &pcfg_pull_up>,
1305                                         <4 11 RK_FUNC_1 &pcfg_pull_up>;
1306                         };
1307
1308                         sdmmc_clk: sdmmc-clk {
1309                                 rockchip,pins =
1310                                         <4 12 RK_FUNC_1 &pcfg_pull_none>;
1311                         };
1312
1313                         sdmmc_cmd: sdmmc-cmd {
1314                                 rockchip,pins =
1315                                         <4 13 RK_FUNC_1 &pcfg_pull_up>;
1316                         };
1317
1318                         sdmmc_cd: sdmcc-cd {
1319                                 rockchip,pins =
1320                                         <0 7 RK_FUNC_1 &pcfg_pull_up>;
1321                         };
1322
1323                         sdmmc_wp: sdmmc-wp {
1324                                 rockchip,pins =
1325                                         <0 8 RK_FUNC_1 &pcfg_pull_up>;
1326                         };
1327                 };
1328
1329                 spdif {
1330                         spdif_bus: spdif-bus {
1331                                 rockchip,pins =
1332                                         <4 21 RK_FUNC_1 &pcfg_pull_none>;
1333                         };
1334                 };
1335
1336                 spi0 {
1337                         spi0_clk: spi0-clk {
1338                                 rockchip,pins =
1339                                         <3 6 RK_FUNC_2 &pcfg_pull_up>;
1340                         };
1341                         spi0_cs0: spi0-cs0 {
1342                                 rockchip,pins =
1343                                         <3 7 RK_FUNC_2 &pcfg_pull_up>;
1344                         };
1345                         spi0_cs1: spi0-cs1 {
1346                                 rockchip,pins =
1347                                         <3 8 RK_FUNC_2 &pcfg_pull_up>;
1348                         };
1349                         spi0_tx: spi0-tx {
1350                                 rockchip,pins =
1351                                         <3 5 RK_FUNC_2 &pcfg_pull_up>;
1352                         };
1353                         spi0_rx: spi0-rx {
1354                                 rockchip,pins =
1355                                         <3 4 RK_FUNC_2 &pcfg_pull_up>;
1356                         };
1357                 };
1358
1359                 spi1 {
1360                         spi1_clk: spi1-clk {
1361                                 rockchip,pins =
1362                                         <1 9 RK_FUNC_2 &pcfg_pull_up>;
1363                         };
1364                         spi1_cs0: spi1-cs0 {
1365                                 rockchip,pins =
1366                                         <1 10 RK_FUNC_2 &pcfg_pull_up>;
1367                         };
1368                         spi1_rx: spi1-rx {
1369                                 rockchip,pins =
1370                                         <1 7 RK_FUNC_2 &pcfg_pull_up>;
1371                         };
1372                         spi1_tx: spi1-tx {
1373                                 rockchip,pins =
1374                                         <1 8 RK_FUNC_2 &pcfg_pull_up>;
1375                         };
1376                 };
1377
1378                 spi2 {
1379                         spi2_clk: spi2-clk {
1380                                 rockchip,pins =
1381                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
1382                         };
1383                         spi2_cs0: spi2-cs0 {
1384                                 rockchip,pins =
1385                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
1386                         };
1387                         spi2_rx: spi2-rx {
1388                                 rockchip,pins =
1389                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
1390                         };
1391                         spi2_tx: spi2-tx {
1392                                 rockchip,pins =
1393                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
1394                         };
1395                 };
1396
1397                 spi3 {
1398                         spi3_clk: spi3-clk {
1399                                 rockchip,pins =
1400                                         <1 17 RK_FUNC_1 &pcfg_pull_up>;
1401                         };
1402                         spi3_cs0: spi3-cs0 {
1403                                 rockchip,pins =
1404                                         <1 18 RK_FUNC_1 &pcfg_pull_up>;
1405                         };
1406                         spi3_rx: spi3-rx {
1407                                 rockchip,pins =
1408                                         <1 15 RK_FUNC_1 &pcfg_pull_up>;
1409                         };
1410                         spi3_tx: spi3-tx {
1411                                 rockchip,pins =
1412                                         <1 16 RK_FUNC_1 &pcfg_pull_up>;
1413                         };
1414                 };
1415
1416                 spi4 {
1417                         spi4_clk: spi4-clk {
1418                                 rockchip,pins =
1419                                         <3 2 RK_FUNC_2 &pcfg_pull_up>;
1420                         };
1421                         spi4_cs0: spi4-cs0 {
1422                                 rockchip,pins =
1423                                         <3 3 RK_FUNC_2 &pcfg_pull_up>;
1424                         };
1425                         spi4_rx: spi4-rx {
1426                                 rockchip,pins =
1427                                         <3 0 RK_FUNC_2 &pcfg_pull_up>;
1428                         };
1429                         spi4_tx: spi4-tx {
1430                                 rockchip,pins =
1431                                         <3 1 RK_FUNC_2 &pcfg_pull_up>;
1432                         };
1433                 };
1434
1435                 spi5 {
1436                         spi5_clk: spi5-clk {
1437                                 rockchip,pins =
1438                                         <2 22 RK_FUNC_2 &pcfg_pull_up>;
1439                         };
1440                         spi5_cs0: spi5-cs0 {
1441                                 rockchip,pins =
1442                                         <2 23 RK_FUNC_2 &pcfg_pull_up>;
1443                         };
1444                         spi5_rx: spi5-rx {
1445                                 rockchip,pins =
1446                                         <2 20 RK_FUNC_2 &pcfg_pull_up>;
1447                         };
1448                         spi5_tx: spi5-tx {
1449                                 rockchip,pins =
1450                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
1451                         };
1452                 };
1453
1454                 tsadc {
1455                         otp_gpio: otp-gpio {
1456                                 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
1457                         };
1458
1459                         otp_out: otp-out {
1460                                 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
1461                         };
1462                 };
1463
1464                 uart0 {
1465                         uart0_xfer: uart0-xfer {
1466                                 rockchip,pins =
1467                                         <2 16 RK_FUNC_1 &pcfg_pull_up>,
1468                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
1469                         };
1470
1471                         uart0_cts: uart0-cts {
1472                                 rockchip,pins =
1473                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
1474                         };
1475
1476                         uart0_rts: uart0-rts {
1477                                 rockchip,pins =
1478                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
1479                         };
1480                 };
1481
1482                 uart1 {
1483                         uart1_xfer: uart1-xfer {
1484                                 rockchip,pins =
1485                                         <3 12 RK_FUNC_2 &pcfg_pull_up>,
1486                                         <3 13 RK_FUNC_2 &pcfg_pull_none>;
1487                         };
1488                 };
1489
1490                 uart2a {
1491                         uart2a_xfer: uart2a-xfer {
1492                                 rockchip,pins =
1493                                         <4 8 RK_FUNC_2 &pcfg_pull_up>,
1494                                         <4 9 RK_FUNC_2 &pcfg_pull_none>;
1495                         };
1496                 };
1497
1498                 uart2b {
1499                         uart2b_xfer: uart2b-xfer {
1500                                 rockchip,pins =
1501                                         <4 16 RK_FUNC_2 &pcfg_pull_up>,
1502                                         <4 17 RK_FUNC_2 &pcfg_pull_none>;
1503                         };
1504                 };
1505
1506                 uart2c {
1507                         uart2c_xfer: uart2c-xfer {
1508                                 rockchip,pins =
1509                                         <4 19 RK_FUNC_1 &pcfg_pull_up>,
1510                                         <4 20 RK_FUNC_1 &pcfg_pull_none>;
1511                         };
1512                 };
1513
1514                 uart3 {
1515                         uart3_xfer: uart3-xfer {
1516                                 rockchip,pins =
1517                                         <3 14 RK_FUNC_2 &pcfg_pull_up>,
1518                                         <3 15 RK_FUNC_2 &pcfg_pull_none>;
1519                         };
1520
1521                         uart3_cts: uart3-cts {
1522                                 rockchip,pins =
1523                                         <3 18 RK_FUNC_2 &pcfg_pull_none>;
1524                         };
1525
1526                         uart3_rts: uart3-rts {
1527                                 rockchip,pins =
1528                                         <3 19 RK_FUNC_2 &pcfg_pull_none>;
1529                         };
1530                 };
1531
1532                 uart4 {
1533                         uart4_xfer: uart4-xfer {
1534                                 rockchip,pins =
1535                                         <1 7 RK_FUNC_1 &pcfg_pull_up>,
1536                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
1537                         };
1538                 };
1539
1540                 uarthdcp {
1541                         uarthdcp_xfer: uarthdcp-xfer {
1542                                 rockchip,pins =
1543                                         <4 21 RK_FUNC_2 &pcfg_pull_up>,
1544                                         <4 22 RK_FUNC_2 &pcfg_pull_none>;
1545                         };
1546                 };
1547
1548                 pwm0 {
1549                         pwm0_pin: pwm0-pin {
1550                                 rockchip,pins =
1551                                         <4 18 RK_FUNC_1 &pcfg_pull_none>;
1552                         };
1553
1554                         vop0_pwm_pin: vop0-pwm-pin {
1555                                 rockchip,pins =
1556                                         <4 18 RK_FUNC_2 &pcfg_pull_none>;
1557                         };
1558                 };
1559
1560                 pwm1 {
1561                         pwm1_pin: pwm1-pin {
1562                                 rockchip,pins =
1563                                         <4 22 RK_FUNC_1 &pcfg_pull_none>;
1564                         };
1565
1566                         vop1_pwm_pin: vop1-pwm-pin {
1567                                 rockchip,pins =
1568                                         <4 18 RK_FUNC_3 &pcfg_pull_none>;
1569                         };
1570                 };
1571
1572                 pwm2 {
1573                         pwm2_pin: pwm2-pin {
1574                                 rockchip,pins =
1575                                         <1 19 RK_FUNC_1 &pcfg_pull_none>;
1576                         };
1577                 };
1578
1579                 pwm3a {
1580                         pwm3a_pin: pwm3a-pin {
1581                                 rockchip,pins =
1582                                         <0 6 RK_FUNC_1 &pcfg_pull_none>;
1583                         };
1584                 };
1585
1586                 pwm3b {
1587                         pwm3b_pin: pwm3b-pin {
1588                                 rockchip,pins =
1589                                         <1 14 RK_FUNC_1 &pcfg_pull_none>;
1590                         };
1591                 };
1592
1593                 pmic {
1594                         pmic_int_l: pmic-int-l {
1595                                 rockchip,pins =
1596                                         <1 21 RK_FUNC_GPIO &pcfg_pull_up>;
1597                         };
1598                 };
1599         };
1600 };