arch/arm64/boot/dts/rockchip/rk3399.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3399-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/interrupt-controller/irq.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/power/rk3399-power.h>
  49 #include <dt-bindings/thermal/thermal.h>
  50
  51 / {
  52         compatible = "rockchip,rk3399";
  53         interrupt-parent = <&gic>;
  54         #address-cells = <2>;
  55         #size-cells = <2>;
  56
  57         aliases {
  58                 i2c0 = &i2c0;
  59                 i2c1 = &i2c1;
  60                 i2c2 = &i2c2;
  61                 i2c3 = &i2c3;
  62                 i2c4 = &i2c4;
  63                 i2c5 = &i2c5;
  64                 i2c6 = &i2c6;
  65                 i2c7 = &i2c7;
  66                 i2c8 = &i2c8;
  67                 serial0 = &uart0;
  68                 serial1 = &uart1;
  69                 serial2 = &uart2;
  70                 serial3 = &uart3;
  71                 serial4 = &uart4;
  72         };
  73
  74         psci {
  75                 compatible = "arm,psci-1.0";
  76                 method = "smc";
  77         };
  78
  79         cpus {
  80                 #address-cells = <2>;
  81                 #size-cells = <0>;
  82
  83                 cpu-map {
  84                         cluster0 {
  85                                 core0 {
  86                                         cpu = <&cpu_l0>;
  87                                 };
  88                                 core1 {
  89                                         cpu = <&cpu_l1>;
  90                                 };
  91                                 core2 {
  92                                         cpu = <&cpu_l2>;
  93                                 };
  94                                 core3 {
  95                                         cpu = <&cpu_l3>;
  96                                 };
  97                         };
  98
  99                         cluster1 {
 100                                 core0 {
 101                                         cpu = <&cpu_b0>;
 102                                 };
 103                                 core1 {
 104                                         cpu = <&cpu_b1>;
 105                                 };
 106                         };
 107                 };
 108
 109                 cpu_l0: cpu@0 {
 110                         device_type = "cpu";
 111                         compatible = "arm,cortex-a53", "arm,armv8";
 112                         reg = <0x0 0x0>;
 113                         enable-method = "psci";
 114                         #cooling-cells = <2>; /* min followed by max */
 115                         clocks = <&cru ARMCLKL>;
 116                         operating-points-v2 = <&cluster0_opp>;
 117                 };
 118
 119                 cpu_l1: cpu@1 {
 120                         device_type = "cpu";
 121                         compatible = "arm,cortex-a53", "arm,armv8";
 122                         reg = <0x0 0x1>;
 123                         enable-method = "psci";
 124                         clocks = <&cru ARMCLKL>;
 125                         operating-points-v2 = <&cluster0_opp>;
 126                 };
 127
 128                 cpu_l2: cpu@2 {
 129                         device_type = "cpu";
 130                         compatible = "arm,cortex-a53", "arm,armv8";
 131                         reg = <0x0 0x2>;
 132                         enable-method = "psci";
 133                         clocks = <&cru ARMCLKL>;
 134                         operating-points-v2 = <&cluster0_opp>;
 135                 };
 136
 137                 cpu_l3: cpu@3 {
 138                         device_type = "cpu";
 139                         compatible = "arm,cortex-a53", "arm,armv8";
 140                         reg = <0x0 0x3>;
 141                         enable-method = "psci";
 142                         clocks = <&cru ARMCLKL>;
 143                         operating-points-v2 = <&cluster0_opp>;
 144                 };
 145
 146                 cpu_b0: cpu@100 {
 147                         device_type = "cpu";
 148                         compatible = "arm,cortex-a72", "arm,armv8";
 149                         reg = <0x0 0x100>;
 150                         enable-method = "psci";
 151                         #cooling-cells = <2>; /* min followed by max */
 152                         clocks = <&cru ARMCLKB>;
 153                         operating-points-v2 = <&cluster1_opp>;
 154                 };
 155
 156                 cpu_b1: cpu@101 {
 157                         device_type = "cpu";
 158                         compatible = "arm,cortex-a72", "arm,armv8";
 159                         reg = <0x0 0x101>;
 160                         enable-method = "psci";
 161                         clocks = <&cru ARMCLKB>;
 162                         operating-points-v2 = <&cluster1_opp>;
 163                 };
 164         };
 165
 166         cluster0_opp: opp_table0 {
 167                 compatible = "operating-points-v2";
 168                 opp-shared;
 169
 170                 opp00 {
 171                         opp-hz = /bits/ 64 <408000000>;
 172                         opp-microvolt = <1000000>;
 173                         clock-latency-ns = <40000>;
 174                 };
 175                 opp01 {
 176                         opp-hz = /bits/ 64 <600000000>;
 177                         opp-microvolt = <1000000>;
 178                 };
 179                 opp02 {
 180                         opp-hz = /bits/ 64 <816000000>;
 181                         opp-microvolt = <1000000>;
 182                 };
 183                 opp03 {
 184                         opp-hz = /bits/ 64 <1008000000>;
 185                         opp-microvolt = <1000000>;
 186                 };
 187         };
 188
 189         cluster1_opp: opp_table1 {
 190                 compatible = "operating-points-v2";
 191                 opp-shared;
 192
 193                 opp00 {
 194                         opp-hz = /bits/ 64 <408000000>;
 195                         opp-microvolt = <1000000>;
 196                         clock-latency-ns = <40000>;
 197                 };
 198                 opp01 {
 199                         opp-hz = /bits/ 64 <600000000>;
 200                         opp-microvolt = <1000000>;
 201                 };
 202                 opp02 {
 203                         opp-hz = /bits/ 64 <816000000>;
 204                         opp-microvolt = <1000000>;
 205                 };
 206                 opp03 {
 207                         opp-hz = /bits/ 64 <1008000000>;
 208                         opp-microvolt = <1000000>;
 209                 };
 210                 opp04 {
 211                         opp-hz = /bits/ 64 <1200000000>;
 212                         opp-microvolt = <1000000>;
 213                 };
 214         };
 215
 216         timer {
 217                 compatible = "arm,armv8-timer";
 218                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
 219                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
 220                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
 221                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
 222         };
 223
 224         pmu_a53 {
 225                 compatible = "arm,cortex-a53-pmu";
 226                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
 227                 interrupt-affinity = <&cpu_l0>,
 228                                      <&cpu_l1>,
 229                                      <&cpu_l2>,
 230                                      <&cpu_l3>;
 231         };
 232
 233         pmu_a72 {
 234                 compatible = "arm,cortex-a72-pmu", "arm,cortex-a57-pmu";
 235                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
 236                 interrupt-affinity = <&cpu_b0>,
 237                                      <&cpu_b1>;
 238         };
 239
 240         xin24m: xin24m {
 241                 compatible = "fixed-clock";
 242                 #clock-cells = <0>;
 243                 clock-frequency = <24000000>;
 244                 clock-output-names = "xin24m";
 245         };
 246
 247         amba {
 248                 compatible = "arm,amba-bus";
 249                 #address-cells = <2>;
 250                 #size-cells = <2>;
 251                 ranges;
 252
 253                 dmac_bus: dma-controller@ff6d0000 {
 254                         compatible = "arm,pl330", "arm,primecell";
 255                         reg = <0x0 0xff6d0000 0x0 0x4000>;
 256                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 257                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 258                         #dma-cells = <1>;
 259                         clocks = <&cru ACLK_DMAC0_PERILP>;
 260                         clock-names = "apb_pclk";
 261                 };
 262
 263                 dmac_peri: dma-controller@ff6e0000 {
 264                         compatible = "arm,pl330", "arm,primecell";
 265                         reg = <0x0 0xff6e0000 0x0 0x4000>;
 266                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 267                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 268                         #dma-cells = <1>;
 269                         clocks = <&cru ACLK_DMAC1_PERILP>;
 270                         clock-names = "apb_pclk";
 271                 };
 272         };
 273
 274         gmac: eth@fe300000 {
 275                 compatible = "rockchip,rk3399-gmac";
 276                 reg = <0x0 0xfe300000 0x0 0x10000>;
 277                 rockchip,grf = <&grf>;
 278                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 279                 interrupt-names = "macirq";
 280                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
 281                          <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
 282                          <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
 283                          <&cru PCLK_GMAC>;
 284                 clock-names = "stmmaceth", "mac_clk_rx",
 285                               "mac_clk_tx", "clk_mac_ref",
 286                               "clk_mac_refout", "aclk_mac",
 287                               "pclk_mac";
 288                 resets = <&cru SRST_A_GMAC>;
 289                 reset-names = "stmmaceth";
 290                 status = "disabled";
 291         };
 292
 293         emmc_phy: phy {
 294                 compatible = "rockchip,rk3399-emmc-phy";
 295                 reg-offset = <0xf780>;
 296                 #phy-cells = <0>;
 297                 rockchip,grf = <&grf>;
 298                 status = "disabled";
 299         };
 300
 301         sdio0: dwmmc@fe310000 {
 302                 compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc";
 303                 reg = <0x0 0xfe310000 0x0 0x4000>;
 304                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 305                 clock-freq-min-max = <400000 150000000>;
 306                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 307                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 308                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 309                 fifo-depth = <0x100>;
 310                 status = "disabled";
 311         };
 312
 313         sdmmc: dwmmc@fe320000 {
 314                 compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc";
 315                 reg = <0x0 0xfe320000 0x0 0x4000>;
 316                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 317                 clock-freq-min-max = <400000 150000000>;
 318                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 319                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 320                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 321                 fifo-depth = <0x100>;
 322                 status = "disabled";
 323         };
 324
 325         sdhci: sdhci@fe330000 {
 326                 compatible = "arasan,sdhci-5.1";
 327                 reg = <0x0 0xfe330000 0x0 0x10000>;
 328                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 329                 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
 330                 clock-names = "clk_xin", "clk_ahb";
 331                 phys = <&emmc_phy>;
 332                 phy-names = "phy_arasan";
 333                 status = "disabled";
 334         };
 335
 336         usb_host0_echi: usb@fe380000 {
 337                 compatible = "generic-ehci";
 338                 reg = <0x0 0xfe380000 0x0 0x20000>;
 339                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 340                 clocks = <&cru HCLK_HOST0>;
 341                 clock-names = "hclk_host0";
 342                 status = "disabled";
 343         };
 344
 345         usb_host0_ohci: usb@fe3a0000 {
 346                 compatible = "generic-ohci";
 347                 reg = <0x0 0xfe3a0000 0x0 0x20000>;
 348                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 349                 clocks = <&cru HCLK_HOST0>;
 350                 clock-names = "hclk_host0";
 351                 status = "disabled";
 352         };
 353
 354         usb_host1_echi: usb@fe3c0000 {
 355                 compatible = "generic-ehci";
 356                 reg = <0x0 0xfe3c0000 0x0 0x20000>;
 357                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 358                 clocks = <&cru HCLK_HOST1>;
 359                 clock-names = "hclk_host1";
 360                 status = "disabled";
 361         };
 362
 363         usb_host1_ohci: usb@fe3e0000 {
 364                 compatible = "generic-ohci";
 365                 reg = <0x0 0xfe3e0000 0x0 0x20000>;
 366                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 367                 clocks = <&cru HCLK_HOST1>;
 368                 clock-names = "hclk_host1";
 369                 status = "disabled";
 370         };
 371
 372         gic: interrupt-controller@fee00000 {
 373                 compatible = "arm,gic-v3";
 374                 #interrupt-cells = <3>;
 375                 #address-cells = <2>;
 376                 #size-cells = <2>;
 377                 ranges;
 378                 interrupt-controller;
 379
 380                 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
 381                       <0x0 0xfef00000 0 0xc0000>, /* GICR */
 382                       <0x0 0xfff00000 0 0x10000>, /* GICC */
 383                       <0x0 0xfff10000 0 0x10000>, /* GICH */
 384                       <0x0 0xfff20000 0 0x10000>; /* GICV */
 385                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 386                 its: interrupt-controller@fee20000 {
 387                         compatible = "arm,gic-v3-its";
 388                         msi-controller;
 389                         reg = <0x0 0xfee20000 0x0 0x20000>;
 390                 };
 391         };
 392
 393         saradc: saradc@ff100000 {
 394                 compatible = "rockchip,rk3399-saradc";
 395                 reg = <0x0 0xff100000 0x0 0x100>;
 396                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 397                 #io-channel-cells = <1>;
 398                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 399                 clock-names = "saradc", "apb_pclk";
 400                 status = "disabled";
 401         };
 402
 403         i2c0: i2c@ff3c0000 {
 404                 compatible = "rockchip,rk3399-i2c";
 405                 reg = <0x0 0xff3c0000 0x0 0x1000>;
 406                 clocks =  <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
 407                 clock-names = "i2c", "pclk";
 408                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 409                 pinctrl-names = "default";
 410                 pinctrl-0 = <&i2c0_xfer>;
 411                 #address-cells = <1>;
 412                 #size-cells = <0>;
 413                 status = "disabled";
 414         };
 415
 416         i2c1: i2c@ff110000 {
 417                 compatible = "rockchip,rk3399-i2c";
 418                 reg = <0x0 0xff110000 0x0 0x1000>;
 419                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 420                 clock-names = "i2c", "pclk";
 421                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 422                 pinctrl-names = "default";
 423                 pinctrl-0 = <&i2c1_xfer>;
 424                 #address-cells = <1>;
 425                 #size-cells = <0>;
 426                 status = "disabled";
 427         };
 428
 429         i2c2: i2c@ff120000 {
 430                 compatible = "rockchip,rk3399-i2c";
 431                 reg = <0x0 0xff120000 0x0 0x1000>;
 432                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 433                 clock-names = "i2c", "pclk";
 434                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 435                 pinctrl-names = "default";
 436                 pinctrl-0 = <&i2c2_xfer>;
 437                 #address-cells = <1>;
 438                 #size-cells = <0>;
 439                 status = "disabled";
 440         };
 441
 442         i2c3: i2c@ff130000 {
 443                 compatible = "rockchip,rk3399-i2c";
 444                 reg = <0x0 0xff130000 0x0 0x1000>;
 445                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 446                 clock-names = "i2c", "pclk";
 447                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 448                 pinctrl-names = "default";
 449                 pinctrl-0 = <&i2c3_xfer>;
 450                 #address-cells = <1>;
 451                 #size-cells = <0>;
 452                 status = "disabled";
 453         };
 454
 455         i2c5: i2c@ff140000 {
 456                 compatible = "rockchip,rk3399-i2c";
 457                 reg = <0x0 0xff140000 0x0 0x1000>;
 458                 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
 459                 clock-names = "i2c", "pclk";
 460                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 461                 pinctrl-names = "default";
 462                 pinctrl-0 = <&i2c5_xfer>;
 463                 #address-cells = <1>;
 464                 #size-cells = <0>;
 465                 status = "disabled";
 466         };
 467
 468         i2c6: i2c@ff150000 {
 469                 compatible = "rockchip,rk3399-i2c";
 470                 reg = <0x0 0xff150000 0x0 0x1000>;
 471                 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
 472                 clock-names = "i2c", "pclk";
 473                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 474                 pinctrl-names = "default";
 475                 pinctrl-0 = <&i2c6_xfer>;
 476                 #address-cells = <1>;
 477                 #size-cells = <0>;
 478                 status = "disabled";
 479         };
 480
 481         i2c7: i2c@ff160000 {
 482                 compatible = "rockchip,rk3399-i2c";
 483                 reg = <0x0 0xff160000 0x0 0x1000>;
 484                 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
 485                 clock-names = "i2c", "pclk";
 486                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 487                 pinctrl-names = "default";
 488                 pinctrl-0 = <&i2c7_xfer>;
 489                 #address-cells = <1>;
 490                 #size-cells = <0>;
 491                 status = "disabled";
 492         };
 493
 494         uart0: serial@ff180000 {
 495                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 496                 reg = <0x0 0xff180000 0x0 0x100>;
 497                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 498                 clock-names = "baudclk", "apb_pclk";
 499                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 500                 reg-shift = <2>;
 501                 reg-io-width = <4>;
 502                 pinctrl-names = "default";
 503                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 504                 status = "disabled";
 505         };
 506
 507         uart1: serial@ff190000 {
 508                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 509                 reg = <0x0 0xff190000 0x0 0x100>;
 510                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 511                 clock-names = "baudclk", "apb_pclk";
 512                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 513                 reg-shift = <2>;
 514                 reg-io-width = <4>;
 515                 pinctrl-names = "default";
 516                 pinctrl-0 = <&uart1_xfer>;
 517                 status = "disabled";
 518         };
 519
 520         uart2: serial@ff1a0000 {
 521                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 522                 reg = <0x0 0xff1a0000 0x0 0x100>;
 523                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 524                 clock-names = "baudclk", "apb_pclk";
 525                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 526                 reg-shift = <2>;
 527                 reg-io-width = <4>;
 528                 pinctrl-names = "default";
 529                 pinctrl-0 = <&uart2c_xfer>;
 530                 status = "disabled";
 531         };
 532
 533         uart3: serial@ff1b0000 {
 534                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 535                 reg = <0x0 0xff1b0000 0x0 0x100>;
 536                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 537                 clock-names = "baudclk", "apb_pclk";
 538                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 539                 reg-shift = <2>;
 540                 reg-io-width = <4>;
 541                 pinctrl-names = "default";
 542                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 543                 status = "disabled";
 544         };
 545
 546         spi0: spi@ff1c0000 {
 547                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 548                 reg = <0x0 0xff1c0000 0x0 0x1000>;
 549                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 550                 clock-names = "spiclk", "apb_pclk";
 551                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 552                 pinctrl-names = "default";
 553                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 554                 #address-cells = <1>;
 555                 #size-cells = <0>;
 556                 status = "disabled";
 557         };
 558
 559         spi1: spi@ff1d0000 {
 560                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 561                 reg = <0x0 0xff1d0000 0x0 0x1000>;
 562                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 563                 clock-names = "spiclk", "apb_pclk";
 564                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 565                 pinctrl-names = "default";
 566                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 567                 #address-cells = <1>;
 568                 #size-cells = <0>;
 569                 status = "disabled";
 570         };
 571
 572         spi2: spi@ff1e0000 {
 573                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 574                 reg = <0x0 0xff1e0000 0x0 0x1000>;
 575                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 576                 clock-names = "spiclk", "apb_pclk";
 577                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 578                 pinctrl-names = "default";
 579                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 580                 #address-cells = <1>;
 581                 #size-cells = <0>;
 582                 status = "disabled";
 583         };
 584
 585         spi4: spi@ff1f0000 {
 586                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 587                 reg = <0x0 0xff1f0000 0x0 0x1000>;
 588                 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
 589                 clock-names = "spiclk", "apb_pclk";
 590                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 591                 pinctrl-names = "default";
 592                 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
 593                 #address-cells = <1>;
 594                 #size-cells = <0>;
 595                 status = "disabled";
 596         };
 597
 598         spi5: spi@ff200000 {
 599                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 600                 reg = <0x0 0xff200000 0x0 0x1000>;
 601                 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
 602                 clock-names = "spiclk", "apb_pclk";
 603                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
 604                 pinctrl-names = "default";
 605                 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
 606                 #address-cells = <1>;
 607                 #size-cells = <0>;
 608                 status = "disabled";
 609         };
 610
 611         thermal-zones {
 612                 #include "rk3368-thermal.dtsi"
 613         };
 614
 615         tsadc: tsadc@ff260000 {
 616                 compatible = "rockchip,rk3399-tsadc";
 617                 reg = <0x0 0xff260000 0x0 0x100>;
 618                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 619                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 620                 clock-names = "tsadc", "apb_pclk";
 621                 resets = <&cru SRST_TSADC>;
 622                 reset-names = "tsadc-apb";
 623                 pinctrl-names = "init", "default", "sleep";
 624                 pinctrl-0 = <&otp_gpio>;
 625                 pinctrl-1 = <&otp_out>;
 626                 pinctrl-2 = <&otp_gpio>;
 627                 #thermal-sensor-cells = <1>;
 628                 rockchip,hw-tshut-temp = <95000>;
 629                 status = "disabled";
 630         };
 631
 632         pmu: power-management@ff31000 {
 633                 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
 634                 reg = <0x0 0xff310000 0x0 0x1000>;
 635
 636                 power: power-controller {
 637                         status = "disabled";
 638                         compatible = "rockchip,rk3399-power-controller";
 639                         #power-domain-cells = <1>;
 640                         #address-cells = <1>;
 641                         #size-cells = <0>;
 642
 643                         pd_center {
 644                                 reg = <RK3399_PD_CENTER>;
 645                                 #address-cells = <1>;
 646                                 #size-cells = <0>;
 647
 648                                 pd_vdu {
 649                                         reg = <RK3399_PD_VDU>;
 650                                 };
 651                                 pd_vcodec {
 652                                         reg = <RK3399_PD_VCODEC>;
 653                                 };
 654                                 pd_iep {
 655                                         reg = <RK3399_PD_IEP>;
 656                                 };
 657                                 pd_rga {
 658                                         reg = <RK3399_PD_RGA>;
 659                                 };
 660                         };
 661                         pd_vio {
 662                                 reg = <RK3399_PD_VIO>;
 663                                 #address-cells = <1>;
 664                                 #size-cells = <0>;
 665
 666                                 pd_isp0 {
 667                                         reg = <RK3399_PD_ISP0>;
 668                                 };
 669                                 pd_isp1 {
 670                                         reg = <RK3399_PD_ISP1>;
 671                                 };
 672                                 pd_hdcp {
 673                                         reg = <RK3399_PD_HDCP>;
 674                                 };
 675                                 pd_vo {
 676                                         reg = <RK3399_PD_VO>;
 677                                         #address-cells = <1>;
 678                                         #size-cells = <0>;
 679
 680                                         pd_vopb {
 681                                                 reg = <RK3399_PD_VOPB>;
 682                                         };
 683                                         pd_vopl {
 684                                                 reg = <RK3399_PD_VOPL>;
 685                                         };
 686                                 };
 687                         };
 688                         pd_gpu {
 689                                 reg = <RK3399_PD_GPU>;
 690                         };
 691                 };
 692         };
 693
 694         pmugrf: syscon@ff320000 {
 695                 compatible = "rockchip,rk3399-pmugrf", "syscon";
 696                 reg = <0x0 0xff320000 0x0 0x1000>;
 697         };
 698
 699         spi3: spi@ff350000 {
 700                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 701                 reg = <0x0 0xff350000 0x0 0x1000>;
 702                 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
 703                 clock-names = "spiclk", "apb_pclk";
 704                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 705                 pinctrl-names = "default";
 706                 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
 707                 #address-cells = <1>;
 708                 #size-cells = <0>;
 709                 status = "disabled";
 710         };
 711
 712         uart4: serial@ff370000 {
 713                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 714                 reg = <0x0 0xff370000 0x0 0x100>;
 715                 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
 716                 clock-names = "baudclk", "apb_pclk";
 717                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 718                 reg-shift = <2>;
 719                 reg-io-width = <4>;
 720                 pinctrl-names = "default";
 721                 pinctrl-0 = <&uart4_xfer>;
 722                 status = "disabled";
 723         };
 724
 725         i2c4: i2c@ff3d0000 {
 726                 compatible = "rockchip,rk3399-i2c";
 727                 reg = <0x0 0xff3d0000 0x0 0x1000>;
 728                 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
 729                 clock-names = "i2c", "pclk";
 730                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 731                 pinctrl-names = "default";
 732                 pinctrl-0 = <&i2c4_xfer>;
 733                 #address-cells = <1>;
 734                 #size-cells = <0>;
 735                 status = "disabled";
 736         };
 737
 738         i2c8: i2c@ff3e0000 {
 739                 compatible = "rockchip,rk3399-i2c";
 740                 reg = <0x0 0xff3e0000 0x0 0x1000>;
 741                 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
 742                 clock-names = "i2c", "pclk";
 743                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 744                 pinctrl-names = "default";
 745                 pinctrl-0 = <&i2c8_xfer>;
 746                 #address-cells = <1>;
 747                 #size-cells = <0>;
 748                 status = "disabled";
 749         };
 750
 751         pwm0: pwm@ff420000 {
 752                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 753                 reg = <0x0 0xff420000 0x0 0x10>;
 754                 #pwm-cells = <3>;
 755                 pinctrl-names = "default";
 756                 pinctrl-0 = <&pwm0_pin>;
 757                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 758                 clock-names = "pwm";
 759                 status = "disabled";
 760         };
 761
 762         pwm1: pwm@ff420010 {
 763                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 764                 reg = <0x0 0xff420010 0x0 0x10>;
 765                 #pwm-cells = <3>;
 766                 pinctrl-names = "default";
 767                 pinctrl-0 = <&pwm1_pin>;
 768                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 769                 clock-names = "pwm";
 770                 status = "disabled";
 771         };
 772
 773         pwm2: pwm@ff420020 {
 774                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 775                 reg = <0x0 0xff420020 0x0 0x10>;
 776                 #pwm-cells = <3>;
 777                 pinctrl-names = "default";
 778                 pinctrl-0 = <&pwm2_pin>;
 779                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 780                 clock-names = "pwm";
 781                 status = "disabled";
 782         };
 783
 784         pwm3: pwm@ff420030 {
 785                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 786                 reg = <0x0 0xff420030 0x0 0x10>;
 787                 #pwm-cells = <3>;
 788                 pinctrl-names = "default";
 789                 pinctrl-0 = <&pwm3a_pin>;
 790                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 791                 clock-names = "pwm";
 792                 status = "disabled";
 793         };
 794
 795         pmucru: pmu-clock-controller@ff750000 {
 796                 compatible = "rockchip,rk3399-pmucru";
 797                 reg = <0x0 0xff750000 0x0 0x1000>;
 798                 rockchip,grf = <&pmugrf>;
 799                 #clock-cells = <1>;
 800                 #reset-cells = <1>;
 801                 assigned-clocks = <&pmucru PLL_PPLL>;
 802                 assigned-clock-rates = <676000000>;
 803         };
 804
 805         cru: clock-controller@ff760000 {
 806                 compatible = "rockchip,rk3399-cru";
 807                 reg = <0x0 0xff760000 0x0 0x1000>;
 808                 rockchip,grf = <&grf>;
 809                 #clock-cells = <1>;
 810                 #reset-cells = <1>;
 811                 assigned-clocks =
 812                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 813                         <&cru PLL_NPLL>,
 814                         <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
 815                         <&cru PCLK_PERIHP>,
 816                         <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
 817                         <&cru PCLK_PERILP0>,
 818                         <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
 819                 assigned-clock-rates =
 820                          <594000000>,  <800000000>,
 821                         <1000000000>,
 822                          <150000000>,   <75000000>,
 823                           <37500000>,
 824                          <100000000>,  <100000000>,
 825                           <50000000>,
 826                          <100000000>,   <50000000>;
 827         };
 828
 829         grf: syscon@ff770000 {
 830                 compatible = "rockchip,rk3399-grf", "syscon";
 831                 reg = <0x0 0xff770000 0x0 0x10000>;
 832         };
 833
 834         wdt0: watchdog@ff840000 {
 835                 compatible = "snps,dw-wdt";
 836                 reg = <0x0 0xff840000 0x0 0x100>;
 837                 clocks = <&cru PCLK_WDT>;
 838                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 839                 status = "disabled";
 840         };
 841
 842         spdif: spdif@ff870000 {
 843                 compatible = "rockchip,rk3399-spdif";
 844                 reg = <0x0 0xff870000 0x0 0x1000>;
 845                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 846                 dmas = <&dmac_bus 7>;
 847                 dma-names = "tx";
 848                 clock-names = "hclk", "mclk";
 849                 clocks = <&cru HCLK_SPDIF>, <&cru SCLK_SPDIF_8CH>;
 850                 pinctrl-names = "default";
 851                 pinctrl-0 = <&spdif_bus>;
 852                 status = "disabled";
 853         };
 854
 855         i2s0: i2s@ff880000 {
 856                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
 857                 reg = <0x0 0xff880000 0x0 0x1000>;
 858                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 859                 #address-cells = <1>;
 860                 #size-cells = <0>;
 861                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
 862                 dma-names = "tx", "rx";
 863                 clock-names = "i2s_hclk", "i2s_clk";
 864                 clocks = <&cru HCLK_I2S0_8CH>, <&cru SCLK_I2S0_8CH>;
 865                 pinctrl-names = "default";
 866                 pinctrl-0 = <&i2s0_8ch_bus>;
 867                 status = "disabled";
 868         };
 869
 870         i2s1: i2s@ff890000 {
 871                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
 872                 reg = <0x0 0xff890000 0x0 0x1000>;
 873                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 874                 #address-cells = <1>;
 875                 #size-cells = <0>;
 876                 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
 877                 dma-names = "tx", "rx";
 878                 clock-names = "i2s_hclk", "i2s_clk";
 879                 clocks = <&cru HCLK_I2S1_8CH>, <&cru SCLK_I2S1_8CH>;
 880                 pinctrl-names = "default";
 881                 pinctrl-0 = <&i2s1_2ch_bus>;
 882                 status = "disabled";
 883         };
 884
 885         i2s2: i2s@ff8a0000 {
 886                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
 887                 reg = <0x0 0xff8a0000 0x0 0x1000>;
 888                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 889                 #address-cells = <1>;
 890                 #size-cells = <0>;
 891                 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
 892                 dma-names = "tx", "rx";
 893                 clock-names = "i2s_hclk", "i2s_clk";
 894                 clocks = <&cru HCLK_I2S2_8CH>, <&cru SCLK_I2S2_8CH>;
 895                 status = "disabled";
 896         };
 897
 898         pinctrl: pinctrl {
 899                 compatible = "rockchip,rk3399-pinctrl";
 900                 rockchip,grf = <&grf>;
 901                 rockchip,pmu = <&pmugrf>;
 902                 #address-cells = <0x2>;
 903                 #size-cells = <0x2>;
 904                 ranges;
 905
 906                 gpio0: gpio0@ff720000 {
 907                         compatible = "rockchip,gpio-bank";
 908                         reg = <0x0 0xff720000 0x0 0x100>;
 909                         clocks = <&pmucru PCLK_GPIO0_PMU>;
 910                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 911
 912                         gpio-controller;
 913                         #gpio-cells = <0x2>;
 914
 915                         interrupt-controller;
 916                         #interrupt-cells = <0x2>;
 917                 };
 918
 919                 gpio1: gpio1@ff730000 {
 920                         compatible = "rockchip,gpio-bank";
 921                         reg = <0x0 0xff730000 0x0 0x100>;
 922                         clocks = <&pmucru PCLK_GPIO1_PMU>;
 923                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 924
 925                         gpio-controller;
 926                         #gpio-cells = <0x2>;
 927
 928                         interrupt-controller;
 929                         #interrupt-cells = <0x2>;
 930                 };
 931
 932                 gpio2: gpio2@ff780000 {
 933                         compatible = "rockchip,gpio-bank";
 934                         reg = <0x0 0xff780000 0x0 0x100>;
 935                         clocks = <&cru PCLK_GPIO2>;
 936                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 937
 938                         gpio-controller;
 939                         #gpio-cells = <0x2>;
 940
 941                         interrupt-controller;
 942                         #interrupt-cells = <0x2>;
 943                 };
 944
 945                 gpio3: gpio3@ff788000 {
 946                         compatible = "rockchip,gpio-bank";
 947                         reg = <0x0 0xff788000 0x0 0x100>;
 948                         clocks = <&cru PCLK_GPIO3>;
 949                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 950
 951                         gpio-controller;
 952                         #gpio-cells = <0x2>;
 953
 954                         interrupt-controller;
 955                         #interrupt-cells = <0x2>;
 956                 };
 957
 958                 gpio4: gpio4@ff790000 {
 959                         compatible = "rockchip,gpio-bank";
 960                         reg = <0x0 0xff790000 0x0 0x100>;
 961                         clocks = <&cru PCLK_GPIO4>;
 962                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 963
 964                         gpio-controller;
 965                         #gpio-cells = <0x2>;
 966
 967                         interrupt-controller;
 968                         #interrupt-cells = <0x2>;
 969                 };
 970
 971                 pcfg_pull_up: pcfg-pull-up {
 972                         bias-pull-up;
 973                 };
 974
 975                 pcfg_pull_down: pcfg-pull-down {
 976                         bias-pull-down;
 977                 };
 978
 979                 pcfg_pull_none: pcfg-pull-none {
 980                         bias-disable;
 981                 };
 982
 983                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
 984                         bias-disable;
 985                         drive-strength = <12>;
 986                 };
 987
 988                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
 989                         bias-pull-up;
 990                         drive-strength = <8>;
 991                 };
 992
 993                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
 994                         bias-pull-down;
 995                         drive-strength = <4>;
 996                 };
 997
 998                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
 999                         bias-pull-up;
1000                         drive-strength = <2>;
1001                 };
1002
1003                 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
1004                         bias-pull-down;
1005                         drive-strength = <12>;
1006                 };
1007
1008                 emmc {
1009                         emmc_pwr: emmc-pwr {
1010                                 rockchip,pins =
1011                                         <0 5 RK_FUNC_1 &pcfg_pull_up>;
1012                         };
1013                 };
1014
1015                 gmac {
1016                         rgmii_pins: rgmii-pins {
1017                                 rockchip,pins =
1018                                         /* mac_txclk */
1019                                         <3 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
1020                                         /* mac_rxclk */
1021                                         <3 14 RK_FUNC_1 &pcfg_pull_none>,
1022                                         /* mac_mdio */
1023                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
1024                                         /* mac_txen */
1025                                         <3 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1026                                         /* mac_clk */
1027                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
1028                                         /* mac_rxdv */
1029                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
1030                                         /* mac_mdc */
1031                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
1032                                         /* mac_rxd1 */
1033                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
1034                                         /* mac_rxd0 */
1035                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
1036                                         /* mac_txd1 */
1037                                         <3 5 RK_FUNC_1 &pcfg_pull_none_12ma>,
1038                                         /* mac_txd0 */
1039                                         <3 4 RK_FUNC_1 &pcfg_pull_none_12ma>,
1040                                         /* mac_rxd3 */
1041                                         <3 3 RK_FUNC_1 &pcfg_pull_none>,
1042                                         /* mac_rxd2 */
1043                                         <3 2 RK_FUNC_1 &pcfg_pull_none>,
1044                                         /* mac_txd3 */
1045                                         <3 1 RK_FUNC_1 &pcfg_pull_none_12ma>,
1046                                         /* mac_txd2 */
1047                                         <3 0 RK_FUNC_1 &pcfg_pull_none_12ma>;
1048                         };
1049
1050                         rmii_pins: rmii-pins {
1051                                 rockchip,pins =
1052                                         /* mac_mdio */
1053                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
1054                                         /* mac_txen */
1055                                         <3 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1056                                         /* mac_clk */
1057                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
1058                                         /* mac_rxer */
1059                                         <3 10 RK_FUNC_1 &pcfg_pull_none>,
1060                                         /* mac_rxdv */
1061                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
1062                                         /* mac_mdc */
1063                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
1064                                         /* mac_rxd1 */
1065                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
1066                                         /* mac_rxd0 */
1067                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
1068                                         /* mac_txd1 */
1069                                         <3 5 RK_FUNC_1 &pcfg_pull_none_12ma>,
1070                                         /* mac_txd0 */
1071                                         <3 4 RK_FUNC_1 &pcfg_pull_none_12ma>;
1072                         };
1073                 };
1074
1075                 i2c0 {
1076                         i2c0_xfer: i2c0-xfer {
1077                                 rockchip,pins =
1078                                         <1 15 RK_FUNC_2 &pcfg_pull_none>,
1079                                         <1 16 RK_FUNC_2 &pcfg_pull_none>;
1080                         };
1081                 };
1082
1083                 i2c1 {
1084                         i2c1_xfer: i2c1-xfer {
1085                                 rockchip,pins =
1086                                         <4 2 RK_FUNC_1 &pcfg_pull_none>,
1087                                         <4 1 RK_FUNC_1 &pcfg_pull_none>;
1088                         };
1089                 };
1090
1091                 i2c2 {
1092                         i2c2_xfer: i2c2-xfer {
1093                                 rockchip,pins =
1094                                         <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1095                                         <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
1096                         };
1097                 };
1098
1099                 i2c3 {
1100                         i2c3_xfer: i2c3-xfer {
1101                                 rockchip,pins =
1102                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
1103                                         <4 16 RK_FUNC_1 &pcfg_pull_none>;
1104                         };
1105                 };
1106
1107                 i2c4 {
1108                         i2c4_xfer: i2c4-xfer {
1109                                 rockchip,pins =
1110                                         <1 12 RK_FUNC_1 &pcfg_pull_none>,
1111                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
1112                         };
1113                 };
1114
1115                 i2c5 {
1116                         i2c5_xfer: i2c5-xfer {
1117                                 rockchip,pins =
1118                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
1119                                         <3 10 RK_FUNC_2 &pcfg_pull_none>;
1120                         };
1121                 };
1122
1123                 i2c6 {
1124                         i2c6_xfer: i2c6-xfer {
1125                                 rockchip,pins =
1126                                         <2 10 RK_FUNC_2 &pcfg_pull_none>,
1127                                         <2 9 RK_FUNC_2 &pcfg_pull_none>;
1128                         };
1129                 };
1130
1131                 i2c7 {
1132                         i2c7_xfer: i2c7-xfer {
1133                                 rockchip,pins =
1134                                         <2 8 RK_FUNC_2 &pcfg_pull_none>,
1135                                         <2 7 RK_FUNC_2 &pcfg_pull_none>;
1136                         };
1137                 };
1138
1139                 i2c8 {
1140                         i2c8_xfer: i2c8-xfer {
1141                                 rockchip,pins =
1142                                         <1 21 RK_FUNC_1 &pcfg_pull_none>,
1143                                         <1 20 RK_FUNC_1 &pcfg_pull_none>;
1144                         };
1145                 };
1146
1147                 i2s0 {
1148                         i2s0_8ch_bus: i2s0-8ch-bus {
1149                                 rockchip,pins =
1150                                         <3 24 RK_FUNC_1 &pcfg_pull_none>,
1151                                         <3 25 RK_FUNC_1 &pcfg_pull_none>,
1152                                         <3 26 RK_FUNC_1 &pcfg_pull_none>,
1153                                         <3 27 RK_FUNC_1 &pcfg_pull_none>,
1154                                         <3 28 RK_FUNC_1 &pcfg_pull_none>,
1155                                         <3 29 RK_FUNC_1 &pcfg_pull_none>,
1156                                         <3 30 RK_FUNC_1 &pcfg_pull_none>,
1157                                         <3 31 RK_FUNC_1 &pcfg_pull_none>,
1158                                         <4 0 RK_FUNC_1 &pcfg_pull_none>;
1159                         };
1160                 };
1161
1162                 i2s1 {
1163                         i2s1_2ch_bus: i2s1-2ch-bus {
1164                                 rockchip,pins =
1165                                         <4 3 RK_FUNC_1 &pcfg_pull_none>,
1166                                         <4 4 RK_FUNC_1 &pcfg_pull_none>,
1167                                         <4 5 RK_FUNC_1 &pcfg_pull_none>,
1168                                         <4 6 RK_FUNC_1 &pcfg_pull_none>,
1169                                         <4 7 RK_FUNC_1 &pcfg_pull_none>;
1170                         };
1171                 };
1172
1173                 sdio0 {
1174                         sdio0_bus1: sdio0-bus1 {
1175                                 rockchip,pins =
1176                                         <2 20 RK_FUNC_1 &pcfg_pull_up>;
1177                         };
1178
1179                         sdio0_bus4: sdio0-bus4 {
1180                                 rockchip,pins =
1181                                         <2 20 RK_FUNC_1 &pcfg_pull_up>,
1182                                         <2 21 RK_FUNC_1 &pcfg_pull_up>,
1183                                         <2 22 RK_FUNC_1 &pcfg_pull_up>,
1184                                         <2 23 RK_FUNC_1 &pcfg_pull_up>;
1185                         };
1186
1187                         sdio0_cmd: sdio0-cmd {
1188                                 rockchip,pins =
1189                                         <2 24 RK_FUNC_1 &pcfg_pull_up>;
1190                         };
1191
1192                         sdio0_clk: sdio0-clk {
1193                                 rockchip,pins =
1194                                         <2 25 RK_FUNC_1 &pcfg_pull_none>;
1195                         };
1196
1197                         sdio0_cd: sdio0-cd {
1198                                 rockchip,pins =
1199                                         <2 26 RK_FUNC_1 &pcfg_pull_up>;
1200                         };
1201
1202                         sdio0_pwr: sdio0-pwr {
1203                                 rockchip,pins =
1204                                         <2 27 RK_FUNC_1 &pcfg_pull_up>;
1205                         };
1206
1207                         sdio0_bkpwr: sdio0-bkpwr {
1208                                 rockchip,pins =
1209                                         <2 28 RK_FUNC_1 &pcfg_pull_up>;
1210                         };
1211
1212                         sdio0_wp: sdio0-wp {
1213                                 rockchip,pins =
1214                                         <0 3 RK_FUNC_1 &pcfg_pull_up>;
1215                         };
1216
1217                         sdio0_int: sdio0-int {
1218                                 rockchip,pins =
1219                                         <0 4 RK_FUNC_1 &pcfg_pull_up>;
1220                         };
1221                 };
1222
1223                 sdmmc {
1224                         sdmmc_bus1: sdmmc-bus1 {
1225                                 rockchip,pins =
1226                                         <4 8 RK_FUNC_1 &pcfg_pull_up>;
1227                         };
1228
1229                         sdmmc_bus4: sdmmc-bus4 {
1230                                 rockchip,pins =
1231                                         <4 8 RK_FUNC_1 &pcfg_pull_up>,
1232                                         <4 9 RK_FUNC_1 &pcfg_pull_up>,
1233                                         <4 10 RK_FUNC_1 &pcfg_pull_up>,
1234                                         <4 11 RK_FUNC_1 &pcfg_pull_up>;
1235                         };
1236
1237                         sdmmc_clk: sdmmc-clk {
1238                                 rockchip,pins =
1239                                         <4 12 RK_FUNC_1 &pcfg_pull_none>;
1240                         };
1241
1242                         sdmmc_cmd: sdmmc-cmd {
1243                                 rockchip,pins =
1244                                         <4 13 RK_FUNC_1 &pcfg_pull_up>;
1245                         };
1246
1247                         sdmmc_cd: sdmcc-cd {
1248                                 rockchip,pins =
1249                                         <0 7 RK_FUNC_1 &pcfg_pull_up>;
1250                         };
1251
1252                         sdmmc_wp: sdmmc-wp {
1253                                 rockchip,pins =
1254                                         <0 8 RK_FUNC_1 &pcfg_pull_up>;
1255                         };
1256                 };
1257
1258                 spdif {
1259                         spdif_bus: spdif-bus {
1260                                 rockchip,pins =
1261                                         <4 21 RK_FUNC_1 &pcfg_pull_none>;
1262                         };
1263                 };
1264
1265                 spi0 {
1266                         spi0_clk: spi0-clk {
1267                                 rockchip,pins =
1268                                         <3 6 RK_FUNC_2 &pcfg_pull_up>;
1269                         };
1270                         spi0_cs0: spi0-cs0 {
1271                                 rockchip,pins =
1272                                         <3 7 RK_FUNC_2 &pcfg_pull_up>;
1273                         };
1274                         spi0_cs1: spi0-cs1 {
1275                                 rockchip,pins =
1276                                         <3 8 RK_FUNC_2 &pcfg_pull_up>;
1277                         };
1278                         spi0_tx: spi0-tx {
1279                                 rockchip,pins =
1280                                         <3 5 RK_FUNC_2 &pcfg_pull_up>;
1281                         };
1282                         spi0_rx: spi0-rx {
1283                                 rockchip,pins =
1284                                         <3 4 RK_FUNC_2 &pcfg_pull_up>;
1285                         };
1286                 };
1287
1288                 spi1 {
1289                         spi1_clk: spi1-clk {
1290                                 rockchip,pins =
1291                                         <1 9 RK_FUNC_2 &pcfg_pull_up>;
1292                         };
1293                         spi1_cs0: spi1-cs0 {
1294                                 rockchip,pins =
1295                                         <1 10 RK_FUNC_2 &pcfg_pull_up>;
1296                         };
1297                         spi1_rx: spi1-rx {
1298                                 rockchip,pins =
1299                                         <1 7 RK_FUNC_2 &pcfg_pull_up>;
1300                         };
1301                         spi1_tx: spi1-tx {
1302                                 rockchip,pins =
1303                                         <1 8 RK_FUNC_2 &pcfg_pull_up>;
1304                         };
1305                 };
1306
1307                 spi2 {
1308                         spi2_clk: spi2-clk {
1309                                 rockchip,pins =
1310                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
1311                         };
1312                         spi2_cs0: spi2-cs0 {
1313                                 rockchip,pins =
1314                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
1315                         };
1316                         spi2_rx: spi2-rx {
1317                                 rockchip,pins =
1318                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
1319                         };
1320                         spi2_tx: spi2-tx {
1321                                 rockchip,pins =
1322                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
1323                         };
1324                 };
1325
1326                 spi3 {
1327                         spi3_clk: spi3-clk {
1328                                 rockchip,pins =
1329                                         <1 17 RK_FUNC_1 &pcfg_pull_up>;
1330                         };
1331                         spi3_cs0: spi3-cs0 {
1332                                 rockchip,pins =
1333                                         <1 18 RK_FUNC_1 &pcfg_pull_up>;
1334                         };
1335                         spi3_rx: spi3-rx {
1336                                 rockchip,pins =
1337                                         <1 15 RK_FUNC_1 &pcfg_pull_up>;
1338                         };
1339                         spi3_tx: spi3-tx {
1340                                 rockchip,pins =
1341                                         <1 16 RK_FUNC_1 &pcfg_pull_up>;
1342                         };
1343                 };
1344
1345                 spi4 {
1346                         spi4_clk: spi4-clk {
1347                                 rockchip,pins =
1348                                         <3 2 RK_FUNC_2 &pcfg_pull_up>;
1349                         };
1350                         spi4_cs0: spi4-cs0 {
1351                                 rockchip,pins =
1352                                         <3 3 RK_FUNC_2 &pcfg_pull_up>;
1353                         };
1354                         spi4_rx: spi4-rx {
1355                                 rockchip,pins =
1356                                         <3 0 RK_FUNC_2 &pcfg_pull_up>;
1357                         };
1358                         spi4_tx: spi4-tx {
1359                                 rockchip,pins =
1360                                         <3 1 RK_FUNC_2 &pcfg_pull_up>;
1361                         };
1362                 };
1363
1364                 spi5 {
1365                         spi5_clk: spi5-clk {
1366                                 rockchip,pins =
1367                                         <2 22 RK_FUNC_2 &pcfg_pull_up>;
1368                         };
1369                         spi5_cs0: spi5-cs0 {
1370                                 rockchip,pins =
1371                                         <2 23 RK_FUNC_2 &pcfg_pull_up>;
1372                         };
1373                         spi5_rx: spi5-rx {
1374                                 rockchip,pins =
1375                                         <2 20 RK_FUNC_2 &pcfg_pull_up>;
1376                         };
1377                         spi5_tx: spi5-tx {
1378                                 rockchip,pins =
1379                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
1380                         };
1381                 };
1382
1383                 tsadc {
1384                         otp_gpio: otp-gpio {
1385                                 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
1386                         };
1387
1388                         otp_out: otp-out {
1389                                 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
1390                         };
1391                 };
1392
1393                 uart0 {
1394                         uart0_xfer: uart0-xfer {
1395                                 rockchip,pins =
1396                                         <2 16 RK_FUNC_1 &pcfg_pull_up>,
1397                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
1398                         };
1399
1400                         uart0_cts: uart0-cts {
1401                                 rockchip,pins =
1402                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
1403                         };
1404
1405                         uart0_rts: uart0-rts {
1406                                 rockchip,pins =
1407                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
1408                         };
1409                 };
1410
1411                 uart1 {
1412                         uart1_xfer: uart1-xfer {
1413                                 rockchip,pins =
1414                                         <3 12 RK_FUNC_2 &pcfg_pull_up>,
1415                                         <3 13 RK_FUNC_2 &pcfg_pull_none>;
1416                         };
1417                 };
1418
1419                 uart2a {
1420                         uart2a_xfer: uart2a-xfer {
1421                                 rockchip,pins =
1422                                         <4 8 RK_FUNC_2 &pcfg_pull_up>,
1423                                         <4 9 RK_FUNC_2 &pcfg_pull_none>;
1424                         };
1425                 };
1426
1427                 uart2b {
1428                         uart2b_xfer: uart2b-xfer {
1429                                 rockchip,pins =
1430                                         <4 16 RK_FUNC_2 &pcfg_pull_up>,
1431                                         <4 17 RK_FUNC_2 &pcfg_pull_none>;
1432                         };
1433                 };
1434
1435                 uart2c {
1436                         uart2c_xfer: uart2c-xfer {
1437                                 rockchip,pins =
1438                                         <4 19 RK_FUNC_1 &pcfg_pull_up>,
1439                                         <4 20 RK_FUNC_1 &pcfg_pull_none>;
1440                         };
1441                 };
1442
1443                 uart3 {
1444                         uart3_xfer: uart3-xfer {
1445                                 rockchip,pins =
1446                                         <3 14 RK_FUNC_2 &pcfg_pull_up>,
1447                                         <3 15 RK_FUNC_2 &pcfg_pull_none>;
1448                         };
1449
1450                         uart3_cts: uart3-cts {
1451                                 rockchip,pins =
1452                                         <3 18 RK_FUNC_2 &pcfg_pull_none>;
1453                         };
1454
1455                         uart3_rts: uart3-rts {
1456                                 rockchip,pins =
1457                                         <3 19 RK_FUNC_2 &pcfg_pull_none>;
1458                         };
1459                 };
1460
1461                 uart4 {
1462                         uart4_xfer: uart4-xfer {
1463                                 rockchip,pins =
1464                                         <1 7 RK_FUNC_1 &pcfg_pull_up>,
1465                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
1466                         };
1467                 };
1468
1469                 uarthdcp {
1470                         uarthdcp_xfer: uarthdcp-xfer {
1471                                 rockchip,pins =
1472                                         <4 21 RK_FUNC_2 &pcfg_pull_up>,
1473                                         <4 22 RK_FUNC_2 &pcfg_pull_none>;
1474                         };
1475                 };
1476
1477                 pwm0 {
1478                         pwm0_pin: pwm0-pin {
1479                                 rockchip,pins =
1480                                         <4 18 RK_FUNC_1 &pcfg_pull_none>;
1481                         };
1482
1483                         vop0_pwm_pin: vop0-pwm-pin {
1484                                 rockchip,pins =
1485                                         <4 18 RK_FUNC_2 &pcfg_pull_none>;
1486                         };
1487                 };
1488
1489                 pwm1 {
1490                         pwm1_pin: pwm1-pin {
1491                                 rockchip,pins =
1492                                         <4 22 RK_FUNC_1 &pcfg_pull_none>;
1493                         };
1494
1495                         vop1_pwm_pin: vop1-pwm-pin {
1496                                 rockchip,pins =
1497                                         <4 18 RK_FUNC_3 &pcfg_pull_none>;
1498                         };
1499                 };
1500
1501                 pwm2 {
1502                         pwm2_pin: pwm2-pin {
1503                                 rockchip,pins =
1504                                         <1 19 RK_FUNC_1 &pcfg_pull_none>;
1505                         };
1506                 };
1507
1508                 pwm3a {
1509                         pwm3a_pin: pwm3a-pin {
1510                                 rockchip,pins =
1511                                         <0 6 RK_FUNC_1 &pcfg_pull_none>;
1512                         };
1513                 };
1514
1515                 pwm3b {
1516                         pwm3b_pin: pwm3b-pin {
1517                                 rockchip,pins =
1518                                         <1 14 RK_FUNC_1 &pcfg_pull_none>;
1519                         };
1520                 };
1521
1522                 pmic {
1523                         pmic_int_l: pmic-int-l {
1524                                 rockchip,pins =
1525                                         <1 21 RK_FUNC_GPIO &pcfg_pull_up>;
1526                         };
1527                 };
1528         };
1529 };