2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
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44 * This define is for support double show any dclk frequency.
45 * dclk_vop will have a exclusive pll as parent.
46 * set dclk_vop will change the pll rate as well.
49 #ifdef RK3399_TWO_PLL_FOR_VOP
52 assigned-clocks = <&cru SCLK_EMMC>;
53 assigned-clock-parents = <&cru PLL_GPLL>;
54 assigned-clock-rates = <200000000>;
58 assigned-clocks = <&cru SCLK_UART0_SRC>;
59 assigned-clock-parents = <&cru PLL_GPLL>;
63 assigned-clocks = <&cru SCLK_UART_SRC>;
64 assigned-clock-parents = <&cru PLL_GPLL>;
68 assigned-clocks = <&cru SCLK_UART_SRC>;
69 assigned-clock-parents = <&cru PLL_GPLL>;
73 assigned-clocks = <&cru SCLK_UART_SRC>;
74 assigned-clock-parents = <&cru PLL_GPLL>;
78 assigned-clocks = <&cru SCLK_UART_SRC>;
79 assigned-clock-parents = <&cru PLL_GPLL>;
83 assigned-clocks = <&cru SCLK_SPDIF_DIV>;
84 assigned-clock-parents = <&cru PLL_GPLL>;
88 assigned-clocks = <&cru SCLK_I2S0_DIV>;
89 assigned-clock-parents = <&cru PLL_GPLL>;
93 assigned-clocks = <&cru SCLK_I2S1_DIV>;
94 assigned-clock-parents = <&cru PLL_GPLL>;
98 assigned-clocks = <&cru SCLK_I2S2_DIV>;
99 assigned-clock-parents = <&cru PLL_GPLL>;
104 <&cru ACLK_PERIHP>, <&cru ACLK_PERILP0>,
105 <&cru HCLK_PERILP1>, <&cru ACLK_VOP0>,
106 <&cru ACLK_VOP1>, <&cru SCLK_SDMMC>,
107 <&cru ACLK_EMMC>, <&cru ACLK_CENTER>,
108 <&cru HCLK_SD>, <&cru SCLK_VDU_CA>,
109 <&cru SCLK_VDU_CORE>, <&cru ACLK_USB3>,
110 <&cru FCLK_CM0S>, <&cru ACLK_CCI>,
111 <&cru PCLK_ALIVE>, <&cru ACLK_GMAC>,
112 <&cru SCLK_CS>, <&cru SCLK_CCI_TRACE>,
113 <&cru ARMCLKL>, <&cru ARMCLKB>,
114 <&cru PLL_NPLL>, <&cru ACLK_GPU>,
115 <&cru PLL_GPLL>, <&cru ACLK_PERIHP>,
116 <&cru HCLK_PERIHP>, <&cru PCLK_PERIHP>,
117 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
118 <&cru PCLK_PERILP0>, <&cru HCLK_PERILP1>,
119 <&cru PCLK_PERILP1>, <&cru ACLK_VOP0>,
120 <&cru HCLK_VOP0>, <&cru ACLK_VOP1>,
121 <&cru HCLK_VOP1>, <&cru SCLK_I2C1>,
122 <&cru SCLK_I2C2>, <&cru SCLK_I2C3>,
123 <&cru SCLK_I2C5>, <&cru SCLK_I2C6>,
124 <&cru SCLK_I2C7>, <&cru SCLK_SPI0>,
125 <&cru SCLK_SPI1>, <&cru SCLK_SPI2>,
126 <&cru SCLK_SPI4>, <&cru SCLK_SPI5>,
127 <&cru ACLK_GIC>, <&cru ACLK_ISP0>,
128 <&cru ACLK_ISP1>, <&cru SCLK_VOP0_PWM>,
129 <&cru SCLK_VOP1_PWM>, <&cru PCLK_EDP>,
130 <&cru ACLK_HDCP>, <&cru ACLK_VIO>,
131 <&cru HCLK_SD>, <&cru SCLK_CRYPTO0>,
132 <&cru SCLK_CRYPTO1>, <&cru SCLK_EMMC>,
133 <&cru ACLK_EMMC>, <&cru ACLK_CENTER>,
134 <&cru ACLK_IEP>, <&cru ACLK_RGA>,
135 <&cru SCLK_RGA_CORE>, <&cru ACLK_VDU>,
136 <&cru ACLK_VCODEC>, <&cru PCLK_DDR>,
137 <&cru ACLK_GMAC>, <&cru SCLK_VDU_CA>,
138 <&cru SCLK_VDU_CORE>, <&cru ACLK_USB3>,
139 <&cru FCLK_CM0S>, <&cru ACLK_CCI>,
140 <&cru PCLK_ALIVE>, <&cru SCLK_CS>,
141 <&cru SCLK_CCI_TRACE>;
142 assigned-clock-rates =
143 <75000000>, <50000000>,
144 <50000000>, <200000000>,
145 <200000000>, <50000000>,
146 <50000000>, <100000000>,
147 <50000000>, <150000000>,
148 <150000000>, <150000000>,
149 <50000000>, <150000000>,
150 <50000000>, <100000000>,
151 <75000000>, <75000000>,
152 <816000000>, <816000000>,
153 <600000000>, <200000000>,
154 <800000000>, <150000000>,
155 <75000000>, <37500000>,
156 <100000000>, <100000000>,
157 <50000000>, <100000000>,
158 <50000000>, <400000000>,
159 <200000000>, <400000000>,
160 <200000000>, <100000000>,
161 <100000000>, <100000000>,
162 <100000000>, <100000000>,
163 <100000000>, <50000000>,
164 <50000000>, <50000000>,
165 <50000000>, <50000000>,
166 <200000000>, <400000000>,
167 <400000000>, <100000000>,
168 <100000000>, <100000000>,
169 <400000000>, <400000000>,
170 <200000000>, <100000000>,
171 <200000000>, <200000000>,
172 <100000000>, <400000000>,
173 <400000000>, <400000000>,
174 <400000000>, <300000000>,
175 <400000000>, <200000000>,
176 <400000000>, <300000000>,
177 <300000000>, <300000000>,
178 <300000000>, <300000000>,
179 <100000000>, <150000000>,