2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
42 #include <dt-bindings/memory/rk3399-dram.h>
45 ddr_timing: ddr_timing {
46 compatible = "rockchip,ddr-timing";
47 ddr3_speed_bin = <21>;
50 sr_mc_gate_idle = <0>;
53 dram_dll_dis_freq = <300>;
54 phy_dll_dis_freq = <125>;
56 ddr3_odt_dis_freq = <333>;
57 ddr3_drv = <DDR3_DS_40ohm>;
58 ddr3_odt = <DDR3_ODT_120ohm>;
59 phy_ddr3_ca_drv = <PHY_DRV_ODT_40>;
60 phy_ddr3_dq_drv = <PHY_DRV_ODT_40>;
61 phy_ddr3_odt = <PHY_DRV_ODT_240>;
63 lpddr3_odt_dis_freq = <333>;
64 lpddr3_drv = <LP3_DS_34ohm>;
65 lpddr3_odt = <LP3_ODT_240ohm>;
66 phy_lpddr3_ca_drv = <PHY_DRV_ODT_40>;
67 phy_lpddr3_dq_drv = <PHY_DRV_ODT_40>;
68 phy_lpddr3_odt = <PHY_DRV_ODT_240>;
70 lpddr4_odt_dis_freq = <333>;
71 lpddr4_drv = <LP4_PDDS_60ohm>;
72 lpddr4_dq_odt = <LP4_DQ_ODT_40ohm>;
73 lpddr4_ca_odt = <LP4_CA_ODT_40ohm>;
74 phy_lpddr4_ca_drv = <PHY_DRV_ODT_40>;
75 phy_lpddr4_ck_cs_drv = <PHY_DRV_ODT_80>;
76 phy_lpddr4_dq_drv = <PHY_DRV_ODT_80>;
77 phy_lpddr4_odt = <PHY_DRV_ODT_60>;