2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
45 #include <dt-bindings/pwm/pwm.h>
46 #include <dt-bindings/input/input.h>
47 #include "rk3399.dtsi"
48 #include "rk3399-android.dtsi"
51 model = "Rockchip RK3399 Box Board v1 (Android)";
52 compatible = "rockchip,rk3399";
54 vcc1v8_s0: vcc1v8-s0 {
55 compatible = "regulator-fixed";
56 regulator-name = "vcc1v8_s0";
57 regulator-min-microvolt = <1800000>;
58 regulator-max-microvolt = <1800000>;
63 compatible = "regulator-fixed";
64 regulator-name = "vcc_sys";
65 regulator-min-microvolt = <5000000>;
66 regulator-max-microvolt = <5000000>;
70 vcc_phy: vcc-phy-regulator {
71 compatible = "regulator-fixed";
72 regulator-name = "vcc_phy";
77 vcc3v3_sys: vcc3v3-sys {
78 compatible = "regulator-fixed";
79 regulator-name = "vcc3v3_sys";
80 regulator-min-microvolt = <3300000>;
81 regulator-max-microvolt = <3300000>;
83 vin-supply = <&vcc_sys>;
86 vcc5v0_host: vcc5v0-host-regulator {
87 compatible = "regulator-fixed";
89 gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>;
90 pinctrl-names = "default";
91 pinctrl-0 = <&host_vbus_drv>;
92 regulator-name = "vcc5v0_host";
95 vdd_center: vdd-center {
96 compatible = "pwm-regulator";
97 pwms = <&pwm2 0 25000 0>;
98 regulator-name = "vdd_center";
99 regulator-min-microvolt = <800000>;
100 regulator-max-microvolt = <1400000>;
104 /* for rockchip boot on */
105 rockchip,pwm_id= <2>;
106 rockchip,pwm_voltage = <900000>;
108 vin-supply = <&vcc_sys>;
111 clkin_gmac: external-gmac-clock {
112 compatible = "fixed-clock";
113 clock-frequency = <125000000>;
114 clock-output-names = "clkin_gmac";
119 compatible = "rockchip,rk3399-io-voltage-domain";
120 rockchip,grf = <&grf>;
122 bt656-supply = <&vcc1v8_s0>; /* bt656_gpio2ab_ms */
123 audio-supply = <&vcc1v8_s0>; /* audio_gpio3d4a_ms */
124 sdmmc-supply = <&vcc_sd>; /* sdmmc_gpio4b_ms */
125 gpio1830-supply = <&vcc_3v0>; /* gpio1833_gpio4cd_ms */
129 compatible = "rockchip,rk3399-pmu-io-voltage-domain";
130 rockchip,grf = <&pmugrf>;
132 pmu1830-supply = <&vcc_1v8>;
137 compatible = "simple-audio-card";
138 simple-audio-card,name = "ROCKCHIP,SPDIF";
139 simple-audio-card,cpu {
140 sound-dai = <&spdif>;
142 simple-audio-card,codec {
143 sound-dai = <&spdif_out>;
147 spdif_out: spdif-out {
149 compatible = "linux,spdif-dit";
150 #sound-dai-cells = <0>;
153 hdmi_sound: hdmi-sound {
155 compatible = "simple-audio-card";
156 simple-audio-card,format = "i2s";
157 simple-audio-card,mclk-fs = <256>;
158 simple-audio-card,name = "rockchip,hdmi";
159 simple-audio-card,cpu {
162 simple-audio-card,codec {
163 sound-dai = <&dw_hdmi_audio>;
167 dw_hdmi_audio: dw-hdmi-audio {
169 compatible = "rockchip,dw-hdmi-audio";
170 #sound-dai-cells = <0>;
173 sdio_pwrseq: sdio-pwrseq {
174 compatible = "mmc-pwrseq-simple";
176 clock-names = "ext_clock";
177 pinctrl-names = "default";
178 pinctrl-0 = <&wifi_enable_h>;
181 * On the module itself this is one of these (depending
182 * on the actual card populated):
183 * - SDIO_RESET_L_WL_REG_ON
184 * - PDN (power down when low)
186 reset-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
190 compatible = "wlan-platdata";
191 rockchip,grf = <&grf>;
192 wifi_chip_type = "ap6354";
194 WIFI,host_wake_irq = <&gpio0 3 GPIO_ACTIVE_HIGH>;
199 compatible = "bluetooth-platdata";
200 /* wifi-bt-power-toggle; */
201 uart_rts_gpios = <&gpio2 19 GPIO_ACTIVE_LOW>;
202 pinctrl-names = "default", "rts_gpio";
203 pinctrl-0 = <&uart0_rts>;
204 pinctrl-1 = <&uart0_gpios>;
205 /* BT,power_gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>; */
206 BT,reset_gpio = <&gpio0 9 GPIO_ACTIVE_HIGH>;
207 BT,wake_gpio = <&gpio2 26 GPIO_ACTIVE_HIGH>;
208 BT,wake_host_irq = <&gpio0 4 GPIO_ACTIVE_HIGH>;
214 clock-frequency = <150000000>;
215 clock-freq-min-max = <400000 150000000>;
223 vqmmc-supply = <&vcc_sd>;
224 pinctrl-names = "default";
225 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
230 clock-frequency = <140000000>;
231 clock-freq-min-max = <200000 140000000>;
237 keep-power-in-suspend;
238 mmc-pwrseq = <&sdio_pwrseq>;
241 pinctrl-names = "default";
242 pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
248 freq-sel = <200000000>;
259 mmc-hs400-enhanced-strobe;
265 rockchip,i2s-broken-burst-len;
266 rockchip,playback-channels = <8>;
267 rockchip,capture-channels = <8>;
268 #sound-dai-cells = <0>;
272 #sound-dai-cells = <0>;
276 pinctrl-0 = <&spdif_bus_1>;
278 #sound-dai-cells = <0>;
283 i2c-scl-rising-time-ns = <168>;
284 i2c-scl-falling-time-ns = <4>;
285 clock-frequency = <400000>;
287 vdd_cpu_b: syr827@40 {
288 compatible = "silergy,syr827";
290 regulator-compatible = "fan53555-reg";
291 regulator-name = "vdd_cpu_b";
292 regulator-min-microvolt = <712500>;
293 regulator-max-microvolt = <1500000>;
294 regulator-ramp-delay = <1000>;
295 fcs,suspend-voltage-selector = <1>;
298 regulator-initial-state = <3>;
299 vin-supply = <&vcc_sys>;
300 regulator-state-mem {
301 regulator-off-in-suspend;
306 compatible = "silergy,syr828";
308 regulator-compatible = "fan53555-reg";
309 regulator-name = "vdd_gpu";
310 regulator-min-microvolt = <735000>;
311 regulator-max-microvolt = <1400000>;
312 regulator-ramp-delay = <1000>;
313 fcs,suspend-voltage-selector = <1>;
316 vin-supply = <&vcc_sys>;
317 regulator-state-mem {
318 regulator-off-in-suspend;
323 compatible = "rockchip,rk808";
325 interrupt-parent = <&gpio1>;
326 interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
327 pinctrl-names = "default";
328 pinctrl-0 = <&pmic_int_l>;
329 rockchip,system-power-controller;
332 clock-output-names = "xin32k", "rk808-clkout2";
334 vcc1-supply = <&vcc_sys>;
335 vcc2-supply = <&vcc_sys>;
336 vcc3-supply = <&vcc_sys>;
337 vcc4-supply = <&vcc_sys>;
338 vcc6-supply = <&vcc_sys>;
339 vcc7-supply = <&vcc_sys>;
340 vcc8-supply = <&vcc3v3_sys>;
341 vcc9-supply = <&vcc_sys>;
342 vcc10-supply = <&vcc_sys>;
343 vcc11-supply = <&vcc_sys>;
344 vcc12-supply = <&vcc3v3_sys>;
345 vddio-supply = <&vcc_1v8>;
349 regulator-name = "vdd_log";
350 regulator-min-microvolt = <750000>;
351 regulator-max-microvolt = <1350000>;
354 regulator-state-mem {
355 regulator-on-in-suspend;
356 regulator-suspend-microvolt = <900000>;
360 vdd_cpu_l: DCDC_REG2 {
361 regulator-name = "vdd_cpu_l";
362 regulator-min-microvolt = <750000>;
363 regulator-max-microvolt = <1350000>;
366 regulator-state-mem {
367 regulator-off-in-suspend;
372 regulator-name = "vcc_ddr";
375 regulator-state-mem {
376 regulator-on-in-suspend;
381 regulator-name = "vcc_1v8";
382 regulator-min-microvolt = <1800000>;
383 regulator-max-microvolt = <1800000>;
386 regulator-state-mem {
387 regulator-on-in-suspend;
388 regulator-suspend-microvolt = <1800000>;
392 vcc1v8_dvp: LDO_REG1 {
393 regulator-name = "vcc1v8_dvp";
394 regulator-min-microvolt = <1800000>;
395 regulator-max-microvolt = <1800000>;
398 regulator-state-mem {
399 regulator-on-in-suspend;
400 regulator-suspend-microvolt = <1800000>;
404 vcc3v0_tp: LDO_REG2 {
405 regulator-name = "vcc3v0_tp";
406 regulator-min-microvolt = <3000000>;
407 regulator-max-microvolt = <3000000>;
410 regulator-state-mem {
411 regulator-off-in-suspend;
415 vcc1v8_pll: LDO_REG3 {
416 regulator-name = "vcc1v8_pll";
417 regulator-min-microvolt = <1800000>;
418 regulator-max-microvolt = <1800000>;
421 regulator-state-mem {
422 regulator-on-in-suspend;
423 regulator-suspend-microvolt = <1800000>;
428 regulator-name = "vcc_sd";
429 regulator-min-microvolt = <1800000>;
430 regulator-max-microvolt = <3300000>;
433 regulator-state-mem {
434 regulator-on-in-suspend;
435 regulator-suspend-microvolt = <3300000>;
439 vcc3v0_sd: LDO_REG5 {
440 regulator-name = "vcc3v0_sd";
441 regulator-min-microvolt = <3000000>;
442 regulator-max-microvolt = <3000000>;
445 regulator-state-mem {
446 regulator-on-in-suspend;
447 regulator-suspend-microvolt = <3000000>;
452 regulator-name = "vcc_1v5";
453 regulator-min-microvolt = <1500000>;
454 regulator-max-microvolt = <1500000>;
457 regulator-state-mem {
458 regulator-on-in-suspend;
459 regulator-suspend-microvolt = <1500000>;
464 regulator-name = "vcc_0v9a";
465 regulator-min-microvolt = <900000>;
466 regulator-max-microvolt = <900000>;
469 regulator-state-mem {
470 regulator-on-in-suspend;
471 regulator-suspend-microvolt = <900000>;
476 regulator-name = "vcc_3v0";
477 regulator-min-microvolt = <3000000>;
478 regulator-max-microvolt = <3000000>;
481 regulator-state-mem {
482 regulator-on-in-suspend;
483 regulator-suspend-microvolt = <3000000>;
487 vcc3v3_s3: SWITCH_REG1 {
488 regulator-name = "vcc3v3_s3";
491 regulator-state-mem {
492 regulator-on-in-suspend;
496 vcc3v3_s0: SWITCH_REG2 {
497 regulator-name = "vcc3v3_s0";
500 regulator-state-mem {
501 regulator-on-in-suspend;
509 cpu-supply = <&vdd_cpu_l>;
513 cpu-supply = <&vdd_cpu_l>;
517 cpu-supply = <&vdd_cpu_l>;
521 cpu-supply = <&vdd_cpu_l>;
525 cpu-supply = <&vdd_cpu_b>;
529 cpu-supply = <&vdd_cpu_b>;
534 mali-supply = <&vdd_gpu>;
542 /* tshut mode 0:CRU 1:GPIO */
543 rockchip,hw-tshut-mode = <1>;
544 /* tshut polarity 0:LOW 1:HIGH */
545 rockchip,hw-tshut-polarity = <1>;
552 u2phy0_otg: otg-port {
556 u2phy0_host: host-port {
557 phy-supply = <&vcc5v0_host>;
565 u2phy1_otg: otg-port {
569 u2phy1_host: host-port {
570 phy-supply = <&vcc5v0_host>;
576 pinctrl-names = "default";
577 pinctrl-0 = <&uart0_xfer &uart0_cts>;
606 dr_mode = "peripheral";
626 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH 0>;
627 compatible = "rockchip,remotectl-pwm";
632 rockchip,usercode = <0x4040>;
642 <0xe3 KEY_VOLUMEDOWN>,
659 rockchip,usercode = <0xff00>;
669 <0xeb KEY_VOLUMEDOWN>,
674 <0xa9 KEY_VOLUMEDOWN>,
675 <0xa8 KEY_VOLUMEDOWN>,
676 <0xe0 KEY_VOLUMEDOWN>,
677 <0xa5 KEY_VOLUMEDOWN>,
682 <0xed KEY_VOLUMEDOWN>,
684 <0xb3 KEY_VOLUMEDOWN>,
685 <0xf1 KEY_VOLUMEDOWN>,
686 <0xf2 KEY_VOLUMEDOWN>,
688 <0xb4 KEY_VOLUMEDOWN>,
693 rockchip,usercode = <0x1dcc>;
703 <0xfd KEY_VOLUMEDOWN>,
721 <0xb5 KEY_BACKSPACE>;
726 phy-supply = <&vcc_phy>;
728 clock_in_out = "input";
729 snps,reset-gpio = <&gpio3 15 GPIO_ACTIVE_LOW>;
730 snps,reset-active-low;
731 snps,reset-delays-us = <0 10000 50000>;
732 assigned-clocks = <&cru SCLK_RMII_SRC>;
733 assigned-clock-parents = <&clkin_gmac>;
734 pinctrl-names = "default";
735 pinctrl-0 = <&rgmii_pins>;
747 wifi_enable_h: wifi-enable-h {
748 rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>;
753 uart0_gpios: uart0-gpios {
754 rockchip,pins = <2 19 RK_FUNC_GPIO &pcfg_pull_none>;
759 pmic_int_l: pmic-int-l {
761 <1 21 RK_FUNC_GPIO &pcfg_pull_up>;
766 host_vbus_drv: host-vbus-drv {
768 <4 25 RK_FUNC_GPIO &pcfg_pull_none>;
774 #include <dt-bindings/display/screen-timing/lcd-box.dtsi>
782 rockchip,disp-mode = <NO_DUAL>;
783 rockchip,disp-policy = <DISPLAY_POLICY_BOX>;
788 rockchip,hdmi_video_source = <DISPLAY_SOURCE_LCDC0>;