2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
42 #include <dt-bindings/display/rk_fb.h>
43 #include <dt-bindings/display/mipi_dsi.h>
46 compatible = "rockchip,android", "rockchip,rk3399";
54 bootargs = "earlycon=uart8250,mmio32,0xff1a0000 swiotlb=1";
57 ramoops_mem: ramoops_mem {
58 reg = <0x0 0x110000 0x0 0xf0000>;
59 reg-names = "ramoops_mem";
63 compatible = "ramoops";
64 record-size = <0x0 0x20000>;
65 console-size = <0x0 0x80000>;
66 ftrace-size = <0x0 0x00000>;
67 pmsg-size = <0x0 0x50000>;
68 memory-region = <&ramoops_mem>;
71 fiq_debugger: fiq-debugger {
72 compatible = "rockchip,fiq-debugger";
73 rockchip,serial-id = <2>;
74 rockchip,signal-irq = <182>;
75 rockchip,wake-irq = <0>;
76 rockchip,irq-mode-enable = <1>; /* If enable uart uses irq instead of fiq */
77 rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */
78 pinctrl-names = "default";
79 pinctrl-0 = <&uart2c_xfer>;
87 /* global autoconfigured region for contiguous allocations */
89 compatible = "shared-dma-pool";
91 size = <0x0 0x8000000>;
94 /* reg = <0x0 0x0 0x0 0x0> will be updated by uboot */
95 rockchip_logo: rockchip-logo@00000000 {
96 compatible = "rockchip,fb-logo";
97 reg = <0x0 0x0 0x0 0x0>;
102 compatible = "rockchip,ion";
103 #address-cells = <1>;
107 reg = <0x00000000 0x02000000>;
114 rk_key: rockchip-key {
115 compatible = "rockchip,key";
118 io-channels = <&saradc 1>;
123 rockchip,adc_value = <1>;
128 label = "volume down";
129 rockchip,adc_value = <170>;
133 gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
142 rockchip,adc_value = <746>;
148 rockchip,adc_value = <355>;
154 rockchip,adc_value = <560>;
160 rockchip,adc_value = <450>;
164 cdn_dp_fb: dp-fb@fec00000 {
166 compatible = "rockchip,rk3399-cdn-dp-fb";
167 reg = <0x0 0xfec00000 0x0 0x100000>;
168 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
169 clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
170 <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
171 clock-names = "core-clk", "pclk", "spdif", "grf";
172 assigned-clocks = <&cru SCLK_DP_CORE>;
173 assigned-clock-rates = <100000000>;
174 power-domains = <&power RK3399_PD_HDCP>;
175 phys = <&tcphy0_dp>, <&tcphy1_dp>;
176 resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>,
177 <&cru SRST_P_UPHY0_APB>;
178 reset-names = "spdif", "dptx", "apb";
179 rockchip,grf = <&grf>;
180 #address-cells = <1>;
182 #sound-dai-cells = <1>;
185 cdn_dp_sound: cdn-dp-sound {
187 compatible = "simple-audio-card";
188 simple-audio-card,name = "rockchip,cdn-dp-fb";
189 simple-audio-card,widgets = "Headphone", "Out Jack",
192 simple-audio-card,dai-link@0 {
201 sound-dai = <&cdn_dp_fb 0>;
207 compatible = "rockchip,iep";
209 reg = <0x0 0xff670000 0x0 0x800>;
210 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
211 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
212 clock-names = "aclk_iep", "hclk_iep";
213 power-domains = <&power RK3399_PD_IEP>;
219 compatible = "rockchip,iep_mmu";
220 reg = <0x0 0xff670800 0x0 0x40>;
221 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
222 interrupt-names = "iep_mmu";
226 compatible = "rockchip,rga2";
228 reg = <0x0 0xff680000 0x0 0x1000>;
229 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
230 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
231 clock-names = "aclk_rga", "hclk_rga", "clk_rga";
232 power-domains = <&power RK3399_PD_RGA>;
238 compatible = "rockchip,rk-fb";
239 rockchip,disp-mode = <DUAL>;
240 rockchip,uboot-logo-on = <1>;
241 memory-region = <&rockchip_logo>;
246 compatible = "rockchip,screen";
249 vopb_rk_fb: vop-rk-fb@ff900000 {
251 compatible = "rockchip,rk3399-lcdc";
252 rockchip,prop = <PRMRY>;
253 reg = <0x0 0xff900000 0x0 0x3efc>;
254 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
255 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
256 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
257 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
258 reset-names = "axi", "ahb", "dclk";
259 rockchip,grf = <&grf>;
260 rockchip,pwr18 = <0>;
261 rockchip,iommu-enabled = <1>;
262 power-domains = <&power RK3399_PD_VOPB>;
266 vopb_mmu_rk_fb: vopb-mmu {
269 compatible = "rockchip,vopb_mmu";
270 reg = <0x0 0xff903f00 0x0 0x100>;
271 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
272 interrupt-names = "vopb_mmu";
275 vopl_rk_fb: vop-rk-fb@ff8f0000 {
277 compatible = "rockchip,rk3399-lcdc";
278 rockchip,prop = <EXTEND>;
279 reg = <0x0 0xff8f0000 0x0 0x3efc>;
280 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
281 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
282 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
283 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
284 reset-names = "axi", "ahb", "dclk";
285 rockchip,grf = <&grf>;
286 rockchip,pwr18 = <0>;
287 rockchip,iommu-enabled = <1>;
288 power-domains = <&power RK3399_PD_VOPL>;
292 vopl_mmu_rk_fb: vopl-mmu {
295 compatible = "rockchip,vopl_mmu";
296 reg = <0x0 0xff8f3f00 0x0 0x100>;
297 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
298 interrupt-names = "vopl_mmu";
301 cif_isp0: cif_isp@ff910000 {
302 compatible = "rockchip,rk3399-cif-isp";
303 rockchip,grf = <&grf>;
304 reg = <0x0 0xff910000 0x0 0x10000>, <0x0 0xff968000 0x0 0x8000>;
305 reg-names = "register", "dsihost-register";
307 <&cru SCLK_CIF_OUT>, <&cru SCLK_CIF_OUT>,
308 <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru SCLK_MIPIDPHY_REF>,
309 <&cru ACLK_ISP0_NOC>, <&cru ACLK_ISP0_WRAPPER>,
310 <&cru HCLK_ISP0_NOC>, <&cru HCLK_ISP0_WRAPPER>,
311 <&cru SCLK_ISP0>, <&cru SCLK_DPHY_RX0_CFG>;
313 "clk_cif_out", "clk_cif_pll",
314 "pclk_dphytxrx", "pclk_dphy_ref",
315 "aclk_isp0_noc", "aclk_isp0_wrapper",
316 "hclk_isp0_noc", "hclk_isp0_wrapper",
317 "clk_isp0", "pclk_dphyrx";
318 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
319 interrupt-names = "cif_isp10_irq";
320 power-domains = <&power RK3399_PD_ISP0>;
325 compatible = "rockchip,rk3399-isp", "rockchip,isp";
326 reg = <0x0 0xff910000 0x0 0x10000>;
327 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
329 <&cru SCLK_CIF_OUT>, <&cru SCLK_CIF_OUT>,
330 <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru SCLK_MIPIDPHY_REF>,
331 <&cru ACLK_ISP0_NOC>, <&cru ACLK_ISP0_WRAPPER>,
332 <&cru HCLK_ISP0_NOC>, <&cru HCLK_ISP0_WRAPPER>,
333 <&cru SCLK_ISP0>, <&cru SCLK_DPHY_RX0_CFG>;
335 "clk_cif_out", "clk_cif_pll",
336 "pclk_dphytxrx", "pclk_dphy_ref",
337 "aclk_isp0_noc", "aclk_isp0_wrapper",
338 "hclk_isp0_noc", "hclk_isp0_wrapper",
339 "clk_isp0", "pclk_dphyrx";
341 "cif_clkout","isp_dvp8bit0", "isp_mipi_fl",
342 "isp_mipi_fl_prefl", "isp_flash_as_gpio",
343 "isp_flash_as_trigger_out";
344 pinctrl-0 = <&cif_clkout>;
345 pinctrl-1 = <&isp_dvp_d0d7>;
346 pinctrl-2 = <&cif_clkout>;
347 pinctrl-3 = <&isp_prelight>;
348 pinctrl-4 = <&isp_flash_trigger_as_gpio>;
349 pinctrl-5 = <&isp_flash_trigger>;
350 rockchip,isp,mipiphy = <2>;
351 rockchip,isp,cifphy = <1>;
352 rockchip,isp,dsiphy,reg = <0xff968000 0x8000>;
353 rockchip,grf = <&grf>;
354 rockchip,cru = <&cru>;
355 rockchip,gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
356 rockchip,isp,iommu-enable = <1>;
357 power-domains = <&power RK3399_PD_ISP0>;
363 compatible = "rockchip,isp0_mmu";
364 reg = <0x0 0xff914000 0x0 0x100>,
365 <0x0 0xff915000 0x0 0x100>;
366 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
367 interrupt-names = "isp0_mmu";
371 compatible = "rockchip,rk3399-isp", "rockchip,isp";
372 reg = <0x0 0xff920000 0x0 0x10000>;
373 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
375 <&cru ACLK_ISP1_NOC>, <&cru ACLK_ISP1_WRAPPER>,
376 <&cru HCLK_ISP1_NOC>, <&cru HCLK_ISP1_WRAPPER>,
377 <&cru SCLK_ISP1>, <&cru SCLK_CIF_OUT>,
378 <&cru SCLK_CIF_OUT>, <&cru SCLK_DPHY_TX1RX1_CFG>,
379 <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_ISP1_WRAPPER>,
380 <&cru SCLK_DPHY_RX0_CFG>, <&cru PCLK_MIPI_DSI1>,
381 <&cru SCLK_MIPIDPHY_CFG>;
383 "aclk_isp1_noc", "aclk_isp1_wrapper",
384 "hclk_isp1_noc", "hclk_isp1_wrapper",
385 "clk_isp1", "clk_cif_out",
386 "clk_cif_pll", "pclk_dphytxrx",
387 "pclk_dphy_ref", "pclk_isp1",
388 "pclk_dphyrx", "pclk_mipi_dsi",
391 "cif_clkout","isp_dvp8bit0", "isp_mipi_fl",
392 "isp_mipi_fl_prefl", "isp_flash_as_gpio",
393 "isp_flash_as_trigger_out";
394 pinctrl-0 = <&cif_clkout>;
395 pinctrl-1 = <&isp_dvp_d0d7>;
396 pinctrl-2 = <&cif_clkout>;
397 pinctrl-3 = <&isp_prelight>;
398 pinctrl-4 = <&isp_flash_trigger_as_gpio>;
399 pinctrl-5 = <&isp_flash_trigger>;
400 rockchip,isp,mipiphy = <2>;
401 rockchip,isp,cifphy = <1>;
402 rockchip,isp,dsiphy,reg = <0xff968000 0x8000>;
403 rockchip,grf = <&grf>;
404 rockchip,cru = <&cru>;
405 rockchip,gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
406 rockchip,isp,iommu-enable = <1>;
407 power-domains = <&power RK3399_PD_ISP1>;
413 compatible = "rockchip,isp1_mmu";
414 reg = <0x0 0xff924000 0x0 0x100>,
415 <0x0 0xff925000 0x0 0x100>;
416 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
417 interrupt-names = "isp1_mmu";
420 hdmi_rk_fb: hdmi-rk-fb@ff940000 {
422 compatible = "rockchip,rk3399-hdmi";
423 reg = <0x0 0xff940000 0x0 0x20000>;
424 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>,
425 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH 0>;
426 clocks = <&cru PCLK_HDMI_CTRL>,
428 <&cru SCLK_HDMI_CEC>,
430 <&cru SCLK_HDMI_SFR>;
431 clock-names = "pclk_hdmi",
436 resets = <&cru SRST_HDMI_CTRL>;
437 reset-names = "hdmi";
438 pinctrl-names = "default", "gpio";
439 pinctrl-0 = <&hdmi_i2c_xfer &hdmi_cec>;
440 pinctrl-1 = <&i2c3_gpio>;
441 rockchip,grf = <&grf>;
442 power-domains = <&power RK3399_PD_HDCP>;
445 mipi0_rk_fb: mipi-rk-fb@ff960000 {
446 compatible = "rockchip,rk3399-dsi";
448 rockchip,grf = <&grf>;
449 reg = <0x0 0xff960000 0x0 0x8000>;
450 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
451 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>, <&cru SCLK_MIPIDPHY_CFG>;
452 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "mipi_dphy_cfg";
453 power-domains = <&power RK3399_PD_VIO>;
457 mipi1_rk_fb: mipi-rk-fb@ff968000 {
458 compatible = "rockchip,rk3399-dsi";
460 rockchip,grf = <&grf>;
461 reg = <0x0 0xff968000 0x0 0x8000>;
462 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH 0>;
463 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI1>, <&cru SCLK_MIPIDPHY_CFG>;
464 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "mipi_dphy_cfg";
465 power-domains = <&power RK3399_PD_VIO>;
469 edp_rk_fb: edp-rk-fb@ff970000 {
470 compatible = "rockchip,rk3399-edp-fb";
471 reg = <0x0 0xff970000 0x0 0x8000>;
472 rockchip,grf = <&grf>;
473 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
474 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>, <&cru PCLK_VIO_GRF>;
475 clock-names = "clk_edp", "pclk_edp", "clk_grf";
476 resets = <&cru SRST_P_EDP_CTRL>;
477 reset-names = "edp_apb";
479 power-domains = <&power RK3399_PD_EDP>;
485 /delete-property/ iommus;
486 /* 0 means ion, 1 means drm */
492 compatible = "rockchip,vpu_mmu";
497 /delete-property/ iommus;
498 /* 0 means ion, 1 means drm */
504 compatible = "rockchip,vdec_mmu";
509 cif_clkout: cif-clkout {
512 <2 11 RK_FUNC_3 &pcfg_pull_none>;
515 isp_dvp_d0d7: isp-dvp-d0d7 {
518 <2 0 RK_FUNC_3 &pcfg_pull_none>,
520 <2 1 RK_FUNC_3 &pcfg_pull_none>,
522 <2 2 RK_FUNC_3 &pcfg_pull_none>,
524 <2 3 RK_FUNC_3 &pcfg_pull_none>,
526 <2 4 RK_FUNC_3 &pcfg_pull_none>,
528 <2 5 RK_FUNC_3 &pcfg_pull_none>,
530 <2 6 RK_FUNC_3 &pcfg_pull_none>,
532 <2 7 RK_FUNC_3 &pcfg_pull_none>,
534 <2 8 RK_FUNC_3 &pcfg_pull_none>,
536 <2 9 RK_FUNC_3 &pcfg_pull_none>,
538 <2 10 RK_FUNC_3 &pcfg_pull_none>;
541 isp_shutter: isp-shutter {
544 <1 1 RK_FUNC_1 &pcfg_pull_none>,
546 <1 0 RK_FUNC_1 &pcfg_pull_none>;
549 isp_flash_trigger: isp-flash-trigger {
551 rockchip,pins = <1 3 RK_FUNC_1 &pcfg_pull_none>;
554 isp_prelight: isp-prelight {
556 rockchip,pins = <1 4 RK_FUNC_1 &pcfg_pull_none>;
559 isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
561 rockchip,pins = <0 17 RK_FUNC_GPIO &pcfg_pull_none>;
566 cam0_default_pins: cam0-default-pins {
567 rockchip,pins = <4 27 RK_FUNC_GPIO &pcfg_pull_none>,
568 <2 11 RK_FUNC_3 &pcfg_pull_none>;
570 cam0_sleep_pins: cam0-sleep-pins {
571 rockchip,pins = <4 27 RK_FUNC_3 &pcfg_pull_none>,
572 <2 11 RK_FUNC_GPIO &pcfg_pull_none>;