2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
42 #include <dt-bindings/display/rk_fb.h>
43 #include <dt-bindings/display/mipi_dsi.h>
46 compatible = "rockchip,android", "rockchip,rk3399";
54 bootargs = "earlycon=uart8250,mmio32,0xff1a0000 swiotlb=1";
57 ramoops_mem: ramoops_mem {
58 reg = <0x0 0x100000 0x0 0x100000>;
59 reg-names = "ramoops_mem";
63 compatible = "ramoops";
64 record-size = <0x0 0x20000>;
65 console-size = <0x0 0x80000>;
66 ftrace-size = <0x0 0x10000>;
67 pmsg-size = <0x0 0x50000>;
68 memory-region = <&ramoops_mem>;
71 fiq_debugger: fiq-debugger {
72 compatible = "rockchip,fiq-debugger";
73 rockchip,serial-id = <2>;
74 rockchip,signal-irq = <182>;
75 rockchip,wake-irq = <0>;
76 rockchip,irq-mode-enable = <1>; /* If enable uart uses irq instead of fiq */
77 rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */
78 pinctrl-names = "default";
79 pinctrl-0 = <&uart2c_xfer>;
87 /* global autoconfigured region for contiguous allocations */
89 compatible = "shared-dma-pool";
91 size = <0x0 0x8000000>;
94 /* reg = <0x0 0x0 0x0 0x0> will be updated by uboot */
95 rockchip_logo: rockchip-logo@00000000 {
96 compatible = "rockchip,fb-logo";
97 reg = <0x0 0x0 0x0 0x0>;
102 compatible = "rockchip,ion";
103 #address-cells = <1>;
107 reg = <0x00000000 0x02000000>;
114 rk_key: rockchip-key {
115 compatible = "rockchip,key";
118 io-channels = <&saradc 1>;
123 rockchip,adc_value = <1>;
128 label = "volume down";
129 rockchip,adc_value = <170>;
133 gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
142 rockchip,adc_value = <746>;
148 rockchip,adc_value = <355>;
154 rockchip,adc_value = <560>;
160 rockchip,adc_value = <450>;
164 vpu: vpu_service@ff650000 {
165 compatible = "rockchip,vpu_service";
166 rockchip,grf = <&grf>;
168 reg = <0x0 0xff650000 0x0 0x800>;
169 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>,
170 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>;
171 interrupt-names = "irq_dec", "irq_enc";
172 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
173 clock-names = "aclk_vcodec", "hclk_vcodec";
174 resets = <&cru SRST_H_VCODEC>, <&cru SRST_A_VCODEC>;
175 reset-names = "video_h", "video_a";
176 power-domains = <&power RK3399_PD_VCODEC>;
177 name = "vpu_service";
183 compatible = "rockchip,vpu_mmu";
184 reg = <0x0 0xff650800 0x0 0x40>;
185 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
186 interrupt-names = "vpu_mmu";
189 rkvdec: rkvdec@ff660000 {
190 compatible = "rockchip,rkvdec";
191 rockchip,grf = <&grf>;
193 reg = <0x0 0xff660000 0x0 0x400>;
194 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
195 interrupt-names = "irq_dec";
196 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>,<&cru SCLK_VDU_CA>,<&cru SCLK_VDU_CORE>;
197 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_cabac", "clk_core";
198 resets = <&cru SRST_H_VDU>, <&cru SRST_A_VDU>;
199 reset-names = "video_h", "video_a";
200 power-domains = <&power RK3399_PD_VDU>;
207 compatible = "rockchip,vdec_mmu";
208 reg = <0x0 0xff660480 0x0 0x40>,
209 <0x0 0xff6604c0 0x0 0x40>;
210 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
211 interrupt-names = "vdec_mmu";
215 compatible = "rockchip,iep";
217 reg = <0x0 0xff670000 0x0 0x800>;
218 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
219 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
220 clock-names = "aclk_iep", "hclk_iep";
221 power-domains = <&power RK3399_PD_IEP>;
227 compatible = "rockchip,iep_mmu";
228 reg = <0x0 0xff670800 0x0 0x40>;
229 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
230 interrupt-names = "iep_mmu";
234 compatible = "rockchip,rga2";
236 reg = <0x0 0xff680000 0x0 0x1000>;
237 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
238 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
239 clock-names = "aclk_rga", "hclk_rga", "clk_rga";
240 power-domains = <&power RK3399_PD_RGA>;
246 compatible = "rockchip,rk-fb";
247 rockchip,disp-mode = <DUAL>;
248 rockchip,uboot-logo-on = <1>;
249 memory-region = <&rockchip_logo>;
254 compatible = "rockchip,screen";
257 vopb_rk_fb: vop-rk-fb@ff900000 {
259 compatible = "rockchip,rk3399-lcdc";
260 rockchip,prop = <PRMRY>;
261 reg = <0x0 0xff900000 0x0 0x3efc>;
262 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
263 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
264 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
265 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
266 reset-names = "axi", "ahb", "dclk";
267 rockchip,grf = <&grf>;
268 rockchip,pwr18 = <0>;
269 rockchip,iommu-enabled = <1>;
270 power-domains = <&power RK3399_PD_VOPB>;
273 vopb_mmu_rk_fb: vopb-mmu {
276 compatible = "rockchip,vopb_mmu";
277 reg = <0x0 0xff903f00 0x0 0x100>;
278 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
279 interrupt-names = "vopb_mmu";
282 vopl_rk_fb: vop-rk-fb@ff8f0000 {
284 compatible = "rockchip,rk3399-lcdc";
285 rockchip,prop = <EXTEND>;
286 reg = <0x0 0xff8f0000 0x0 0x3efc>;
287 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
288 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
289 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
290 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
291 reset-names = "axi", "ahb", "dclk";
292 rockchip,grf = <&grf>;
293 rockchip,pwr18 = <0>;
294 rockchip,iommu-enabled = <1>;
295 power-domains = <&power RK3399_PD_VOPL>;
298 vopl_mmu_rk_fb: vopl-mmu {
301 compatible = "rockchip,vopl_mmu";
302 reg = <0x0 0xff8f3f00 0x0 0x100>;
303 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
304 interrupt-names = "vopl_mmu";
308 compatible = "rockchip,rk3399-isp", "rockchip,isp";
309 reg = <0x0 0xff910000 0x0 0x10000>;
310 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
312 <&cru SCLK_CIF_OUT>, <&cru SCLK_CIF_OUT>,
313 <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru SCLK_MIPIDPHY_REF>,
314 <&cru ACLK_ISP0_NOC>, <&cru ACLK_ISP0_WRAPPER>,
315 <&cru HCLK_ISP0_NOC>, <&cru HCLK_ISP0_WRAPPER>,
316 <&cru SCLK_ISP0>, <&cru SCLK_DPHY_RX0_CFG>;
318 "clk_cif_out", "clk_cif_pll",
319 "pclk_dphytxrx", "pclk_dphy_ref",
320 "aclk_isp0_noc", "aclk_isp0_wrapper",
321 "hclk_isp0_noc", "hclk_isp0_wrapper",
322 "clk_isp0", "pclk_dphyrx";
324 "cif_clkout","isp_dvp8bit0", "isp_mipi_fl",
325 "isp_mipi_fl_prefl", "isp_flash_as_gpio",
326 "isp_flash_as_trigger_out";
327 pinctrl-0 = <&cif_clkout>;
328 pinctrl-1 = <&isp_dvp_d0d7>;
329 pinctrl-2 = <&cif_clkout>;
330 pinctrl-3 = <&cif_clkout &isp_prelight>;
331 pinctrl-4 = <&isp_flash_trigger_as_gpio>;
332 pinctrl-5 = <&isp_flash_trigger>;
333 rockchip,isp,mipiphy = <2>;
334 rockchip,isp,cifphy = <1>;
335 rockchip,isp,dsiphy,reg = <0xff968000 0x8000>;
336 rockchip,grf = <&grf>;
337 rockchip,cru = <&cru>;
338 rockchip,gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
339 rockchip,isp,iommu-enable = <1>;
340 power-domains = <&power RK3399_PD_ISP0>;
346 compatible = "rockchip,isp0_mmu";
347 reg = <0x0 0xff914000 0x0 0x100>,
348 <0x0 0xff915000 0x0 0x100>;
349 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
350 interrupt-names = "isp0_mmu";
354 compatible = "rockchip,rk3399-isp", "rockchip,isp";
355 reg = <0x0 0xff920000 0x0 0x10000>;
356 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
358 <&cru ACLK_ISP1_NOC>, <&cru ACLK_ISP1_WRAPPER>,
359 <&cru HCLK_ISP1_NOC>, <&cru HCLK_ISP1_WRAPPER>,
360 <&cru SCLK_ISP1>, <&cru SCLK_CIF_OUT>,
361 <&cru SCLK_CIF_OUT>, <&cru SCLK_DPHY_TX1RX1_CFG>,
362 <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_ISP1_WRAPPER>,
363 <&cru SCLK_DPHY_RX0_CFG>;
365 "aclk_isp1_noc", "aclk_isp1_wrapper",
366 "hclk_isp1_noc", "hclk_isp1_wrapper",
367 "clk_isp1", "clk_cif_out",
368 "clk_cif_pll", "pclk_dphytxrx",
369 "pclk_dphy_ref", "pclk_isp1",
372 "cif_clkout","isp_dvp8bit0", "isp_mipi_fl",
373 "isp_mipi_fl_prefl", "isp_flash_as_gpio",
374 "isp_flash_as_trigger_out";
375 pinctrl-0 = <&cif_clkout>;
376 pinctrl-1 = <&cif_clkout &isp_dvp_d0d7>;
377 pinctrl-2 = <&cif_clkout>;
378 pinctrl-3 = <&cif_clkout &isp_prelight>;
379 pinctrl-4 = <&isp_flash_trigger_as_gpio>;
380 pinctrl-5 = <&isp_flash_trigger>;
381 rockchip,isp,mipiphy = <2>;
382 rockchip,isp,cifphy = <1>;
383 rockchip,isp,dsiphy,reg = <0xff968000 0x8000>;
384 rockchip,grf = <&grf>;
385 rockchip,cru = <&cru>;
386 rockchip,gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
387 rockchip,isp,iommu-enable = <1>;
388 power-domains = <&power RK3399_PD_ISP1>;
394 compatible = "rockchip,isp1_mmu";
395 reg = <0x0 0xff924000 0x0 0x100>,
396 <0x0 0xff925000 0x0 0x100>;
397 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
398 interrupt-names = "isp1_mmu";
401 hdmi_rk_fb: hdmi-rk-fb@ff940000 {
403 compatible = "rockchip,rk3399-hdmi";
404 reg = <0x0 0xff940000 0x0 0x20000>;
405 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>,
406 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH 0>;
407 clocks = <&cru PCLK_HDMI_CTRL>,
409 <&cru SCLK_HDMI_CEC>,
411 <&cru SCLK_HDMI_SFR>;
412 clock-names = "pclk_hdmi",
417 resets = <&cru SRST_HDMI_CTRL>;
418 reset-names = "hdmi";
419 pinctrl-names = "default", "gpio";
420 pinctrl-0 = <&hdmi_i2c_xfer &hdmi_cec>;
421 pinctrl-1 = <&i2c3_gpio>;
422 rockchip,grf = <&grf>;
423 power-domains = <&power RK3399_PD_HDCP>;
426 mipi0_rk_fb: mipi-rk-fb@ff960000 {
427 compatible = "rockchip,rk3399-dsi";
429 rockchip,grf = <&grf>;
430 reg = <0x0 0xff960000 0x0 0x8000>;
431 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
432 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>, <&cru SCLK_MIPIDPHY_CFG>;
433 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "mipi_dphy_cfg";
434 power-domains = <&power RK3399_PD_VIO>;
438 mipi1_rk_fb: mipi-rk-fb@ff968000 {
439 compatible = "rockchip,rk3399-dsi";
441 rockchip,grf = <&grf>;
442 reg = <0x0 0xff968000 0x0 0x8000>;
443 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH 0>;
444 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI1>, <&cru SCLK_MIPIDPHY_CFG>;
445 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "mipi_dphy_cfg";
446 power-domains = <&power RK3399_PD_VIO>;
450 edp_rk_fb: edp-rk-fb@ff970000 {
451 compatible = "rockchip,rk3399-edp-fb";
452 reg = <0x0 0xff970000 0x0 0x8000>;
453 rockchip,grf = <&grf>;
454 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
455 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>;
456 clock-names = "clk_edp", "pclk_edp";
457 resets = <&cru SRST_P_EDP_CTRL>;
458 reset-names = "edp_apb";
465 cif_clkout: cif-clkout {
468 <2 11 RK_FUNC_3 &pcfg_pull_none>;
471 isp_dvp_d0d7: isp-dvp-d0d7 {
474 <2 0 RK_FUNC_3 &pcfg_pull_none>,
476 <2 1 RK_FUNC_3 &pcfg_pull_none>,
478 <2 2 RK_FUNC_3 &pcfg_pull_none>,
480 <2 3 RK_FUNC_3 &pcfg_pull_none>,
482 <2 4 RK_FUNC_3 &pcfg_pull_none>,
484 <2 5 RK_FUNC_3 &pcfg_pull_none>,
486 <2 6 RK_FUNC_3 &pcfg_pull_none>,
488 <2 7 RK_FUNC_3 &pcfg_pull_none>,
490 <2 8 RK_FUNC_3 &pcfg_pull_none>,
492 <2 9 RK_FUNC_3 &pcfg_pull_none>,
494 <2 10 RK_FUNC_3 &pcfg_pull_none>,
496 <2 11 RK_FUNC_3 &pcfg_pull_none>;
499 isp_shutter: isp-shutter {
502 <1 1 RK_FUNC_1 &pcfg_pull_none>,
504 <1 0 RK_FUNC_1 &pcfg_pull_none>;
507 isp_flash_trigger: isp-flash-trigger {
509 rockchip,pins = <1 3 RK_FUNC_1 &pcfg_pull_none>;
512 isp_prelight: isp-prelight {
514 rockchip,pins = <1 4 RK_FUNC_1 &pcfg_pull_none>;
517 isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
519 rockchip,pins = <0 17 RK_FUNC_GPIO &pcfg_pull_none>;