2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
42 #include <dt-bindings/display/rk_fb.h>
43 #include <dt-bindings/display/mipi_dsi.h>
46 compatible = "rockchip,android", "rockchip,rk3399";
54 bootargs = "earlycon=uart8250,mmio32,0xff1a0000";
57 ramoops_mem: ramoops_mem {
58 reg = <0x0 0x100000 0x0 0x100000>;
59 reg-names = "ramoops_mem";
63 compatible = "ramoops";
64 record-size = <0x0 0x20000>;
65 console-size = <0x0 0x80000>;
66 ftrace-size = <0x0 0x10000>;
67 pmsg-size = <0x0 0x50000>;
68 memory-region = <&ramoops_mem>;
71 fiq_debugger: fiq-debugger {
72 compatible = "rockchip,fiq-debugger";
73 rockchip,serial-id = <2>;
74 rockchip,signal-irq = <182>;
75 rockchip,wake-irq = <0>;
76 rockchip,irq-mode-enable = <1>; /* If enable uart uses irq instead of fiq */
77 rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */
78 pinctrl-names = "default";
79 pinctrl-0 = <&uart2c_xfer>;
87 /* global autoconfigured region for contiguous allocations */
89 compatible = "shared-dma-pool";
91 size = <0x0 0x8000000>;
94 /* reg = <0x0 0x0 0x0 0x0> will be updated by uboot */
95 rockchip_logo: rockchip-logo@00000000 {
96 compatible = "rockchip,fb-logo";
97 reg = <0x0 0x0 0x0 0x0>;
102 compatible = "rockchip,ion";
103 #address-cells = <1>;
107 reg = <0x00000000 0x02000000>;
114 rk_key: rockchip-key {
115 compatible = "rockchip,key";
118 io-channels = <&saradc 1>;
123 rockchip,adc_value = <1>;
128 label = "volume down";
129 rockchip,adc_value = <170>;
133 gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
142 rockchip,adc_value = <746>;
148 rockchip,adc_value = <355>;
154 rockchip,adc_value = <560>;
160 rockchip,adc_value = <450>;
164 vpu: vpu_service@ff650000 {
165 compatible = "rockchip,vpu_service";
166 rockchip,grf = <&grf>;
168 reg = <0x0 0xff650000 0x0 0x800>;
169 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
170 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
171 interrupt-names = "irq_dec", "irq_enc";
172 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
173 clock-names = "aclk_vcodec", "hclk_vcodec";
174 resets = <&cru SRST_H_VCODEC>, <&cru SRST_A_VCODEC>;
175 reset-names = "video_h", "video_a";
176 power-domains = <&power RK3399_PD_VCODEC>;
177 name = "vpu_service";
183 compatible = "rockchip,vpu_mmu";
184 reg = <0x0 0xff650800 0x0 0x40>;
185 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
186 interrupt-names = "vpu_mmu";
189 rkvdec: rkvdec@ff660000 {
190 compatible = "rockchip,rkvdec";
191 rockchip,grf = <&grf>;
193 reg = <0x0 0xff660000 0x0 0x400>;
194 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
195 interrupt-names = "irq_dec";
196 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>,<&cru SCLK_VDU_CA>,<&cru SCLK_VDU_CORE>;
197 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_cabac", "clk_core";
198 resets = <&cru SRST_H_VDU>, <&cru SRST_A_VDU>;
199 reset-names = "video_h", "video_a";
200 power-domains = <&power RK3399_PD_VDU>;
207 compatible = "rockchip,vdec_mmu";
208 reg = <0x0 0xff660480 0x0 0x40>,
209 <0x0 0xff6604c0 0x0 0x40>;
210 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
211 interrupt-names = "vdec_mmu";
215 compatible = "rockchip,iep";
217 reg = <0x0 0xff670000 0x0 0x800>;
218 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
219 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
220 clock-names = "aclk_iep", "hclk_iep";
221 power-domains = <&power RK3399_PD_IEP>;
227 compatible = "rockchip,iep_mmu";
228 reg = <0x0 0xff670800 0x0 0x40>;
229 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
230 interrupt-names = "iep_mmu";
234 compatible = "rockchip,rga2";
236 reg = <0x0 0xff680000 0x0 0x1000>;
237 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
238 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
239 clock-names = "aclk_rga", "hclk_rga", "clk_rga";
240 power-domains = <&power RK3399_PD_RGA>;
246 compatible = "rockchip,rk-fb";
247 rockchip,disp-mode = <DUAL>;
248 rockchip,uboot-logo-on = <1>;
249 memory-region = <&rockchip_logo>;
254 compatible = "rockchip,screen";
257 vopb_rk_fb: vop-rk-fb@ff900000 {
259 compatible = "rockchip,rk3399-lcdc";
260 rockchip,prop = <PRMRY>;
261 reg = <0x0 0xff900000 0x0 0x3efc>;
262 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
263 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
264 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
265 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
266 reset-names = "axi", "ahb", "dclk";
267 rockchip,grf = <&grf>;
268 rockchip,pwr18 = <0>;
269 rockchip,iommu-enabled = <1>;
270 power-domains = <&power RK3399_PD_VOPB>;
273 vopb_mmu_rk_fb: vopb-mmu {
276 compatible = "rockchip,vopb_mmu";
277 reg = <0x0 0xff903f00 0x0 0x100>;
278 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
279 interrupt-names = "vopb_mmu";
282 vopl_rk_fb: vop-rk-fb@ff8f0000 {
284 compatible = "rockchip,rk3399-lcdc";
285 rockchip,prop = <EXTEND>;
286 reg = <0x0 0xff8f0000 0x0 0x3efc>;
287 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
288 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
289 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
290 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
291 reset-names = "axi", "ahb", "dclk";
292 rockchip,grf = <&grf>;
293 rockchip,pwr18 = <0>;
294 rockchip,iommu-enabled = <1>;
295 power-domains = <&power RK3399_PD_VOPL>;
298 vopl_mmu_rk_fb: vopl-mmu {
301 compatible = "rockchip,vopl_mmu";
302 reg = <0x0 0xff8f3f00 0x0 0x100>;
303 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
304 interrupt-names = "vopl_mmu";
307 hdmi_rk_fb: hdmi-rk-fb@ff940000 {
309 compatible = "rockchip,rk3399-hdmi";
310 reg = <0x0 0xff940000 0x0 0x20000>;
311 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
312 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
313 clocks = <&cru PCLK_HDMI_CTRL>,
315 <&cru SCLK_HDMI_CEC>,
317 <&cru SCLK_HDMI_SFR>;
318 clock-names = "pclk_hdmi",
323 resets = <&cru SRST_HDMI_CTRL>;
324 reset-names = "hdmi";
325 pinctrl-names = "default", "gpio";
326 pinctrl-0 = <&hdmi_i2c_xfer &hdmi_cec>;
327 pinctrl-1 = <&i2c3_gpio>;
328 rockchip,grf = <&grf>;
329 power-domains = <&power RK3399_PD_HDCP>;
332 mipi0_rk_fb: mipi-rk-fb@ff960000 {
333 compatible = "rockchip,rk3399-dsi";
335 rockchip,grf = <&grf>;
336 reg = <0x0 0xff960000 0x0 0x8000>;
337 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
338 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>, <&cru SCLK_MIPIDPHY_CFG>;
339 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "mipi_dphy_cfg";
340 power-domains = <&power RK3399_PD_VIO>;
344 mipi1_rk_fb: mipi-rk-fb@ff968000 {
345 compatible = "rockchip,rk3399-dsi";
347 rockchip,grf = <&grf>;
348 reg = <0x0 0xff968000 0x0 0x8000>;
349 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
350 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI1>, <&cru SCLK_MIPIDPHY_CFG>;
351 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "mipi_dphy_cfg";
352 power-domains = <&power RK3399_PD_VIO>;
356 edp_rk_fb: edp-rk-fb@ff970000 {
357 compatible = "rockchip,rk3399-edp-fb";
358 reg = <0x0 0xff970000 0x0 0x8000>;
359 rockchip,grf = <&grf>;
360 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
361 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>;
362 clock-names = "clk_edp", "pclk_edp";
363 resets = <&cru SRST_P_EDP_CTRL>;
364 reset-names = "edp_apb";
368 hdmi_sound: hdmi-sound {
370 compatible = "simple-audio-card";
371 simple-audio-card,format = "i2s";
372 simple-audio-card,mclk-fs = <256>;
373 simple-audio-card,name = "rockchip,hdmi";
374 simple-audio-card,cpu {
377 simple-audio-card,codec {
378 sound-dai = <&dw_hdmi_audio>;
382 dw_hdmi_audio: dw-hdmi-audio {
384 compatible = "rockchip,dw-hdmi-audio";
385 #sound-dai-cells = <0>;
390 #sound-dai-cells = <0>;
394 dr_mode = "peripheral";