2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
42 #include <dt-bindings/display/rk_fb.h>
43 #include <dt-bindings/display/mipi_dsi.h>
46 compatible = "rockchip,android", "rockchip,rk3399";
49 bootargs = "console=uart,mmio32,0xff1a0000";
52 ramoops_mem: ramoops_mem {
53 reg = <0x0 0x100000 0x0 0x100000>;
54 reg-names = "ramoops_mem";
58 compatible = "ramoops";
59 record-size = <0x0 0x20000>;
60 console-size = <0x0 0x80000>;
61 ftrace-size = <0x0 0x10000>;
62 pmsg-size = <0x0 0x50000>;
63 memory-region = <&ramoops_mem>;
71 /* global autoconfigured region for contiguous allocations */
73 compatible = "shared-dma-pool";
75 size = <0x0 0x8000000>;
81 compatible = "rockchip,ion";
86 reg = <0x00000000 0x02000000>;
93 rk_key: rockchip-key {
94 compatible = "rockchip,key";
97 io-channels = <&saradc 1>;
102 rockchip,adc_value = <1>;
107 label = "volume down";
108 rockchip,adc_value = <170>;
112 gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
121 rockchip,adc_value = <746>;
127 rockchip,adc_value = <355>;
133 rockchip,adc_value = <560>;
139 rockchip,adc_value = <450>;
143 vpu: vpu_service@ff650000 {
144 compatible = "rockchip,vpu_service";
145 rockchip,grf = <&grf>;
147 reg = <0x0 0xff650000 0x0 0x800>;
148 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
149 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
150 interrupt-names = "irq_dec", "irq_enc";
151 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
152 clock-names = "aclk_vcodec", "hclk_vcodec";
153 resets = <&cru SRST_H_VCODEC>, <&cru SRST_A_VCODEC>;
154 reset-names = "video_h", "video_a";
155 name = "vpu_service";
161 compatible = "rockchip,vpu_mmu";
162 reg = <0x0 0xff650800 0x0 0x40>;
163 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
164 interrupt-names = "vpu_mmu";
167 rkvdec: rkvdec@ff660000 {
168 compatible = "rockchip,rkvdec";
169 rockchip,grf = <&grf>;
171 reg = <0x0 0xff660000 0x0 0x400>;
172 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
173 interrupt-names = "irq_dec";
174 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>,<&cru SCLK_VDU_CA>,<&cru SCLK_VDU_CORE>;
175 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_cabac", "clk_core";
176 resets = <&cru SRST_H_VDU>, <&cru SRST_A_VDU>;
177 reset-names = "video_h", "video_a";
184 compatible = "rockchip,vdec_mmu";
185 reg = <0x0 0xff660480 0x0 0x40>,
186 <0x0 0xff6604c0 0x0 0x40>;
187 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
188 interrupt-names = "vdec_mmu";
192 compatible = "rockchip,iep";
194 reg = <0x0 0xff670000 0x0 0x800>;
195 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
196 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
197 clock-names = "aclk_iep", "hclk_iep";
203 compatible = "rockchip,iep_mmu";
204 reg = <0x0 0xff670800 0x0 0x40>;
205 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
206 interrupt-names = "iep_mmu";
210 compatible = "rockchip,rga2";
212 reg = <0x0 0xff680000 0x0 0x1000>;
213 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
214 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
215 clock-names = "aclk_rga", "hclk_rga", "clk_rga";
219 compatible = "rockchip,rk-fb";
220 rockchip,disp-mode = <DUAL>;
224 compatible = "rockchip,screen";
225 #include <dt-bindings/display/screen-timing/lcd-tv080wum-nl0-mipi.dtsi>
228 vopb_rk_fb: vop-rk-fb@ff900000 {
229 compatible = "rockchip,rk3399-lcdc";
230 rockchip,prop = <PRMRY>;
231 reg = <0x0 0xff900000 0x0 0x3efc>;
232 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
233 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
234 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
235 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
236 reset-names = "axi", "ahb", "dclk";
237 rockchip,grf = <&grf>;
238 rockchip,pwr18 = <0>;
239 rockchip,iommu-enabled = <1>;
240 power-domains = <&power RK3399_PD_VOPB>;
241 power_ctr: power_ctr {
242 /*rockchip,debug = <0>;
244 rockchip,power_type = <GPIO>;
245 gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;//GPIO_C6 = 22
246 rockchip,delay = <10>;
251 rockchip,power_type = <GPIO>;
252 gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>;//GPIO_C5 = 21
253 rockchip,delay = <10>;
257 rockchip,power_type = <GPIO>;
258 gpios = <&gpio3 GPIO_D6 GPIO_ACTIVE_HIGH>;
259 rockchip,delay = <5>;
264 vopb_mmu_rk_fb: vopb-mmu {
266 compatible = "rockchip,vopb_mmu";
267 reg = <0x0 0xff903f00 0x0 0x100>;
268 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
269 interrupt-names = "vopb_mmu";
272 vopl_rk_fb: vop-rk-fb@ff8f0000 {
273 compatible = "rockchip,rk3399-lcdc";
274 rockchip,prop = <EXTEND>;
275 reg = <0x0 0xff8f0000 0x0 0x3efc>;
276 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
277 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
278 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
279 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
280 reset-names = "axi", "ahb", "dclk";
281 rockchip,grf = <&grf>;
282 rockchip,pwr18 = <0>;
283 rockchip,iommu-enabled = <1>;
284 power-domains = <&power RK3399_PD_VOPL>;
287 vopl_mmu_rk_fb: vopl-mmu {
289 compatible = "rockchip,vopl_mmu";
290 reg = <0x0 0xff8f3f00 0x0 0x100>;
291 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
292 interrupt-names = "vopl_mmu";
295 hdmi_rk_fb: hdmi-rk-fb@ff940000 {
296 compatible = "rockchip,rk3399-hdmi";
297 reg = <0x0 0xff940000 0x0 0x20000>;
298 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
299 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
300 clocks = <&cru PCLK_HDMI_CTRL>,
301 <&cru SCLK_HDMI_SFR>,
302 <&cru SCLK_HDMI_CEC>,
304 clock-names = "pclk_hdmi",
308 resets = <&cru SRST_HDMI_CTRL>;
309 reset-names = "hdmi";
310 pinctrl-names = "default", "gpio";
311 pinctrl-0 = <&hdmi_i2c_xfer &hdmi_cec>;
312 pinctrl-1 = <&i2c3_gpio>;
313 rockchip,grf = <&grf>;
314 power-domains = <&power RK3399_PD_HDCP>;
317 mipi0_rk_fb: mipi-rk-fb@ff960000 {
318 compatible = "rockchip,rk3399-dsi";
320 rockchip,grf = <&grf>;
321 reg = <0x0 0xff960000 0x0 0x8000>;
322 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
323 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>, <&cru SCLK_MIPIDPHY_CFG>;
324 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "mipi_dphy_cfg";
325 power-domains = <&power RK3399_PD_VIO>;
328 mipi1_rk_fb: mipi-rk-fb@ff968000 {
329 compatible = "rockchip,rk3399-dsi";
331 rockchip,grf = <&grf>;
332 reg = <0x0 0xff968000 0x0 0x8000>;
333 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
334 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI1>, <&cru SCLK_MIPIDPHY_CFG>;
335 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "mipi_dphy_cfg";
336 power-domains = <&power RK3399_PD_VIO>;
340 compatible = "simple-audio-card";
341 simple-audio-card,format = "i2s";
342 simple-audio-card,mclk-fs = <256>;
343 simple-audio-card,name = "rockchip,hdmi";
344 simple-audio-card,cpu {
347 simple-audio-card,codec {
348 sound-dai = <&dw_hdmi_audio>;
352 dw_hdmi_audio: dw-hdmi-audio {
353 compatible = "rockchip,dw-hdmi-audio";
354 #sound-dai-cells = <0>;
360 #sound-dai-cells = <0>;
364 dr_mode = "peripheral";