2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/display/drm_mipi_dsi.h>
44 #include <dt-bindings/display/media-bus-format.h>
47 compatible = "rockchip,android", "rockchip,rk3399";
50 bootargs = "earlycon=uart8250,mmio32,0xff1a0000 swiotlb=1";
53 ramoops_mem: ramoops_mem {
54 reg = <0x0 0x110000 0x0 0xf0000>;
55 reg-names = "ramoops_mem";
59 compatible = "ramoops";
60 record-size = <0x0 0x20000>;
61 console-size = <0x0 0x80000>;
62 ftrace-size = <0x0 0x00000>;
63 pmsg-size = <0x0 0x50000>;
64 memory-region = <&ramoops_mem>;
67 fiq_debugger: fiq-debugger {
68 compatible = "rockchip,fiq-debugger";
69 rockchip,serial-id = <2>;
70 rockchip,signal-irq = <182>;
71 rockchip,wake-irq = <0>;
72 rockchip,irq-mode-enable = <1>; /* If enable uart uses irq instead of fiq */
73 rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */
74 pinctrl-names = "default";
75 pinctrl-0 = <&uart2c_xfer>;
83 drm_logo: drm-logo@00000000 {
84 compatible = "rockchip,drm-logo";
85 reg = <0x0 0x0 0x0 0x0>;
89 rk_key: rockchip-key {
90 compatible = "rockchip,key";
93 io-channels = <&saradc 1>;
98 rockchip,adc_value = <1>;
103 label = "volume down";
104 rockchip,adc_value = <170>;
108 gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
117 rockchip,adc_value = <746>;
123 rockchip,adc_value = <355>;
129 rockchip,adc_value = <560>;
135 rockchip,adc_value = <450>;
140 compatible = "rockchip,rga2";
142 reg = <0x0 0xff680000 0x0 0x1000>;
143 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
144 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
145 clock-names = "aclk_rga", "hclk_rga", "clk_rga";
146 power-domains = <&power RK3399_PD_RGA>;
152 compatible = "rockchip,rk3399-isp", "rockchip,isp";
153 reg = <0x0 0xff910000 0x0 0x4000>;
154 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
156 <&cru SCLK_CIF_OUT>, <&cru SCLK_CIF_OUT>,
157 <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru SCLK_MIPIDPHY_REF>,
158 <&cru ACLK_ISP0_NOC>, <&cru ACLK_ISP0_WRAPPER>,
159 <&cru HCLK_ISP0_NOC>, <&cru HCLK_ISP0_WRAPPER>,
160 <&cru SCLK_ISP0>, <&cru SCLK_DPHY_RX0_CFG>;
162 "clk_cif_out", "clk_cif_pll",
163 "pclk_dphytxrx", "pclk_dphy_ref",
164 "aclk_isp0_noc", "aclk_isp0_wrapper",
165 "hclk_isp0_noc", "hclk_isp0_wrapper",
166 "clk_isp0", "pclk_dphyrx";
168 "cif_clkout", "isp_dvp8bit0", "isp_mipi_fl",
169 "isp_mipi_fl_prefl", "isp_flash_as_gpio",
170 "isp_flash_as_trigger_out";
171 pinctrl-0 = <&cif_clkout>;
172 pinctrl-1 = <&isp_dvp_d0d7>;
173 pinctrl-2 = <&cif_clkout>;
174 pinctrl-3 = <&isp_prelight>;
175 pinctrl-4 = <&isp_flash_trigger_as_gpio>;
176 pinctrl-5 = <&isp_flash_trigger>;
177 rockchip,isp,mipiphy = <2>;
178 rockchip,isp,cifphy = <1>;
179 rockchip,isp,dsiphy,reg = <0xff968000 0x8000>;
180 rockchip,grf = <&grf>;
181 rockchip,cru = <&cru>;
182 rockchip,gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
183 rockchip,isp,iommu-enable = <1>;
184 power-domains = <&power RK3399_PD_ISP0>;
185 iommus = <&isp0_mmu>;
190 compatible = "rockchip,rk3399-isp", "rockchip,isp";
191 reg = <0x0 0xff920000 0x0 0x4000>;
192 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
194 <&cru ACLK_ISP1_NOC>, <&cru ACLK_ISP1_WRAPPER>,
195 <&cru HCLK_ISP1_NOC>, <&cru HCLK_ISP1_WRAPPER>,
196 <&cru SCLK_ISP1>, <&cru SCLK_CIF_OUT>,
197 <&cru SCLK_CIF_OUT>, <&cru SCLK_DPHY_TX1RX1_CFG>,
198 <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_ISP1_WRAPPER>,
199 <&cru SCLK_DPHY_RX0_CFG>, <&cru PCLK_MIPI_DSI1>,
200 <&cru SCLK_MIPIDPHY_CFG>;
202 "aclk_isp1_noc", "aclk_isp1_wrapper",
203 "hclk_isp1_noc", "hclk_isp1_wrapper",
204 "clk_isp1", "clk_cif_out",
205 "clk_cif_pll", "pclk_dphytxrx",
206 "pclk_dphy_ref", "pclk_isp1",
207 "pclk_dphyrx", "pclk_mipi_dsi",
210 "cif_clkout", "isp_dvp8bit0", "isp_mipi_fl",
211 "isp_mipi_fl_prefl", "isp_flash_as_gpio",
212 "isp_flash_as_trigger_out";
213 pinctrl-0 = <&cif_clkout>;
214 pinctrl-1 = <&isp_dvp_d0d7>;
215 pinctrl-2 = <&cif_clkout>;
216 pinctrl-3 = <&isp_prelight>;
217 pinctrl-4 = <&isp_flash_trigger_as_gpio>;
218 pinctrl-5 = <&isp_flash_trigger>;
219 rockchip,isp,mipiphy = <2>;
220 rockchip,isp,cifphy = <1>;
221 rockchip,isp,dsiphy,reg = <0xff968000 0x8000>;
222 rockchip,grf = <&grf>;
223 rockchip,cru = <&cru>;
224 rockchip,gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
225 rockchip,isp,iommu-enable = <1>;
226 power-domains = <&power RK3399_PD_ISP1>;
227 iommus = <&isp1_mmu>;
232 compatible = "rockchip,uboot-charge";
233 rockchip,uboot-charge-on = <1>;
234 rockchip,android-charge-on = <0>;
256 i2c-scl-rising-time-ns = <450>;
257 i2c-scl-falling-time-ns = <15>;
261 ddc-i2c-bus = <&i2c3>;
268 ports = <&vopb_out>, <&vopl_out>;
269 memory-region = <&drm_logo>;
271 route_hdmi: route-hdmi {
273 logo,uboot = "logo.bmp";
274 logo,kernel = "logo_kernel.bmp";
275 logo,mode = "fullscreen";
276 charge_logo,mode = "center";
277 connect = <&vopb_out_hdmi>;
280 route_mipi: route-mipi {
282 logo,uboot = "logo.bmp";
283 logo,kernel = "logo_kernel.bmp";
284 logo,mode = "fullscreen";
285 charge_logo,mode = "center";
286 connect = <&vopb_out_mipi>;
289 route_edp: route-edp {
291 logo,uboot = "logo.bmp";
292 logo,kernel = "logo_kernel.bmp";
293 logo,mode = "fullscreen";
294 charge_logo,mode = "center";
295 connect = <&vopb_out_edp>;
301 #sound-dai-cells = <0>;
310 cif_clkout: cif-clkout {
313 <2 11 RK_FUNC_3 &pcfg_pull_none>;
316 isp_dvp_d0d7: isp-dvp-d0d7 {
319 <2 0 RK_FUNC_3 &pcfg_pull_none>,
321 <2 1 RK_FUNC_3 &pcfg_pull_none>,
323 <2 2 RK_FUNC_3 &pcfg_pull_none>,
325 <2 3 RK_FUNC_3 &pcfg_pull_none>,
327 <2 4 RK_FUNC_3 &pcfg_pull_none>,
329 <2 5 RK_FUNC_3 &pcfg_pull_none>,
331 <2 6 RK_FUNC_3 &pcfg_pull_none>,
333 <2 7 RK_FUNC_3 &pcfg_pull_none>,
335 <2 8 RK_FUNC_3 &pcfg_pull_none>,
337 <2 9 RK_FUNC_3 &pcfg_pull_none>,
339 <2 10 RK_FUNC_3 &pcfg_pull_none>;
342 isp_shutter: isp-shutter {
345 <1 1 RK_FUNC_1 &pcfg_pull_none>,
347 <1 0 RK_FUNC_1 &pcfg_pull_none>;
350 isp_flash_trigger: isp-flash-trigger {
352 rockchip,pins = <1 3 RK_FUNC_1 &pcfg_pull_none>;
355 isp_prelight: isp-prelight {
357 rockchip,pins = <1 4 RK_FUNC_1 &pcfg_pull_none>;
360 isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
363 <0 17 RK_FUNC_GPIO &pcfg_pull_none>;