2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
42 #include <dt-bindings/display/rk_fb.h>
43 #include <dt-bindings/display/mipi_dsi.h>
44 #include "rk3399-vop-clk-set.dtsi"
47 compatible = "rockchip,android", "rockchip,rk3399";
55 bootargs = "earlycon=uart8250,mmio32,0xff1a0000 swiotlb=1";
58 ramoops_mem: ramoops_mem {
59 reg = <0x0 0x110000 0x0 0xf0000>;
60 reg-names = "ramoops_mem";
64 compatible = "ramoops";
65 record-size = <0x0 0x20000>;
66 console-size = <0x0 0x80000>;
67 ftrace-size = <0x0 0x00000>;
68 pmsg-size = <0x0 0x50000>;
69 memory-region = <&ramoops_mem>;
72 fiq_debugger: fiq-debugger {
73 compatible = "rockchip,fiq-debugger";
74 rockchip,serial-id = <2>;
75 rockchip,signal-irq = <182>;
76 rockchip,wake-irq = <0>;
77 rockchip,irq-mode-enable = <1>; /* If enable uart uses irq instead of fiq */
78 rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */
79 pinctrl-names = "default";
80 pinctrl-0 = <&uart2c_xfer>;
88 /* global autoconfigured region for contiguous allocations */
90 compatible = "shared-dma-pool";
92 size = <0x0 0x8000000>;
95 /* reg = <0x0 0x0 0x0 0x0> will be updated by uboot */
96 rockchip_logo: rockchip-logo@00000000 {
97 compatible = "rockchip,fb-logo";
98 reg = <0x0 0x0 0x0 0x0>;
103 compatible = "rockchip,ion";
104 #address-cells = <1>;
108 reg = <0x00000000 0x02000000>;
115 rk_key: rockchip-key {
116 compatible = "rockchip,key";
119 io-channels = <&saradc 1>;
124 rockchip,adc_value = <1>;
129 label = "volume down";
130 rockchip,adc_value = <170>;
134 gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
143 rockchip,adc_value = <746>;
149 rockchip,adc_value = <355>;
155 rockchip,adc_value = <560>;
161 rockchip,adc_value = <450>;
165 cdn_dp_fb: dp-fb@fec00000 {
167 compatible = "rockchip,rk3399-cdn-dp-fb";
168 reg = <0x0 0xfec00000 0x0 0x100000>;
169 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
170 clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
171 <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
172 clock-names = "core-clk", "pclk", "spdif", "grf";
173 assigned-clocks = <&cru SCLK_DP_CORE>;
174 assigned-clock-rates = <100000000>;
175 power-domains = <&power RK3399_PD_HDCP>;
176 phys = <&tcphy0_dp>, <&tcphy1_dp>;
177 resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>,
178 <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>;
179 reset-names = "spdif", "dptx", "apb", "core";
180 rockchip,grf = <&grf>;
181 #address-cells = <1>;
183 #sound-dai-cells = <1>;
186 cdn_dp_sound: cdn-dp-sound {
188 compatible = "simple-audio-card";
189 simple-audio-card,name = "rockchip,cdn-dp-fb";
190 simple-audio-card,widgets = "Headphone", "Out Jack",
193 simple-audio-card,dai-link@0 {
202 sound-dai = <&cdn_dp_fb 0>;
208 compatible = "rockchip,rga2";
210 reg = <0x0 0xff680000 0x0 0x1000>;
211 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
212 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
213 clock-names = "aclk_rga", "hclk_rga", "clk_rga";
214 power-domains = <&power RK3399_PD_RGA>;
220 compatible = "rockchip,rk-fb";
221 rockchip,disp-mode = <DUAL>;
222 rockchip,uboot-logo-on = <1>;
223 memory-region = <&rockchip_logo>;
228 compatible = "rockchip,screen";
231 vopb_rk_fb: vop-rk-fb@ff900000 {
233 compatible = "rockchip,rk3399-lcdc";
234 rockchip,prop = <PRMRY>;
235 reg = <0x0 0xff900000 0x0 0x3efc>;
236 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
237 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
238 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
239 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
240 reset-names = "axi", "ahb", "dclk";
241 rockchip,grf = <&grf>;
242 rockchip,pwr18 = <0>;
243 rockchip,iommu-enabled = <1>;
244 power-domains = <&power RK3399_PD_VOPB>;
248 vopb_mmu_rk_fb: vopb-mmu {
251 compatible = "rockchip,vopb_mmu";
252 reg = <0x0 0xff903f00 0x0 0x100>;
253 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
254 interrupt-names = "vopb_mmu";
257 vopl_rk_fb: vop-rk-fb@ff8f0000 {
259 compatible = "rockchip,rk3399-lcdc";
260 rockchip,prop = <EXTEND>;
261 reg = <0x0 0xff8f0000 0x0 0x3efc>;
262 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
263 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
264 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
265 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
266 reset-names = "axi", "ahb", "dclk";
267 rockchip,grf = <&grf>;
268 rockchip,pwr18 = <0>;
269 rockchip,iommu-enabled = <1>;
270 power-domains = <&power RK3399_PD_VOPL>;
274 vopl_mmu_rk_fb: vopl-mmu {
277 compatible = "rockchip,vopl_mmu";
278 reg = <0x0 0xff8f3f00 0x0 0x100>;
279 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
280 interrupt-names = "vopl_mmu";
283 cif_isp0: cif_isp@ff910000 {
284 compatible = "rockchip,rk3399-cif-isp";
285 rockchip,grf = <&grf>;
286 reg = <0x0 0xff910000 0x0 0x10000>, <0x0 0xff968000 0x0 0x8000>;
287 reg-names = "register", "dsihost-register";
289 <&cru SCLK_CIF_OUT>, <&cru SCLK_CIF_OUT>,
290 <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru SCLK_MIPIDPHY_REF>,
291 <&cru ACLK_ISP0_NOC>, <&cru ACLK_ISP0_WRAPPER>,
292 <&cru HCLK_ISP0_NOC>, <&cru HCLK_ISP0_WRAPPER>,
293 <&cru SCLK_ISP0>, <&cru SCLK_DPHY_RX0_CFG>;
295 "clk_cif_out", "clk_cif_pll",
296 "pclk_dphytxrx", "pclk_dphy_ref",
297 "aclk_isp0_noc", "aclk_isp0_wrapper",
298 "hclk_isp0_noc", "hclk_isp0_wrapper",
299 "clk_isp0", "pclk_dphyrx";
300 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
301 interrupt-names = "cif_isp10_irq";
302 power-domains = <&power RK3399_PD_ISP0>;
307 compatible = "rockchip,rk3399-isp", "rockchip,isp";
308 reg = <0x0 0xff910000 0x0 0x10000>;
309 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
311 <&cru SCLK_CIF_OUT>, <&cru SCLK_CIF_OUT>,
312 <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru SCLK_MIPIDPHY_REF>,
313 <&cru ACLK_ISP0_NOC>, <&cru ACLK_ISP0_WRAPPER>,
314 <&cru HCLK_ISP0_NOC>, <&cru HCLK_ISP0_WRAPPER>,
315 <&cru SCLK_ISP0>, <&cru SCLK_DPHY_RX0_CFG>;
317 "clk_cif_out", "clk_cif_pll",
318 "pclk_dphytxrx", "pclk_dphy_ref",
319 "aclk_isp0_noc", "aclk_isp0_wrapper",
320 "hclk_isp0_noc", "hclk_isp0_wrapper",
321 "clk_isp0", "pclk_dphyrx";
323 "cif_clkout","isp_dvp8bit0", "isp_mipi_fl",
324 "isp_mipi_fl_prefl", "isp_flash_as_gpio",
325 "isp_flash_as_trigger_out";
326 pinctrl-0 = <&cif_clkout>;
327 pinctrl-1 = <&isp_dvp_d0d7>;
328 pinctrl-2 = <&cif_clkout>;
329 pinctrl-3 = <&isp_prelight>;
330 pinctrl-4 = <&isp_flash_trigger_as_gpio>;
331 pinctrl-5 = <&isp_flash_trigger>;
332 rockchip,isp,mipiphy = <2>;
333 rockchip,isp,cifphy = <1>;
334 rockchip,isp,dsiphy,reg = <0xff968000 0x8000>;
335 rockchip,grf = <&grf>;
336 rockchip,cru = <&cru>;
337 rockchip,gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
338 rockchip,isp,iommu-enable = <1>;
339 power-domains = <&power RK3399_PD_ISP0>;
345 compatible = "rockchip,isp0_mmu";
346 reg = <0x0 0xff914000 0x0 0x100>,
347 <0x0 0xff915000 0x0 0x100>;
348 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
349 interrupt-names = "isp0_mmu";
353 compatible = "rockchip,rk3399-isp", "rockchip,isp";
354 reg = <0x0 0xff920000 0x0 0x10000>;
355 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
357 <&cru ACLK_ISP1_NOC>, <&cru ACLK_ISP1_WRAPPER>,
358 <&cru HCLK_ISP1_NOC>, <&cru HCLK_ISP1_WRAPPER>,
359 <&cru SCLK_ISP1>, <&cru SCLK_CIF_OUT>,
360 <&cru SCLK_CIF_OUT>, <&cru SCLK_DPHY_TX1RX1_CFG>,
361 <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_ISP1_WRAPPER>,
362 <&cru SCLK_DPHY_RX0_CFG>, <&cru PCLK_MIPI_DSI1>,
363 <&cru SCLK_MIPIDPHY_CFG>;
365 "aclk_isp1_noc", "aclk_isp1_wrapper",
366 "hclk_isp1_noc", "hclk_isp1_wrapper",
367 "clk_isp1", "clk_cif_out",
368 "clk_cif_pll", "pclk_dphytxrx",
369 "pclk_dphy_ref", "pclk_isp1",
370 "pclk_dphyrx", "pclk_mipi_dsi",
373 "cif_clkout","isp_dvp8bit0", "isp_mipi_fl",
374 "isp_mipi_fl_prefl", "isp_flash_as_gpio",
375 "isp_flash_as_trigger_out";
376 pinctrl-0 = <&cif_clkout>;
377 pinctrl-1 = <&isp_dvp_d0d7>;
378 pinctrl-2 = <&cif_clkout>;
379 pinctrl-3 = <&isp_prelight>;
380 pinctrl-4 = <&isp_flash_trigger_as_gpio>;
381 pinctrl-5 = <&isp_flash_trigger>;
382 rockchip,isp,mipiphy = <2>;
383 rockchip,isp,cifphy = <1>;
384 rockchip,isp,dsiphy,reg = <0xff968000 0x8000>;
385 rockchip,grf = <&grf>;
386 rockchip,cru = <&cru>;
387 rockchip,gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
388 rockchip,isp,iommu-enable = <1>;
389 power-domains = <&power RK3399_PD_ISP1>;
395 compatible = "rockchip,isp1_mmu";
396 reg = <0x0 0xff924000 0x0 0x100>,
397 <0x0 0xff925000 0x0 0x100>;
398 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
399 interrupt-names = "isp1_mmu";
402 hdmi_rk_fb: hdmi-rk-fb@ff940000 {
404 compatible = "rockchip,rk3399-hdmi";
405 reg = <0x0 0xff940000 0x0 0x20000>;
406 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>,
407 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH 0>;
408 clocks = <&cru PCLK_HDMI_CTRL>,
410 <&cru SCLK_HDMI_CEC>,
412 <&cru SCLK_HDMI_SFR>;
413 clock-names = "pclk_hdmi",
418 resets = <&cru SRST_HDMI_CTRL>;
419 reset-names = "hdmi";
420 pinctrl-names = "default", "gpio";
421 pinctrl-0 = <&hdmi_i2c_xfer &hdmi_cec>;
422 pinctrl-1 = <&i2c3_gpio>;
423 rockchip,grf = <&grf>;
424 power-domains = <&power RK3399_PD_HDCP>;
427 mipi0_rk_fb: mipi-rk-fb@ff960000 {
428 compatible = "rockchip,rk3399-dsi";
430 rockchip,grf = <&grf>;
431 reg = <0x0 0xff960000 0x0 0x8000>;
432 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
433 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>, <&cru SCLK_MIPIDPHY_CFG>;
434 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "mipi_dphy_cfg";
435 power-domains = <&power RK3399_PD_VIO>;
439 mipi1_rk_fb: mipi-rk-fb@ff968000 {
440 compatible = "rockchip,rk3399-dsi";
442 rockchip,grf = <&grf>;
443 reg = <0x0 0xff968000 0x0 0x8000>;
444 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH 0>;
445 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI1>, <&cru SCLK_MIPIDPHY_CFG>;
446 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "mipi_dphy_cfg";
447 power-domains = <&power RK3399_PD_VIO>;
451 edp_rk_fb: edp-rk-fb@ff970000 {
452 compatible = "rockchip,rk3399-edp-fb";
453 reg = <0x0 0xff970000 0x0 0x8000>;
454 rockchip,grf = <&grf>;
455 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
456 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>, <&cru PCLK_VIO_GRF>;
457 clock-names = "clk_edp", "pclk_edp", "clk_grf";
458 resets = <&cru SRST_P_EDP_CTRL>;
459 reset-names = "edp_apb";
461 power-domains = <&power RK3399_PD_EDP>;
467 /delete-property/ iommus;
468 /* 0 means ion, 1 means drm */
474 compatible = "rockchip,vpu_mmu";
479 /delete-property/ iommus;
480 /* 0 means ion, 1 means drm */
486 compatible = "rockchip,vdec_mmu";
495 compatible = "rockchip,iep_mmu";
501 cif_clkout: cif-clkout {
504 <2 11 RK_FUNC_3 &pcfg_pull_none>;
507 isp_dvp_d0d7: isp-dvp-d0d7 {
510 <2 0 RK_FUNC_3 &pcfg_pull_none>,
512 <2 1 RK_FUNC_3 &pcfg_pull_none>,
514 <2 2 RK_FUNC_3 &pcfg_pull_none>,
516 <2 3 RK_FUNC_3 &pcfg_pull_none>,
518 <2 4 RK_FUNC_3 &pcfg_pull_none>,
520 <2 5 RK_FUNC_3 &pcfg_pull_none>,
522 <2 6 RK_FUNC_3 &pcfg_pull_none>,
524 <2 7 RK_FUNC_3 &pcfg_pull_none>,
526 <2 8 RK_FUNC_3 &pcfg_pull_none>,
528 <2 9 RK_FUNC_3 &pcfg_pull_none>,
530 <2 10 RK_FUNC_3 &pcfg_pull_none>;
533 isp_shutter: isp-shutter {
536 <1 1 RK_FUNC_1 &pcfg_pull_none>,
538 <1 0 RK_FUNC_1 &pcfg_pull_none>;
541 isp_flash_trigger: isp-flash-trigger {
543 rockchip,pins = <1 3 RK_FUNC_1 &pcfg_pull_none>;
546 isp_prelight: isp-prelight {
548 rockchip,pins = <1 4 RK_FUNC_1 &pcfg_pull_none>;
551 isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
553 rockchip,pins = <1 3 RK_FUNC_GPIO &pcfg_pull_none>;
558 cam0_default_pins: cam0-default-pins {
559 rockchip,pins = <4 27 RK_FUNC_GPIO &pcfg_pull_none>,
560 <2 11 RK_FUNC_3 &pcfg_pull_none>;
562 cam0_sleep_pins: cam0-sleep-pins {
563 rockchip,pins = <4 27 RK_FUNC_3 &pcfg_pull_none>,
564 <2 11 RK_FUNC_GPIO &pcfg_pull_none>;