2 * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/clock/rk3368-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/irq.h>
46 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/display/rk_fb.h>
49 #include <dt-bindings/display/mipi_dsi.h>
50 #include <dt-bindings/power/rk3368-power.h>
51 #include <dt-bindings/soc/rockchip_boot-mode.h>
54 compatible = "rockchip,rk3368";
55 interrupt-parent = <&gic>;
78 #address-cells = <0x2>;
114 entry-method = "psci";
116 cpu_sleep: cpu-sleep-0 {
117 compatible = "arm,idle-state";
118 arm,psci-suspend-param = <0x1010000>;
119 entry-latency-us = <0x3fffffff>;
120 exit-latency-us = <0x40000000>;
121 min-residency-us = <0xffffffff>;
127 compatible = "arm,cortex-a53", "arm,armv8";
129 cpu-idle-states = <&cpu_sleep>;
130 enable-method = "psci";
131 clocks = <&cru ARMCLKL>;
132 operating-points-v2 = <&cluster1_opp>;
137 compatible = "arm,cortex-a53", "arm,armv8";
139 cpu-idle-states = <&cpu_sleep>;
140 enable-method = "psci";
141 clocks = <&cru ARMCLKL>;
142 operating-points-v2 = <&cluster1_opp>;
147 compatible = "arm,cortex-a53", "arm,armv8";
149 cpu-idle-states = <&cpu_sleep>;
150 enable-method = "psci";
151 clocks = <&cru ARMCLKL>;
152 operating-points-v2 = <&cluster1_opp>;
157 compatible = "arm,cortex-a53", "arm,armv8";
159 cpu-idle-states = <&cpu_sleep>;
160 enable-method = "psci";
161 clocks = <&cru ARMCLKL>;
162 operating-points-v2 = <&cluster1_opp>;
167 compatible = "arm,cortex-a53", "arm,armv8";
169 cpu-idle-states = <&cpu_sleep>;
170 enable-method = "psci";
171 clocks = <&cru ARMCLKB>;
172 operating-points-v2 = <&cluster0_opp>;
177 compatible = "arm,cortex-a53", "arm,armv8";
179 cpu-idle-states = <&cpu_sleep>;
180 enable-method = "psci";
181 clocks = <&cru ARMCLKB>;
182 operating-points-v2 = <&cluster0_opp>;
187 compatible = "arm,cortex-a53", "arm,armv8";
189 cpu-idle-states = <&cpu_sleep>;
190 enable-method = "psci";
191 clocks = <&cru ARMCLKB>;
192 operating-points-v2 = <&cluster0_opp>;
197 compatible = "arm,cortex-a53", "arm,armv8";
199 cpu-idle-states = <&cpu_sleep>;
200 enable-method = "psci";
201 clocks = <&cru ARMCLKB>;
202 operating-points-v2 = <&cluster0_opp>;
206 cluster0_opp: opp_table0 {
207 compatible = "operating-points-v2";
211 opp-hz = /bits/ 64 <408000000>;
212 opp-microvolt = <1200000>;
213 clock-latency-ns = <40000>;
217 opp-hz = /bits/ 64 <600000000>;
218 opp-microvolt = <1200000>;
221 opp-hz = /bits/ 64 <816000000>;
222 opp-microvolt = <1200000>;
225 opp-hz = /bits/ 64 <1008000000>;
226 opp-microvolt = <1200000>;
229 opp-hz = /bits/ 64 <1200000000>;
230 opp-microvolt = <1200000>;
234 cluster1_opp: opp_table1 {
235 compatible = "operating-points-v2";
239 opp-hz = /bits/ 64 <408000000>;
240 opp-microvolt = <1200000>;
241 clock-latency-ns = <40000>;
245 opp-hz = /bits/ 64 <600000000>;
246 opp-microvolt = <1200000>;
249 opp-hz = /bits/ 64 <816000000>;
250 opp-microvolt = <1200000>;
253 opp-hz = /bits/ 64 <1008000000>;
254 opp-microvolt = <1200000>;
259 compatible = "arm,armv8-pmuv3";
260 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
261 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
262 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
263 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
264 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
265 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
266 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
267 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
268 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
269 <&cpu_l3>, <&cpu_b0>, <&cpu_b1>,
270 <&cpu_b2>, <&cpu_b3>;
274 compatible = "arm,amba-bus";
275 #address-cells = <2>;
279 dmac_peri: dma-controller@ff250000 {
280 compatible = "arm,pl330", "arm,primecell";
281 reg = <0x0 0xff250000 0x0 0x4000>;
282 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
283 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
285 clocks = <&cru ACLK_DMAC_PERI>;
286 clock-names = "apb_pclk";
287 arm,pl330-broken-no-flushp;
290 dmac_bus: dma-controller@ff600000 {
291 compatible = "arm,pl330", "arm,primecell";
292 reg = <0x0 0xff600000 0x0 0x4000>;
293 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
294 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
296 clocks = <&cru ACLK_DMAC_BUS>;
297 clock-names = "apb_pclk";
298 arm,pl330-broken-no-flushp;
303 compatible = "arm,psci-0.2";
308 compatible = "arm,armv8-timer";
309 interrupts = <GIC_PPI 13
310 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
312 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
314 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
316 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
320 compatible = "fixed-clock";
321 clock-frequency = <24000000>;
322 clock-output-names = "xin24m";
326 sdmmc: rksdmmc@ff0c0000 {
327 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
328 reg = <0x0 0xff0c0000 0x0 0x4000>;
329 clock-freq-min-max = <400000 150000000>;
330 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
331 clock-names = "biu", "ciu";
332 fifo-depth = <0x100>;
333 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
337 sdio0: dwmmc@ff0d0000 {
338 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
339 reg = <0x0 0xff0d0000 0x0 0x4000>;
340 clock-freq-min-max = <400000 150000000>;
341 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
342 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
343 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
344 fifo-depth = <0x100>;
345 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
349 emmc: rksdmmc@ff0f0000 {
350 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
351 reg = <0x0 0xff0f0000 0x0 0x4000>;
352 clock-freq-min-max = <400000 150000000>;
353 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
354 clock-names = "biu", "ciu";
355 fifo-depth = <0x100>;
356 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
360 saradc: saradc@ff100000 {
361 compatible = "rockchip,saradc";
362 reg = <0x0 0xff100000 0x0 0x100>;
363 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
364 #io-channel-cells = <1>;
365 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
366 clock-names = "saradc", "apb_pclk";
371 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
372 reg = <0x0 0xff110000 0x0 0x1000>;
373 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
374 clock-names = "spiclk", "apb_pclk";
375 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
376 pinctrl-names = "default";
377 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
378 #address-cells = <1>;
384 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
385 reg = <0x0 0xff120000 0x0 0x1000>;
386 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
387 clock-names = "spiclk", "apb_pclk";
388 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
389 pinctrl-names = "default";
390 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
391 #address-cells = <1>;
397 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
398 reg = <0x0 0xff130000 0x0 0x1000>;
399 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
400 clock-names = "spiclk", "apb_pclk";
401 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
402 pinctrl-names = "default";
403 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
404 #address-cells = <1>;
410 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
411 reg = <0x0 0xff650000 0x0 0x1000>;
412 clocks = <&cru PCLK_I2C0>;
414 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
415 pinctrl-names = "default";
416 pinctrl-0 = <&i2c0_xfer>;
417 #address-cells = <1>;
423 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
424 reg = <0x0 0xff140000 0x0 0x1000>;
425 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
426 #address-cells = <1>;
429 clocks = <&cru PCLK_I2C2>;
430 pinctrl-names = "default";
431 pinctrl-0 = <&i2c2_xfer>;
436 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
437 reg = <0x0 0xff150000 0x0 0x1000>;
438 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
439 #address-cells = <1>;
442 clocks = <&cru PCLK_I2C3>;
443 pinctrl-names = "default";
444 pinctrl-0 = <&i2c3_xfer>;
449 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
450 reg = <0x0 0xff160000 0x0 0x1000>;
451 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
452 #address-cells = <1>;
455 clocks = <&cru PCLK_I2C4>;
456 pinctrl-names = "default";
457 pinctrl-0 = <&i2c4_xfer>;
462 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
463 reg = <0x0 0xff170000 0x0 0x1000>;
464 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
465 #address-cells = <1>;
468 clocks = <&cru PCLK_I2C5>;
469 pinctrl-names = "default";
470 pinctrl-0 = <&i2c5_xfer>;
474 uart0: serial@ff180000 {
475 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
476 reg = <0x0 0xff180000 0x0 0x100>;
477 clock-frequency = <24000000>;
478 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
479 clock-names = "baudclk", "apb_pclk";
480 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
486 uart1: serial@ff190000 {
487 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
488 reg = <0x0 0xff190000 0x0 0x100>;
489 clock-frequency = <24000000>;
490 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
491 clock-names = "baudclk", "apb_pclk";
492 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
498 uart3: serial@ff1b0000 {
499 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
500 reg = <0x0 0xff1b0000 0x0 0x100>;
501 clock-frequency = <24000000>;
502 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
503 clock-names = "baudclk", "apb_pclk";
504 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
510 uart4: serial@ff1c0000 {
511 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
512 reg = <0x0 0xff1c0000 0x0 0x100>;
513 clock-frequency = <24000000>;
514 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
515 clock-names = "baudclk", "apb_pclk";
516 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
522 gmac: ethernet@ff290000 {
523 compatible = "rockchip,rk3368-gmac";
524 reg = <0x0 0xff290000 0x0 0x10000>;
525 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
526 interrupt-names = "macirq";
527 rockchip,grf = <&grf>;
528 clocks = <&cru SCLK_MAC>,
529 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
530 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
531 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
532 clock-names = "stmmaceth",
533 "mac_clk_rx", "mac_clk_tx",
534 "clk_mac_ref", "clk_mac_refout",
535 "aclk_mac", "pclk_mac";
539 nandc0: nandc@ff400000 {
540 compatible = "rockchip,rk-nandc";
541 reg = <0x0 0xff400000 0x0 0x4000>;
542 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
544 clocks = <&cru SCLK_NANDC0>, <&cru HCLK_NANDC0>;
545 clock-names = "clk_nandc", "hclk_nandc";
549 usb_host0_ehci: usb@ff500000 {
550 compatible = "generic-ehci";
551 reg = <0x0 0xff500000 0x0 0x100>;
552 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
553 clocks = <&cru HCLK_HOST0>;
554 clock-names = "usbhost";
558 usb_otg: usb@ff580000 {
559 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
561 reg = <0x0 0xff580000 0x0 0x40000>;
562 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
563 clocks = <&cru HCLK_OTG0>;
566 g-np-tx-fifo-size = <16>;
567 g-rx-fifo-size = <275>;
568 g-tx-fifo-size = <256 128 128 64 64 32>;
573 ddrpctl: syscon@ff610000 {
574 compatible = "rockchip,rk3368-ddrpctl", "syscon";
575 reg = <0x0 0xff610000 0x0 0x400>;
579 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
580 reg = <0x0 0xff660000 0x0 0x1000>;
581 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
582 #address-cells = <1>;
585 clocks = <&cru PCLK_I2C1>;
586 pinctrl-names = "default";
587 pinctrl-0 = <&i2c1_xfer>;
592 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
593 reg = <0x0 0xff680000 0x0 0x10>;
595 pinctrl-names = "default";
596 pinctrl-0 = <&pwm0_pin>;
597 clocks = <&cru PCLK_PWM1>;
603 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
604 reg = <0x0 0xff680010 0x0 0x10>;
606 pinctrl-names = "default";
607 pinctrl-0 = <&pwm1_pin>;
608 clocks = <&cru PCLK_PWM1>;
614 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
615 reg = <0x0 0xff680020 0x0 0x10>;
617 clocks = <&cru PCLK_PWM1>;
623 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
624 reg = <0x0 0xff680030 0x0 0x10>;
626 pinctrl-names = "default";
627 pinctrl-0 = <&pwm3_pin>;
628 clocks = <&cru PCLK_PWM1>;
633 uart2: serial@ff690000 {
634 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
635 reg = <0x0 0xff690000 0x0 0x100>;
636 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
637 clock-names = "baudclk", "apb_pclk";
638 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
639 pinctrl-names = "default";
640 pinctrl-0 = <&uart2_xfer>;
646 pmu: power-management@ff730000 {
647 compatible = "rockchip,rk3368-pmu", "syscon", "simple-mfd";
648 reg = <0x0 0xff730000 0x0 0x1000>;
650 power: power-controller {
652 compatible = "rockchip,rk3368-power-controller";
653 #power-domain-cells = <1>;
654 #address-cells = <1>;
658 * Note: Although SCLK_* are the working clocks
659 * of device without including on the NOC, needed for
662 * The clocks on the which NOC:
663 * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
664 * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
665 * ACLK_RGA is on ACLK_RGA_NIU.
666 * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
668 * Which clock are device clocks:
670 * *_IEP IEP:Image Enhancement Processor
671 * *_ISP ISP:Image Signal Processing
672 * *_VIP VIP:Video Input Processor
673 * *_VOP* VOP:Visual Output Processor
681 reg = <RK3368_PD_VIO>;
682 clocks = <&cru ACLK_IEP>,
694 <&cru HCLK_VIO_HDCPMMU>,
695 <&cru PCLK_EDP_CTRL>,
696 <&cru PCLK_HDMI_CTRL>,
702 <&cru PCLK_MIPI_CSI>,
703 <&cru PCLK_MIPI_DSI0>,
704 <&cru SCLK_VOP0_PWM>,
710 <&cru SCLK_HDMI_CEC>,
711 <&cru SCLK_HDMI_HDCP>;
714 * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
715 * (video endecoder & decoder) clocks that on the
716 * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
719 reg = <RK3368_PD_VIDEO>;
720 clocks = <&cru ACLK_VIDEO>,
722 <&cru SCLK_HEVC_CABAC>,
723 <&cru SCLK_HEVC_CORE>;
726 * Note: ACLK_GPU is the GPU clock,
727 * and on the ACLK_GPU_NIU (NOC).
730 reg = <RK3368_PD_GPU_1>;
731 clocks = <&cru ACLK_GPU_CFG>,
733 <&cru SCLK_GPU_CORE>;
738 pmugrf: syscon@ff738000 {
739 compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd";
740 reg = <0x0 0xff738000 0x0 0x1000>;
743 compatible = "syscon-reboot-mode";
745 mode-normal = <BOOT_NORMAL>;
746 mode-recovery = <BOOT_RECOVERY>;
747 mode-bootloader = <BOOT_FASTBOOT>;
748 mode-loader = <BOOT_LOADER>;
753 cru: clock-controller@ff760000 {
754 compatible = "rockchip,rk3368-cru";
755 reg = <0x0 0xff760000 0x0 0x1000>;
756 rockchip,grf = <&grf>;
760 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
762 <&cru ACLK_BUS>, <&cru ACLK_PERI>,
763 <&cru HCLK_BUS>, <&cru HCLK_PERI>,
764 <&cru PCLK_BUS>, <&cru PCLK_PERI>;
765 assigned-clock-rates =
766 <576000000>, <400000000>,
768 <300000000>, <300000000>,
769 <150000000>, <150000000>,
770 <75000000>, <75000000>;
773 grf: syscon@ff770000 {
774 compatible = "rockchip,rk3368-grf", "syscon";
775 reg = <0x0 0xff770000 0x0 0x1000>;
778 wdt: watchdog@ff800000 {
779 compatible = "rockchip,rk3368-wdt", "snps,dw-wdt";
780 reg = <0x0 0xff800000 0x0 0x100>;
781 clocks = <&cru PCLK_WDT>;
782 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
786 gic: interrupt-controller@ffb71000 {
787 compatible = "arm,gic-400";
788 interrupt-controller;
789 #interrupt-cells = <3>;
790 #address-cells = <0>;
792 reg = <0x0 0xffb71000 0x0 0x1000>,
793 <0x0 0xffb72000 0x0 0x1000>,
794 <0x0 0xffb74000 0x0 0x2000>,
795 <0x0 0xffb76000 0x0 0x2000>;
796 interrupts = <GIC_PPI 9
797 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
800 gpu: rogue-g6110@ffa30000 {
801 compatible = "arm,rogue-G6110", "arm,rk3368-gpu";
802 reg = <0x0 0xffa30000 0x0 0x10000>;
804 <&cru SCLK_GPU_CORE>,
818 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
819 interrupt-names = "rogue-g6110-irq";
822 i2s_2ch: i2s-2ch@ff890000 {
823 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
824 reg = <0x0 0xff890000 0x0 0x1000>;
825 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
826 dmas = <&dmac_bus 6>, <&dmac_bus 7>;
827 dma-names = "tx", "rx";
828 clock-names = "i2s_clk", "i2s_hclk";
829 clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>;
833 i2s_8ch: i2s-8ch@ff898000 {
834 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
835 reg = <0x0 0xff898000 0x0 0x1000>;
836 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
837 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
838 dma-names = "tx", "rx";
839 clock-names = "i2s_clk", "i2s_hclk";
840 clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>;
841 pinctrl-names = "default";
842 pinctrl-0 = <&i2s_8ch_bus>;
847 compatible = "rockchip,rk3368-isp", "rockchip,isp";
848 reg = <0x0 0xff910000 0x0 0x10000>;
849 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
850 /*power-domains = <&power PD_VIO>;*/
852 <&cru ACLK_RGA>, <&cru HCLK_ISP>, <&cru SCLK_ISP>,
853 <&cru SCLK_ISP>, <&cru PCLK_ISP>, <&cru SCLK_VIP_OUT>,
854 <&cru SCLK_VIP_OUT>, <&cru PCLK_MIPI_CSI>,
855 <&cru PCLK_DPHYRX>, <&cru ACLK_VIO0_NOC>;
857 "aclk_isp", "hclk_isp", "clk_isp",
858 "clk_isp_jpe", "pclkin_isp", "clk_cif_out",
859 "clk_cif_pll", "hclk_mipiphy1",
860 "pclk_dphyrx", "clk_vio0_noc";
862 "default", "isp_dvp8bit2", "isp_dvp10bit", "isp_dvp12bit",
863 "isp_dvp8bit0", "isp_dvp8bit4", "isp_mipi_fl",
864 "isp_mipi_fl_prefl", "isp_flash_as_gpio",
865 "isp_flash_as_trigger_out";
866 pinctrl-0 = <&cif_clkout>;
867 pinctrl-1 = <&cif_clkout &isp_dvp_d2d9>;
868 pinctrl-2 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1>;
869 pinctrl-3 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1 &isp_dvp_d10d11>;
870 pinctrl-4 = <&cif_clkout &isp_dvp_d0d7>;
871 pinctrl-5 = <&cif_clkout &isp_dvp_d4d11>;
872 pinctrl-6 = <&cif_clkout>;
873 pinctrl-7 = <&cif_clkout &isp_prelight>;
874 pinctrl-8 = <&isp_flash_trigger_as_gpio>;
875 pinctrl-9 = <&isp_flash_trigger>;
876 rockchip,isp,mipiphy = <2>;
877 rockchip,isp,cifphy = <1>;
878 rockchip,isp,mipiphy1,reg = <0xff964000 0x4000>;
879 rockchip,isp,csiphy,reg = <0xff96C000 0x4000>;
880 rockchip,grf = <&grf>;
881 rockchip,cru = <&cru>;
882 rockchip,gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
883 rockchip,isp,iommu_enable = <1>;
888 compatible = "rockchip,rga2";
890 reg = <0x0 0xff920000 0x0 0x1000>;
891 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
892 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
893 clock-names = "aclk_rga", "hclk_rga", "clk_rga";
898 compatible = "rockchip,rk3368-pinctrl";
899 rockchip,grf = <&grf>;
900 rockchip,pmu = <&pmugrf>;
901 #address-cells = <0x2>;
905 gpio0: gpio0@ff750000 {
906 compatible = "rockchip,gpio-bank";
907 reg = <0x0 0xff750000 0x0 0x100>;
908 clocks = <&cru PCLK_GPIO0>;
909 interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>;
914 interrupt-controller;
915 #interrupt-cells = <0x2>;
918 gpio1: gpio1@ff780000 {
919 compatible = "rockchip,gpio-bank";
920 reg = <0x0 0xff780000 0x0 0x100>;
921 clocks = <&cru PCLK_GPIO1>;
922 interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>;
927 interrupt-controller;
928 #interrupt-cells = <0x2>;
931 gpio2: gpio2@ff790000 {
932 compatible = "rockchip,gpio-bank";
933 reg = <0x0 0xff790000 0x0 0x100>;
934 clocks = <&cru PCLK_GPIO2>;
935 interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>;
940 interrupt-controller;
941 #interrupt-cells = <0x2>;
944 gpio3: gpio3@ff7a0000 {
945 compatible = "rockchip,gpio-bank";
946 reg = <0x0 0xff7a0000 0x0 0x100>;
947 clocks = <&cru PCLK_GPIO3>;
948 interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>;
953 interrupt-controller;
954 #interrupt-cells = <0x2>;
957 pcfg_pull_up: pcfg-pull-up {
961 pcfg_pull_down: pcfg-pull-down {
965 pcfg_pull_none: pcfg-pull-none {
969 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
971 drive-strength = <12>;
976 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
980 rockchip,pins = <1 26 RK_FUNC_2 &pcfg_pull_up>;
984 rockchip,pins = <1 27 RK_FUNC_2 &pcfg_pull_up>;
987 emmc_bus1: emmc-bus1 {
988 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>;
991 emmc_bus4: emmc-bus4 {
992 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
993 <1 19 RK_FUNC_2 &pcfg_pull_up>,
994 <1 20 RK_FUNC_2 &pcfg_pull_up>,
995 <1 21 RK_FUNC_2 &pcfg_pull_up>;
998 emmc_bus8: emmc-bus8 {
999 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
1000 <1 19 RK_FUNC_2 &pcfg_pull_up>,
1001 <1 20 RK_FUNC_2 &pcfg_pull_up>,
1002 <1 21 RK_FUNC_2 &pcfg_pull_up>,
1003 <1 22 RK_FUNC_2 &pcfg_pull_up>,
1004 <1 23 RK_FUNC_2 &pcfg_pull_up>,
1005 <1 24 RK_FUNC_2 &pcfg_pull_up>,
1006 <1 25 RK_FUNC_2 &pcfg_pull_up>;
1011 rgmii_pins: rgmii-pins {
1012 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
1013 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1014 <3 19 RK_FUNC_1 &pcfg_pull_none>,
1015 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1016 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
1017 <3 10 RK_FUNC_1 &pcfg_pull_none_12ma>,
1018 <3 14 RK_FUNC_1 &pcfg_pull_none_12ma>,
1019 <3 28 RK_FUNC_1 &pcfg_pull_none_12ma>,
1020 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
1021 <3 15 RK_FUNC_1 &pcfg_pull_none>,
1022 <3 16 RK_FUNC_1 &pcfg_pull_none>,
1023 <3 17 RK_FUNC_1 &pcfg_pull_none>,
1024 <3 18 RK_FUNC_1 &pcfg_pull_none>,
1025 <3 25 RK_FUNC_1 &pcfg_pull_none>,
1026 <3 20 RK_FUNC_1 &pcfg_pull_none>;
1029 rmii_pins: rmii-pins {
1030 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
1031 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1032 <3 19 RK_FUNC_1 &pcfg_pull_none>,
1033 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1034 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
1035 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
1036 <3 15 RK_FUNC_1 &pcfg_pull_none>,
1037 <3 16 RK_FUNC_1 &pcfg_pull_none>,
1038 <3 20 RK_FUNC_1 &pcfg_pull_none>,
1039 <3 21 RK_FUNC_1 &pcfg_pull_none>;
1044 hdmii2c_xfer: hdmii2c-xfer {
1045 rockchip,pins = <3 26 RK_FUNC_1 &pcfg_pull_none>,
1046 <3 27 RK_FUNC_1 &pcfg_pull_none>;
1051 hdmi_cec: hdmi-cec {
1052 rockchip,pins = <3 23 RK_FUNC_1 &pcfg_pull_none>;
1057 i2c0_xfer: i2c0-xfer {
1058 rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
1059 <0 7 RK_FUNC_1 &pcfg_pull_none>;
1064 i2c1_xfer: i2c1-xfer {
1065 rockchip,pins = <2 21 RK_FUNC_1 &pcfg_pull_none>,
1066 <2 22 RK_FUNC_1 &pcfg_pull_none>;
1071 i2c2_xfer: i2c2-xfer {
1072 rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_none>,
1073 <3 31 RK_FUNC_2 &pcfg_pull_none>;
1078 i2c3_xfer: i2c3-xfer {
1079 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>,
1080 <1 17 RK_FUNC_1 &pcfg_pull_none>;
1085 i2c4_xfer: i2c4-xfer {
1086 rockchip,pins = <3 24 RK_FUNC_2 &pcfg_pull_none>,
1087 <3 25 RK_FUNC_2 &pcfg_pull_none>;
1092 i2c5_xfer: i2c5-xfer {
1093 rockchip,pins = <3 26 RK_FUNC_2 &pcfg_pull_none>,
1094 <3 27 RK_FUNC_2 &pcfg_pull_none>;
1096 i2c5_gpio: i2c5-gpio {
1097 rockchip,pins = <3 26 RK_FUNC_GPIO &pcfg_pull_none>,
1098 <3 27 RK_FUNC_GPIO &pcfg_pull_none>;
1103 i2s_8ch_bus: i2s-8ch-bus {
1104 rockchip,pins = <2 12 RK_FUNC_1 &pcfg_pull_none>,
1105 <2 13 RK_FUNC_1 &pcfg_pull_none>,
1106 <2 14 RK_FUNC_1 &pcfg_pull_none>,
1107 <2 15 RK_FUNC_1 &pcfg_pull_none>,
1108 <2 16 RK_FUNC_1 &pcfg_pull_none>,
1109 <2 17 RK_FUNC_1 &pcfg_pull_none>,
1110 <2 18 RK_FUNC_1 &pcfg_pull_none>,
1111 <2 19 RK_FUNC_1 &pcfg_pull_none>,
1112 <2 20 RK_FUNC_1 &pcfg_pull_none>;
1117 sdio0_bus1: sdio0-bus1 {
1118 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>;
1121 sdio0_bus4: sdio0-bus4 {
1122 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>,
1123 <2 29 RK_FUNC_1 &pcfg_pull_up>,
1124 <2 30 RK_FUNC_1 &pcfg_pull_up>,
1125 <2 31 RK_FUNC_1 &pcfg_pull_up>;
1128 sdio0_cmd: sdio0-cmd {
1129 rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_up>;
1132 sdio0_clk: sdio0-clk {
1133 rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none>;
1136 sdio0_cd: sdio0-cd {
1137 rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_up>;
1140 sdio0_wp: sdio0-wp {
1141 rockchip,pins = <3 3 RK_FUNC_1 &pcfg_pull_up>;
1144 sdio0_pwr: sdio0-pwr {
1145 rockchip,pins = <3 4 RK_FUNC_1 &pcfg_pull_up>;
1148 sdio0_bkpwr: sdio0-bkpwr {
1149 rockchip,pins = <3 5 RK_FUNC_1 &pcfg_pull_up>;
1152 sdio0_int: sdio0-int {
1153 rockchip,pins = <3 6 RK_FUNC_1 &pcfg_pull_up>;
1158 sdmmc_clk: sdmmc-clk {
1159 rockchip,pins = <2 9 RK_FUNC_1 &pcfg_pull_none>;
1162 sdmmc_cmd: sdmmc-cmd {
1163 rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_up>;
1166 sdmmc_cd: sdmcc-cd {
1167 rockchip,pins = <2 11 RK_FUNC_1 &pcfg_pull_up>;
1170 sdmmc_bus1: sdmmc-bus1 {
1171 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>;
1174 sdmmc_bus4: sdmmc-bus4 {
1175 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>,
1176 <2 6 RK_FUNC_1 &pcfg_pull_up>,
1177 <2 7 RK_FUNC_1 &pcfg_pull_up>,
1178 <2 8 RK_FUNC_1 &pcfg_pull_up>;
1183 spi0_clk: spi0-clk {
1184 rockchip,pins = <1 29 RK_FUNC_2 &pcfg_pull_up>;
1186 spi0_cs0: spi0-cs0 {
1187 rockchip,pins = <1 24 RK_FUNC_3 &pcfg_pull_up>;
1189 spi0_cs1: spi0-cs1 {
1190 rockchip,pins = <1 25 RK_FUNC_3 &pcfg_pull_up>;
1193 rockchip,pins = <1 23 RK_FUNC_3 &pcfg_pull_up>;
1196 rockchip,pins = <1 22 RK_FUNC_3 &pcfg_pull_up>;
1201 spi1_clk: spi1-clk {
1202 rockchip,pins = <1 14 RK_FUNC_2 &pcfg_pull_up>;
1204 spi1_cs0: spi1-cs0 {
1205 rockchip,pins = <1 15 RK_FUNC_2 &pcfg_pull_up>;
1207 spi1_cs1: spi1-cs1 {
1208 rockchip,pins = <3 28 RK_FUNC_2 &pcfg_pull_up>;
1211 rockchip,pins = <1 16 RK_FUNC_2 &pcfg_pull_up>;
1214 rockchip,pins = <1 17 RK_FUNC_2 &pcfg_pull_up>;
1219 spi2_clk: spi2-clk {
1220 rockchip,pins = <0 12 RK_FUNC_2 &pcfg_pull_up>;
1222 spi2_cs0: spi2-cs0 {
1223 rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>;
1226 rockchip,pins = <0 10 RK_FUNC_2 &pcfg_pull_up>;
1229 rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>;
1234 uart0_xfer: uart0-xfer {
1235 rockchip,pins = <2 24 RK_FUNC_1 &pcfg_pull_up>,
1236 <2 25 RK_FUNC_1 &pcfg_pull_none>;
1239 uart0_cts: uart0-cts {
1240 rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>;
1243 uart0_rts: uart0-rts {
1244 rockchip,pins = <2 27 RK_FUNC_1 &pcfg_pull_none>;
1249 uart1_xfer: uart1-xfer {
1250 rockchip,pins = <0 20 RK_FUNC_3 &pcfg_pull_up>,
1251 <0 21 RK_FUNC_3 &pcfg_pull_none>;
1254 uart1_cts: uart1-cts {
1255 rockchip,pins = <0 22 RK_FUNC_3 &pcfg_pull_none>;
1258 uart1_rts: uart1-rts {
1259 rockchip,pins = <0 23 RK_FUNC_3 &pcfg_pull_none>;
1264 uart2_xfer: uart2-xfer {
1265 rockchip,pins = <2 6 RK_FUNC_2 &pcfg_pull_up>,
1266 <2 5 RK_FUNC_2 &pcfg_pull_none>;
1268 /* no rts / cts for uart2 */
1272 uart3_xfer: uart3-xfer {
1273 rockchip,pins = <3 29 RK_FUNC_2 &pcfg_pull_up>,
1274 <3 30 RK_FUNC_3 &pcfg_pull_none>;
1277 uart3_cts: uart3-cts {
1278 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none>;
1281 uart3_rts: uart3-rts {
1282 rockchip,pins = <3 17 RK_FUNC_2 &pcfg_pull_none>;
1287 uart4_xfer: uart4-xfer {
1288 rockchip,pins = <0 27 RK_FUNC_3 &pcfg_pull_up>,
1289 <0 26 RK_FUNC_3 &pcfg_pull_none>;
1292 uart4_cts: uart4-cts {
1293 rockchip,pins = <0 24 RK_FUNC_3 &pcfg_pull_none>;
1296 uart4_rts: uart4-rts {
1297 rockchip,pins = <0 25 RK_FUNC_3 &pcfg_pull_none>;
1302 pwm0_pin: pwm0-pin {
1303 rockchip,pins = <3 8 RK_FUNC_2 &pcfg_pull_none>;
1306 vop_pwm_pin: vop-pwm {
1307 rockchip,pins = <3 8 RK_FUNC_3 &pcfg_pull_none>;
1312 pwm1_pin: pwm1-pin {
1313 rockchip,pins = <0 8 RK_FUNC_2 &pcfg_pull_none>;
1318 pwm3_pin: pwm3-pin {
1319 rockchip,pins = <3 29 RK_FUNC_3 &pcfg_pull_none>;
1324 lcdc_lcdc: lcdc-lcdc {
1326 <0 14 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D10
1327 <0 15 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D11
1328 <0 16 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D12
1329 <0 17 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D13
1330 <0 18 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D14
1331 <0 18 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D15
1332 <0 20 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D16
1333 <0 21 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D17
1334 <0 22 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D18
1335 <0 23 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D19
1336 <0 24 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D20
1337 <0 25 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D21
1338 <0 26 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D22
1339 <0 27 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D23
1340 <0 31 RK_FUNC_1 &pcfg_pull_none>,//DCLK
1341 <0 30 RK_FUNC_1 &pcfg_pull_none>,//DEN
1342 <0 28 RK_FUNC_1 &pcfg_pull_none>,//HSYNC
1343 <0 29 RK_FUNC_1 &pcfg_pull_none>;//VSYN
1346 lcdc_gpio: lcdc-gpio {
1348 <0 14 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D10
1349 <0 15 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D11
1350 <0 16 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D12
1351 <0 17 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D13
1352 <0 18 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D14
1353 <0 19 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D15
1354 <0 20 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D16
1355 <0 21 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D17
1356 <0 22 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D18
1357 <0 23 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D19
1358 <0 24 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D20
1359 <0 25 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D21
1360 <0 26 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D22
1361 <0 27 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D23
1362 <0 31 RK_FUNC_GPIO &pcfg_pull_none>,//DCLK
1363 <0 30 RK_FUNC_GPIO &pcfg_pull_none>,//DEN
1364 <0 28 RK_FUNC_GPIO &pcfg_pull_none>,//HSYNC
1365 <0 29 RK_FUNC_GPIO &pcfg_pull_none>;//VSYN
1370 cif_clkout: cif-clkout {
1371 rockchip,pins = <1 11 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
1374 isp_dvp_d2d9: isp-dvp-d2d9 {
1376 <1 0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
1377 <1 1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
1378 <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1379 <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1380 <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1381 <1 5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
1382 <1 6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
1383 <1 7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
1384 <1 8 RK_FUNC_1 &pcfg_pull_none>,//cif_sync
1385 <1 9 RK_FUNC_1 &pcfg_pull_none>,//cif_href
1386 <1 10 RK_FUNC_1 &pcfg_pull_none>,//cif_clkin
1387 <1 11 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
1390 isp_dvp_d0d1: isp-dvp-d0d1 {
1392 <1 12 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
1393 <1 13 RK_FUNC_1 &pcfg_pull_none>;//cif_data1
1396 isp_dvp_d10d11:isp_d10d11 {
1398 <1 14 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
1399 <1 15 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
1402 isp_dvp_d0d7: isp-dvp-d0d7 {
1404 <1 12 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
1405 <1 13 RK_FUNC_1 &pcfg_pull_none>,//cif_data1
1406 <1 0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
1407 <1 1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
1408 <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1409 <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1410 <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1411 <1 5 RK_FUNC_1 &pcfg_pull_none>;//cif_data7
1414 isp_dvp_d4d11: isp-dvp-d4d11 {
1416 <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1417 <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1418 <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1419 <1 5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
1420 <1 6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
1421 <1 7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
1422 <1 14 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
1423 <1 17 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
1426 isp_shutter: isp-shutter {
1428 <3 19 RK_FUNC_2 &pcfg_pull_none>, //SHUTTEREN
1429 <3 22 RK_FUNC_2 &pcfg_pull_none>;//SHUTTERTRIG
1432 isp_flash_trigger: isp-flash-trigger {
1433 rockchip,pins = <3 20 RK_FUNC_2 &pcfg_pull_none>; //ISP_FLASHTRIGOU
1436 isp_prelight: isp-prelight {
1437 rockchip,pins = <3 21 RK_FUNC_2 &pcfg_pull_none>;//ISP_PRELIGHTTRIG
1440 isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
1441 rockchip,pins = <3 20 RK_FUNC_GPIO &pcfg_pull_none>;//ISP_FLASHTRIGOU
1447 compatible = "rockchip,rk-fb";
1448 rockchip,disp-mode = <NO_DUAL>;
1449 status = "disabled";
1453 compatible = "rockchip,screen";
1454 status = "disabled";
1457 lcdc: lcdc@ff930000 {
1458 compatible = "rockchip,rk3368-lcdc";
1459 rockchip,grf = <&grf>;
1460 rockchip,pmugrf = <&pmugrf>;
1461 rockchip,cru = <&cru>;
1462 rockchip,prop = <PRMRY>;
1463 rockchip,pwr18 = <0>;
1464 rockchip,iommu-enabled = <1>;
1465 reg = <0x0 0xff930000 0x0 0x10000>;
1466 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1467 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
1468 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
1469 /*power-domains = <&power PD_VIO>;*/
1470 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
1471 reset-names = "axi", "ahb", "dclk";
1472 status = "disabled";
1475 mipi: mipi@ff960000 {
1476 compatible = "rockchip,rk3368-dsi";
1477 rockchip,prop = <0>;
1478 reg = <0x0 0xff960000 0x0 0x4000>, <0x0 0xff968000 0x0 0x4000>;
1479 reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
1480 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1481 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX0>, <&cru PCLK_MIPI_DSI0>;
1482 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pclk_mipi_dsi_host";
1483 /*power-domains = <&power PD_VIO>;*/
1484 status = "disabled";
1487 lvds: lvds@ff968000 {
1488 compatible = "rockchip,rk3368-lvds";
1489 rockchip,grf = <&grf>;
1490 reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
1491 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
1492 clocks = <&cru PCLK_DPHYTX0>, <&cru PCLK_MIPI_DSI0>;
1493 clock-names = "pclk_lvds", "pclk_lvds_ctl";
1494 /*power-domains = <&power PD_VIO>;*/
1495 status = "disabled";
1499 compatible = "rockchip,rk32-edp";
1500 reg = <0x0 0xff970000 0x0 0x4000>;
1501 rockchip,grf = <&grf>;
1502 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
1503 clocks = <&cru SCLK_EDP>, <&cru SCLK_EDP_24M>, <&cru PCLK_EDP_CTRL>;
1504 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
1505 /*power-domains = <&power PD_VIO>;*/
1506 resets = <&cru SRST_EDP_24M>, <&cru SRST_EDP>;
1507 reset-names = "edp_24m", "edp_apb";
1508 status = "disabled";
1511 hdmi: hdmi@ff980000 {
1512 compatible = "rockchip,rk3368-hdmi";
1513 reg = <0x0 0xff980000 0x0 0x20000>;
1514 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1515 clocks = <&cru PCLK_HDMI_CTRL>,
1516 <&cru SCLK_HDMI_HDCP>,
1517 <&cru SCLK_HDMI_CEC>;
1518 clock-names = "pclk_hdmi", "hdcp_clk_hdmi", "cec_clk_hdmi";
1519 /*power-domains = <&power PD_VIO>;*/
1520 resets = <&cru SRST_HDMI>;
1521 reset-names = "hdmi";
1522 pinctrl-names = "default", "gpio";
1523 pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>;
1524 pinctrl-1 = <&i2c5_gpio>;
1525 status = "disabled";
1530 compatible = "rockchip,iep_mmu";
1531 reg = <0x0 0xff900800 0x0 0x100>;
1532 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1533 interrupt-names = "iep_mmu";
1534 status = "disabled";
1539 compatible = "rockchip,vip_mmu";
1540 reg = <0x0 0xff950800 0x0 0x100>;
1541 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1542 interrupt-names = "vip_mmu";
1543 status = "disabled";
1546 vopb_mmu: vopb-mmu {
1548 compatible = "rockchip,vopb_mmu";
1549 reg = <0x0 0xff930300 0x0 0x100>;
1550 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1551 interrupt-names = "vop_mmu";
1552 status = "disabled";
1556 dbgname = "isp_mmu";
1557 compatible = "rockchip,isp_mmu";
1558 reg = <0x0 0xff914000 0x0 0x100>,
1559 <0x0 0xff915000 0x0 0x100>;
1560 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1561 interrupt-names = "isp_mmu";
1562 status = "disabled";
1565 hdcp_mmu: hdcp-mmu {
1566 dbgname = "hdcp_mmu";
1567 compatible = "rockchip,hdcp_mmu";
1568 reg = <0x0 0xff940000 0x0 0x100>;
1569 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1570 interrupt-names = "hdcp_mmu";
1571 status = "disabled";
1574 hevc_mmu: hevc-mmu {
1576 compatible = "rockchip,hevc_mmu";
1577 reg = <0x0 0xff9a0440 0x0 0x40>,
1578 <0x0 0xff9a0480 0x0 0x40>;
1579 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1580 interrupt-names = "hevc_mmu";
1581 status = "disabled";
1586 compatible = "rockchip,vpu_mmu";
1587 reg = <0x0 0xff9a0800 0x0 0x100>;
1588 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1589 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1590 interrupt-names = "vepu_mmu", "vdpu_mmu";
1591 status = "disabled";