2 * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/clock/rk3368-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/irq.h>
46 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/display/rk_fb.h>
51 compatible = "rockchip,rk3368";
52 interrupt-parent = <&gic>;
75 #address-cells = <0x2>;
111 entry-method = "psci";
113 cpu_sleep: cpu-sleep-0 {
114 compatible = "arm,idle-state";
115 arm,psci-suspend-param = <0x1010000>;
116 entry-latency-us = <0x3fffffff>;
117 exit-latency-us = <0x40000000>;
118 min-residency-us = <0xffffffff>;
124 compatible = "arm,cortex-a53", "arm,armv8";
126 cpu-idle-states = <&cpu_sleep>;
127 enable-method = "psci";
132 compatible = "arm,cortex-a53", "arm,armv8";
134 cpu-idle-states = <&cpu_sleep>;
135 enable-method = "psci";
140 compatible = "arm,cortex-a53", "arm,armv8";
142 cpu-idle-states = <&cpu_sleep>;
143 enable-method = "psci";
148 compatible = "arm,cortex-a53", "arm,armv8";
150 cpu-idle-states = <&cpu_sleep>;
151 enable-method = "psci";
156 compatible = "arm,cortex-a53", "arm,armv8";
158 cpu-idle-states = <&cpu_sleep>;
159 enable-method = "psci";
164 compatible = "arm,cortex-a53", "arm,armv8";
166 cpu-idle-states = <&cpu_sleep>;
167 enable-method = "psci";
172 compatible = "arm,cortex-a53", "arm,armv8";
174 cpu-idle-states = <&cpu_sleep>;
175 enable-method = "psci";
180 compatible = "arm,cortex-a53", "arm,armv8";
182 cpu-idle-states = <&cpu_sleep>;
183 enable-method = "psci";
188 compatible = "arm,armv8-pmuv3";
189 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
190 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
191 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
192 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
193 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
194 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
195 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
196 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
197 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
198 <&cpu_l3>, <&cpu_b0>, <&cpu_b1>,
199 <&cpu_b2>, <&cpu_b3>;
203 compatible = "arm,amba-bus";
204 #address-cells = <2>;
208 dmac_peri: dma-controller@ff250000 {
209 compatible = "arm,pl330", "arm,primecell";
210 reg = <0x0 0xff250000 0x0 0x4000>;
211 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
212 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
214 clocks = <&cru ACLK_DMAC_PERI>;
215 clock-names = "apb_pclk";
218 dmac_bus: dma-controller@ff600000 {
219 compatible = "arm,pl330", "arm,primecell";
220 reg = <0x0 0xff600000 0x0 0x4000>;
221 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
222 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
224 clocks = <&cru ACLK_DMAC_BUS>;
225 clock-names = "apb_pclk";
230 compatible = "arm,psci-0.2";
235 compatible = "arm,armv8-timer";
236 interrupts = <GIC_PPI 13
237 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
239 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
241 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
243 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
247 compatible = "fixed-clock";
248 clock-frequency = <24000000>;
249 clock-output-names = "xin24m";
253 sdmmc: rksdmmc@ff0c0000 {
254 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
255 reg = <0x0 0xff0c0000 0x0 0x4000>;
256 clock-freq-min-max = <400000 150000000>;
257 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
258 clock-names = "biu", "ciu";
259 fifo-depth = <0x100>;
260 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
264 sdio0: dwmmc@ff0d0000 {
265 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
266 reg = <0x0 0xff0d0000 0x0 0x4000>;
267 clock-freq-min-max = <400000 150000000>;
268 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
269 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
270 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
271 fifo-depth = <0x100>;
272 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
276 emmc: rksdmmc@ff0f0000 {
277 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
278 reg = <0x0 0xff0f0000 0x0 0x4000>;
279 clock-freq-min-max = <400000 150000000>;
280 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
281 clock-names = "biu", "ciu";
282 fifo-depth = <0x100>;
283 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
287 saradc: saradc@ff100000 {
288 compatible = "rockchip,saradc";
289 reg = <0x0 0xff100000 0x0 0x100>;
290 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
291 #io-channel-cells = <1>;
292 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
293 clock-names = "saradc", "apb_pclk";
298 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
299 reg = <0x0 0xff110000 0x0 0x1000>;
300 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
301 clock-names = "spiclk", "apb_pclk";
302 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
303 pinctrl-names = "default";
304 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
305 #address-cells = <1>;
311 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
312 reg = <0x0 0xff120000 0x0 0x1000>;
313 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
314 clock-names = "spiclk", "apb_pclk";
315 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
316 pinctrl-names = "default";
317 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
318 #address-cells = <1>;
324 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
325 reg = <0x0 0xff130000 0x0 0x1000>;
326 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
327 clock-names = "spiclk", "apb_pclk";
328 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
329 pinctrl-names = "default";
330 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
331 #address-cells = <1>;
337 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
338 reg = <0x0 0xff140000 0x0 0x1000>;
339 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
340 #address-cells = <1>;
343 clocks = <&cru PCLK_I2C1>;
344 pinctrl-names = "default";
345 pinctrl-0 = <&i2c1_xfer>;
350 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
351 reg = <0x0 0xff150000 0x0 0x1000>;
352 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
353 #address-cells = <1>;
356 clocks = <&cru PCLK_I2C3>;
357 pinctrl-names = "default";
358 pinctrl-0 = <&i2c3_xfer>;
363 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
364 reg = <0x0 0xff160000 0x0 0x1000>;
365 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
366 #address-cells = <1>;
369 clocks = <&cru PCLK_I2C4>;
370 pinctrl-names = "default";
371 pinctrl-0 = <&i2c4_xfer>;
376 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
377 reg = <0x0 0xff170000 0x0 0x1000>;
378 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
379 #address-cells = <1>;
382 clocks = <&cru PCLK_I2C5>;
383 pinctrl-names = "default";
384 pinctrl-0 = <&i2c5_xfer>;
388 uart0: serial@ff180000 {
389 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
390 reg = <0x0 0xff180000 0x0 0x100>;
391 clock-frequency = <24000000>;
392 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
393 clock-names = "baudclk", "apb_pclk";
394 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
400 uart1: serial@ff190000 {
401 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
402 reg = <0x0 0xff190000 0x0 0x100>;
403 clock-frequency = <24000000>;
404 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
405 clock-names = "baudclk", "apb_pclk";
406 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
412 uart3: serial@ff1b0000 {
413 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
414 reg = <0x0 0xff1b0000 0x0 0x100>;
415 clock-frequency = <24000000>;
416 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
417 clock-names = "baudclk", "apb_pclk";
418 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
424 uart4: serial@ff1c0000 {
425 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
426 reg = <0x0 0xff1c0000 0x0 0x100>;
427 clock-frequency = <24000000>;
428 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
429 clock-names = "baudclk", "apb_pclk";
430 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
436 gmac: ethernet@ff290000 {
437 compatible = "rockchip,rk3368-gmac";
438 reg = <0x0 0xff290000 0x0 0x10000>;
439 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
440 interrupt-names = "macirq";
441 rockchip,grf = <&grf>;
442 clocks = <&cru SCLK_MAC>,
443 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
444 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
445 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
446 clock-names = "stmmaceth",
447 "mac_clk_rx", "mac_clk_tx",
448 "clk_mac_ref", "clk_mac_refout",
449 "aclk_mac", "pclk_mac";
453 usb_host0_ehci: usb@ff500000 {
454 compatible = "generic-ehci";
455 reg = <0x0 0xff500000 0x0 0x100>;
456 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
457 clocks = <&cru HCLK_HOST0>;
458 clock-names = "usbhost";
462 usb_otg: usb@ff580000 {
463 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
465 reg = <0x0 0xff580000 0x0 0x40000>;
466 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
467 clocks = <&cru HCLK_OTG0>;
470 g-np-tx-fifo-size = <16>;
471 g-rx-fifo-size = <275>;
472 g-tx-fifo-size = <256 128 128 64 64 32>;
477 ddrpctl: syscon@ff610000 {
478 compatible = "rockchip,rk3368-ddrpctl", "syscon";
479 reg = <0x0 0xff610000 0x0 0x400>;
483 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
484 reg = <0x0 0xff650000 0x0 0x1000>;
485 clocks = <&cru PCLK_I2C0>;
487 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
488 pinctrl-names = "default";
489 pinctrl-0 = <&i2c0_xfer>;
490 #address-cells = <1>;
496 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
497 reg = <0x0 0xff660000 0x0 0x1000>;
498 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
499 #address-cells = <1>;
502 clocks = <&cru PCLK_I2C2>;
503 pinctrl-names = "default";
504 pinctrl-0 = <&i2c2_xfer>;
509 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
510 reg = <0x0 0xff680000 0x0 0x10>;
512 pinctrl-names = "default";
513 pinctrl-0 = <&pwm0_pin>;
514 clocks = <&cru PCLK_PWM1>;
520 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
521 reg = <0x0 0xff680010 0x0 0x10>;
523 pinctrl-names = "default";
524 pinctrl-0 = <&pwm1_pin>;
525 clocks = <&cru PCLK_PWM1>;
531 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
532 reg = <0x0 0xff680020 0x0 0x10>;
534 clocks = <&cru PCLK_PWM1>;
540 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
541 reg = <0x0 0xff680030 0x0 0x10>;
543 pinctrl-names = "default";
544 pinctrl-0 = <&pwm3_pin>;
545 clocks = <&cru PCLK_PWM1>;
550 uart2: serial@ff690000 {
551 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
552 reg = <0x0 0xff690000 0x0 0x100>;
553 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
554 clock-names = "baudclk", "apb_pclk";
555 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
556 pinctrl-names = "default";
557 pinctrl-0 = <&uart2_xfer>;
563 pmu: power-management@ff730000 {
564 compatible = "rockchip,rk3368-pmu", "syscon";
565 reg = <0x0 0xff730000 0x0 0x1000>;
568 pmugrf: syscon@ff738000 {
569 compatible = "rockchip,rk3368-pmugrf", "syscon";
570 reg = <0x0 0xff738000 0x0 0x1000>;
573 cru: clock-controller@ff760000 {
574 compatible = "rockchip,rk3368-cru";
575 reg = <0x0 0xff760000 0x0 0x1000>;
576 rockchip,grf = <&grf>;
581 grf: syscon@ff770000 {
582 compatible = "rockchip,rk3368-grf", "syscon";
583 reg = <0x0 0xff770000 0x0 0x1000>;
586 wdt: watchdog@ff800000 {
587 compatible = "rockchip,rk3368-wdt", "snps,dw-wdt";
588 reg = <0x0 0xff800000 0x0 0x100>;
589 clocks = <&cru PCLK_WDT>;
590 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
594 gic: interrupt-controller@ffb71000 {
595 compatible = "arm,gic-400";
596 interrupt-controller;
597 #interrupt-cells = <3>;
598 #address-cells = <0>;
600 reg = <0x0 0xffb71000 0x0 0x1000>,
601 <0x0 0xffb72000 0x0 0x1000>,
602 <0x0 0xffb74000 0x0 0x2000>,
603 <0x0 0xffb76000 0x0 0x2000>;
604 interrupts = <GIC_PPI 9
605 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
608 i2s_2ch: i2s-2ch@ff890000 {
609 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
610 reg = <0x0 0xff898000 0x0 0x1000>;
611 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
612 #address-cells = <2>;
614 dmas = <&dmac_bus 6>, <&dmac_bus 7>;
615 dma-names = "tx", "rx";
616 clock-names = "i2s_hclk", "i2s_clk";
617 clocks = <&cru HCLK_I2S_2CH>, <&cru SCLK_I2S_2CH>;
621 i2s_8ch: i2s-8ch@ff898000 {
622 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
623 reg = <0x0 0xff898000 0x0 0x1000>;
624 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
625 #address-cells = <1>;
627 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
628 dma-names = "tx", "rx";
629 clock-names = "i2s_hclk", "i2s_clk";
630 clocks = <&cru HCLK_I2S_8CH>, <&cru SCLK_I2S_8CH>;
631 pinctrl-names = "default";
632 pinctrl-0 = <&i2s_8ch_bus>;
637 compatible = "rockchip,rk3368-pinctrl";
638 rockchip,grf = <&grf>;
639 rockchip,pmu = <&pmugrf>;
640 #address-cells = <0x2>;
644 gpio0: gpio0@ff750000 {
645 compatible = "rockchip,gpio-bank";
646 reg = <0x0 0xff750000 0x0 0x100>;
647 clocks = <&cru PCLK_GPIO0>;
648 interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>;
653 interrupt-controller;
654 #interrupt-cells = <0x2>;
657 gpio1: gpio1@ff780000 {
658 compatible = "rockchip,gpio-bank";
659 reg = <0x0 0xff780000 0x0 0x100>;
660 clocks = <&cru PCLK_GPIO1>;
661 interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>;
666 interrupt-controller;
667 #interrupt-cells = <0x2>;
670 gpio2: gpio2@ff790000 {
671 compatible = "rockchip,gpio-bank";
672 reg = <0x0 0xff790000 0x0 0x100>;
673 clocks = <&cru PCLK_GPIO2>;
674 interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>;
679 interrupt-controller;
680 #interrupt-cells = <0x2>;
683 gpio3: gpio3@ff7a0000 {
684 compatible = "rockchip,gpio-bank";
685 reg = <0x0 0xff7a0000 0x0 0x100>;
686 clocks = <&cru PCLK_GPIO3>;
687 interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>;
692 interrupt-controller;
693 #interrupt-cells = <0x2>;
696 pcfg_pull_up: pcfg-pull-up {
700 pcfg_pull_down: pcfg-pull-down {
704 pcfg_pull_none: pcfg-pull-none {
708 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
710 drive-strength = <12>;
715 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
719 rockchip,pins = <1 26 RK_FUNC_2 &pcfg_pull_up>;
723 rockchip,pins = <1 27 RK_FUNC_2 &pcfg_pull_up>;
726 emmc_bus1: emmc-bus1 {
727 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>;
730 emmc_bus4: emmc-bus4 {
731 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
732 <1 19 RK_FUNC_2 &pcfg_pull_up>,
733 <1 20 RK_FUNC_2 &pcfg_pull_up>,
734 <1 21 RK_FUNC_2 &pcfg_pull_up>;
737 emmc_bus8: emmc-bus8 {
738 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
739 <1 19 RK_FUNC_2 &pcfg_pull_up>,
740 <1 20 RK_FUNC_2 &pcfg_pull_up>,
741 <1 21 RK_FUNC_2 &pcfg_pull_up>,
742 <1 22 RK_FUNC_2 &pcfg_pull_up>,
743 <1 23 RK_FUNC_2 &pcfg_pull_up>,
744 <1 24 RK_FUNC_2 &pcfg_pull_up>,
745 <1 25 RK_FUNC_2 &pcfg_pull_up>;
750 rgmii_pins: rgmii-pins {
751 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
752 <3 24 RK_FUNC_1 &pcfg_pull_none>,
753 <3 19 RK_FUNC_1 &pcfg_pull_none>,
754 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
755 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
756 <3 10 RK_FUNC_1 &pcfg_pull_none_12ma>,
757 <3 14 RK_FUNC_1 &pcfg_pull_none_12ma>,
758 <3 28 RK_FUNC_1 &pcfg_pull_none_12ma>,
759 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
760 <3 15 RK_FUNC_1 &pcfg_pull_none>,
761 <3 16 RK_FUNC_1 &pcfg_pull_none>,
762 <3 17 RK_FUNC_1 &pcfg_pull_none>,
763 <3 18 RK_FUNC_1 &pcfg_pull_none>,
764 <3 25 RK_FUNC_1 &pcfg_pull_none>,
765 <3 20 RK_FUNC_1 &pcfg_pull_none>;
768 rmii_pins: rmii-pins {
769 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
770 <3 24 RK_FUNC_1 &pcfg_pull_none>,
771 <3 19 RK_FUNC_1 &pcfg_pull_none>,
772 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
773 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
774 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
775 <3 15 RK_FUNC_1 &pcfg_pull_none>,
776 <3 16 RK_FUNC_1 &pcfg_pull_none>,
777 <3 20 RK_FUNC_1 &pcfg_pull_none>,
778 <3 21 RK_FUNC_1 &pcfg_pull_none>;
783 i2c0_xfer: i2c0-xfer {
784 rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
785 <0 7 RK_FUNC_1 &pcfg_pull_none>;
790 i2c1_xfer: i2c1-xfer {
791 rockchip,pins = <2 21 RK_FUNC_1 &pcfg_pull_none>,
792 <2 22 RK_FUNC_1 &pcfg_pull_none>;
797 i2c2_xfer: i2c2-xfer {
798 rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_none>,
799 <3 31 RK_FUNC_2 &pcfg_pull_none>;
804 i2c3_xfer: i2c3-xfer {
805 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>,
806 <1 17 RK_FUNC_1 &pcfg_pull_none>;
811 i2c4_xfer: i2c4-xfer {
812 rockchip,pins = <3 24 RK_FUNC_2 &pcfg_pull_none>,
813 <3 25 RK_FUNC_2 &pcfg_pull_none>;
818 i2c5_xfer: i2c5-xfer {
819 rockchip,pins = <3 26 RK_FUNC_2 &pcfg_pull_none>,
820 <3 27 RK_FUNC_2 &pcfg_pull_none>;
825 i2s_8ch_bus: i2s-8ch-bus {
826 rockchip,pins = <2 12 RK_FUNC_1 &pcfg_pull_none>,
827 <2 13 RK_FUNC_1 &pcfg_pull_none>,
828 <2 14 RK_FUNC_1 &pcfg_pull_none>,
829 <2 15 RK_FUNC_1 &pcfg_pull_none>,
830 <2 16 RK_FUNC_1 &pcfg_pull_none>,
831 <2 17 RK_FUNC_1 &pcfg_pull_none>,
832 <2 18 RK_FUNC_1 &pcfg_pull_none>,
833 <2 19 RK_FUNC_1 &pcfg_pull_none>,
834 <2 20 RK_FUNC_1 &pcfg_pull_none>;
839 sdio0_bus1: sdio0-bus1 {
840 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>;
843 sdio0_bus4: sdio0-bus4 {
844 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>,
845 <2 29 RK_FUNC_1 &pcfg_pull_up>,
846 <2 30 RK_FUNC_1 &pcfg_pull_up>,
847 <2 31 RK_FUNC_1 &pcfg_pull_up>;
850 sdio0_cmd: sdio0-cmd {
851 rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_up>;
854 sdio0_clk: sdio0-clk {
855 rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none>;
859 rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_up>;
863 rockchip,pins = <3 3 RK_FUNC_1 &pcfg_pull_up>;
866 sdio0_pwr: sdio0-pwr {
867 rockchip,pins = <3 4 RK_FUNC_1 &pcfg_pull_up>;
870 sdio0_bkpwr: sdio0-bkpwr {
871 rockchip,pins = <3 5 RK_FUNC_1 &pcfg_pull_up>;
874 sdio0_int: sdio0-int {
875 rockchip,pins = <3 6 RK_FUNC_1 &pcfg_pull_up>;
880 sdmmc_clk: sdmmc-clk {
881 rockchip,pins = <2 9 RK_FUNC_1 &pcfg_pull_none>;
884 sdmmc_cmd: sdmmc-cmd {
885 rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_up>;
889 rockchip,pins = <2 11 RK_FUNC_1 &pcfg_pull_up>;
892 sdmmc_bus1: sdmmc-bus1 {
893 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>;
896 sdmmc_bus4: sdmmc-bus4 {
897 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>,
898 <2 6 RK_FUNC_1 &pcfg_pull_up>,
899 <2 7 RK_FUNC_1 &pcfg_pull_up>,
900 <2 8 RK_FUNC_1 &pcfg_pull_up>;
906 rockchip,pins = <1 29 RK_FUNC_2 &pcfg_pull_up>;
909 rockchip,pins = <1 24 RK_FUNC_3 &pcfg_pull_up>;
912 rockchip,pins = <1 25 RK_FUNC_3 &pcfg_pull_up>;
915 rockchip,pins = <1 23 RK_FUNC_3 &pcfg_pull_up>;
918 rockchip,pins = <1 22 RK_FUNC_3 &pcfg_pull_up>;
924 rockchip,pins = <1 14 RK_FUNC_2 &pcfg_pull_up>;
927 rockchip,pins = <1 15 RK_FUNC_2 &pcfg_pull_up>;
930 rockchip,pins = <3 28 RK_FUNC_2 &pcfg_pull_up>;
933 rockchip,pins = <1 16 RK_FUNC_2 &pcfg_pull_up>;
936 rockchip,pins = <1 17 RK_FUNC_2 &pcfg_pull_up>;
942 rockchip,pins = <0 12 RK_FUNC_2 &pcfg_pull_up>;
945 rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>;
948 rockchip,pins = <0 10 RK_FUNC_2 &pcfg_pull_up>;
951 rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>;
956 uart0_xfer: uart0-xfer {
957 rockchip,pins = <2 24 RK_FUNC_1 &pcfg_pull_up>,
958 <2 25 RK_FUNC_1 &pcfg_pull_none>;
961 uart0_cts: uart0-cts {
962 rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>;
965 uart0_rts: uart0-rts {
966 rockchip,pins = <2 27 RK_FUNC_1 &pcfg_pull_none>;
971 uart1_xfer: uart1-xfer {
972 rockchip,pins = <0 20 RK_FUNC_3 &pcfg_pull_up>,
973 <0 21 RK_FUNC_3 &pcfg_pull_none>;
976 uart1_cts: uart1-cts {
977 rockchip,pins = <0 22 RK_FUNC_3 &pcfg_pull_none>;
980 uart1_rts: uart1-rts {
981 rockchip,pins = <0 23 RK_FUNC_3 &pcfg_pull_none>;
986 uart2_xfer: uart2-xfer {
987 rockchip,pins = <2 6 RK_FUNC_2 &pcfg_pull_up>,
988 <2 5 RK_FUNC_2 &pcfg_pull_none>;
990 /* no rts / cts for uart2 */
994 uart3_xfer: uart3-xfer {
995 rockchip,pins = <3 29 RK_FUNC_2 &pcfg_pull_up>,
996 <3 30 RK_FUNC_3 &pcfg_pull_none>;
999 uart3_cts: uart3-cts {
1000 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none>;
1003 uart3_rts: uart3-rts {
1004 rockchip,pins = <3 17 RK_FUNC_2 &pcfg_pull_none>;
1009 uart4_xfer: uart4-xfer {
1010 rockchip,pins = <0 27 RK_FUNC_3 &pcfg_pull_up>,
1011 <0 26 RK_FUNC_3 &pcfg_pull_none>;
1014 uart4_cts: uart4-cts {
1015 rockchip,pins = <0 24 RK_FUNC_3 &pcfg_pull_none>;
1018 uart4_rts: uart4-rts {
1019 rockchip,pins = <0 25 RK_FUNC_3 &pcfg_pull_none>;
1024 pwm0_pin: pwm0-pin {
1025 rockchip,pins = <3 8 RK_FUNC_2 &pcfg_pull_none>;
1028 vop_pwm_pin: vop-pwm {
1029 rockchip,pins = <3 8 RK_FUNC_3 &pcfg_pull_none>;
1034 pwm1_pin: pwm1-pin {
1035 rockchip,pins = <0 8 RK_FUNC_2 &pcfg_pull_none>;
1040 pwm3_pin: pwm3-pin {
1041 rockchip,pins = <3 29 RK_FUNC_3 &pcfg_pull_none>;
1046 lcdc_lcdc: lcdc-lcdc {
1048 <0 14 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D10
1049 <0 15 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D11
1050 <0 16 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D12
1051 <0 17 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D13
1052 <0 18 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D14
1053 <0 18 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D15
1054 <0 20 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D16
1055 <0 21 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D17
1056 <0 22 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D18
1057 <0 23 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D19
1058 <0 24 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D20
1059 <0 25 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D21
1060 <0 26 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D22
1061 <0 27 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D23
1062 <0 31 RK_FUNC_1 &pcfg_pull_none>,//DCLK
1063 <0 30 RK_FUNC_1 &pcfg_pull_none>,//DEN
1064 <0 28 RK_FUNC_1 &pcfg_pull_none>,//HSYNC
1065 <0 29 RK_FUNC_1 &pcfg_pull_none>;//VSYN
1068 lcdc_gpio: lcdc-gpio {
1070 <0 14 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D10
1071 <0 15 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D11
1072 <0 16 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D12
1073 <0 17 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D13
1074 <0 18 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D14
1075 <0 19 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D15
1076 <0 20 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D16
1077 <0 21 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D17
1078 <0 22 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D18
1079 <0 23 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D19
1080 <0 24 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D20
1081 <0 25 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D21
1082 <0 26 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D22
1083 <0 27 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D23
1084 <0 31 RK_FUNC_GPIO &pcfg_pull_none>,//DCLK
1085 <0 30 RK_FUNC_GPIO &pcfg_pull_none>,//DEN
1086 <0 28 RK_FUNC_GPIO &pcfg_pull_none>,//HSYNC
1087 <0 29 RK_FUNC_GPIO &pcfg_pull_none>;//VSYN
1093 compatible = "rockchip,rk-fb";
1094 rockchip,disp-mode = <NO_DUAL>;
1095 status = "disabled";
1099 compatible = "rockchip,screen";
1100 status = "disabled";
1103 lcdc: lcdc@ff930000 {
1104 compatible = "rockchip,rk3368-lcdc";
1105 rockchip,grf = <&grf>;
1106 rockchip,pmugrf = <&pmugrf>;
1107 rockchip,cru = <&cru>;
1108 rockchip,prop = <PRMRY>;
1109 rockchip,pwr18 = <0>;
1110 rockchip,iommu-enabled = <1>;
1111 reg = <0x0 0xff930000 0x0 0x10000>;
1112 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1113 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
1114 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
1115 /*power-domains = <&power PD_VIO>;*/
1116 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
1117 reset-names = "axi", "ahb", "dclk";
1118 status = "disabled";
1121 mipi: mipi@ff960000 {
1122 compatible = "rockchip,rk3368-dsi";
1123 rockchip,prop = <0>;
1124 reg = <0x0 0xff960000 0x0 0x4000>, <0x0 0xff968000 0x0 0x4000>;
1125 reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
1126 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1127 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX0>, <&cru PCLK_MIPI_DSI0>;
1128 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pclk_mipi_dsi_host";
1129 /*power-domains = <&power PD_VIO>;*/
1130 status = "disabled";
1133 lvds: lvds@ff968000 {
1134 compatible = "rockchip,rk3368-lvds";
1135 rockchip,grf = <&grf>;
1136 reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
1137 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
1138 clocks = <&cru PCLK_DPHYTX0>, <&cru PCLK_MIPI_DSI0>;
1139 clock-names = "pclk_lvds", "pclk_lvds_ctl";
1140 /*power-domains = <&power PD_VIO>;*/
1141 status = "disabled";
1145 compatible = "rockchip,rk32-edp";
1146 reg = <0x0 0xff970000 0x0 0x4000>;
1147 rockchip,grf = <&grf>;
1148 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
1149 clocks = <&cru SCLK_EDP>, <&cru SCLK_EDP_24M>, <&cru PCLK_EDP_CTRL>;
1150 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
1151 /*power-domains = <&power PD_VIO>;*/
1152 resets = <&cru SRST_EDP_24M>, <&cru SRST_EDP>;
1153 reset-names = "edp_24m", "edp_apb";
1154 status = "disabled";
1159 compatible = "rockchip,iep_mmu";
1160 reg = <0x0 0xff900800 0x0 0x100>;
1161 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1162 interrupt-names = "iep_mmu";
1163 status = "disabled";
1168 compatible = "rockchip,vip_mmu";
1169 reg = <0x0 0xff950800 0x0 0x100>;
1170 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1171 interrupt-names = "vip_mmu";
1172 status = "disabled";
1175 vopb_mmu: vopb-mmu {
1177 compatible = "rockchip,vopb_mmu";
1178 reg = <0x0 0xff930300 0x0 0x100>;
1179 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1180 interrupt-names = "vop_mmu";
1181 status = "disabled";
1185 dbgname = "isp_mmu";
1186 compatible = "rockchip,isp_mmu";
1187 reg = <0x0 0xff914000 0x0 0x100>,
1188 <0x0 0xff915000 0x0 0x100>;
1189 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1190 interrupt-names = "isp_mmu";
1191 status = "disabled";
1194 hdcp_mmu: hdcp-mmu {
1195 dbgname = "hdcp_mmu";
1196 compatible = "rockchip,hdcp_mmu";
1197 reg = <0x0 0xff940000 0x0 0x100>;
1198 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1199 interrupt-names = "hdcp_mmu";
1200 status = "disabled";
1203 hevc_mmu: hevc-mmu {
1205 compatible = "rockchip,hevc_mmu";
1206 reg = <0x0 0xff9a0440 0x0 0x40>,
1207 <0x0 0xff9a0480 0x0 0x40>;
1208 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1209 interrupt-names = "hevc_mmu";
1210 status = "disabled";
1215 compatible = "rockchip,vpu_mmu";
1216 reg = <0x0 0xff9a0800 0x0 0x100>;
1217 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1218 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1219 interrupt-names = "vepu_mmu", "vdpu_mmu";
1220 status = "disabled";